BOOLEAN ALGEBRA AND LOGIC GATES

Background

George Boole, a nineteenth-century English Mathematician, developed a system of

logical algebra by which reasoning can be expressed mathematically. In 1854,
Boole published a classic book, “An Investigation of the Laws of thought” on which he
founded the Mathematical theories of Logic and Probabilities,

Boole's system of logical algebra, now called Boolean algebra, was investigated as a
tool for analyzing and designing relay switching circuits by Claude E. Shannon at
the Massachusetts institute of Technology in 1938. Shannon, a research assistant
in the Electrical Engineering Department, wrote a thesis entitled "A symbolic Analysis
of Relay and Switching Circuits". As a result of his work, Boolean algebra is now, used
extensively in the analysis and design of logical circuits. Today Boolean algebra is the
backbone of computer circuit analysis.

1.1 Introduction
In Boolean algebra, the variables (known as Boolean variables) are allowed to have
only two possible values, usually denoted as 0 and 1, unlike ordinary algebra where
variables can take on infinitely many values.
In Boolean algebra, we can have expressions such as:

x = f (A, B)

which is read as “x is a function of variables A and B”. A and B are Boolean variables
and can only take on two possible values, 0 or 1. f () is the Boolean operation on the
variables.

1.2 Basic Operations of Boolean Algebra

Boolean algebra has only 3 basic operations:

i) Logical addition (the OR operation), Symbol +

ii) Logical multiplication (the AND operation), Symbol ·

iii) Logical complementation (the NOT operation). Different books have different
symbols for this operation, including ∗ , 0 and¯

Any Boolean function, however complex, can be broken down to a combination of these
three operations.

Page 1
1.2.1 The OR operation

This operation operates on two or more variables. The expression:

x=A+B

is read as “x equals A OR B”. We can write the operation of the 2-variable in the
form of a table as shown below:
A B x
0 0 0
0 1 1
1 0 1
1 1 1
A table, such as the one above, which shows how a logic circuit’s outputs respond to
various combinations of logic levels at the inputs is known as a truth-table.
From the truth-table above, we can write that:
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
In general, a truth-table of m inputs has 2m input combinations e.g. a 3-input OR
operation (for the operation x = A + B + C) has 23 = 8 input combinations, and it is
shown on the table below:
A B C x
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
The OR operation is implemented using an OR gate. The Figure 2.1 shows a 2-input
OR gate and a 3-input OR gate.
In general, the OR operation produces a result of 1 when any of the input variables
is 1. The OR operation produces a result of zero only when all the input variables are
0.

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PSfrag replacements
A A
x B x
B C
2−input OR gate 3−input OR gate

Figure 2.1: 2 and 3 input OR gates

1.2.2 The AND operation

This operates on two or more variables. The expression:

x=A·B

is read as “x = A AND B”. Note that in most cases, the dot between A and B is
omitted and the expression simply written as x = AB. The truth-table for the 2-
input AND operation is shown below:
A B x
0 0 0
0 1 0
1 0 0
1 1 1
The AND operation is implemented using an AND gate, and Figure 2.2 shows a 2-
input and 3-input AND gate.
PSfrag replacements
A A
x B x
B
C
2−input AND gate 3−input AND gate

Figure 2.2: 2 and 3 input AND gates

For the AND operation, an output equal to 1 occurs only for the single case when all
the inputs are 1. The output is 0 for any case where one or more inputs are 0.

1.2.3 NOT operation

The inputs have to be reduced to a single variable before a NOT operation can be
performed. It is the inversion or complementation function.
If this operation is to be applied on a variable A, we can then write:

x=A

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which is read as “x = NOT A”. The truth-table for this is shown below:
A x
0 1
1 0

This means that 0 = 1 (NOT ‘0’ = ‘1’) and 1 = 0 (NOT ‘1’ = ‘0’). Note also that 0 = 0
and 1 = 1.
The NOT operation is implemented using a NOT gate, illustrated on Figure 2.3. The
NOT gate is also known as an inverter.
PSfrag replacements
A A

Figure 2.3: A NOT gate (inverter)

1.3 Other Logic Gates

1.3.1 The NOR gate

For two variables A and B, the NOR operation is defined as:

x=A+B

In this case, we read this as “x equals NOT (A OR B). This case is equivalent to a
2-input OR gate and an inverter connected in series. The symbol for a 2-input NOR
gate is shown on Figure 2.4.
PSfrag replacements
A
A+B

Figure 2.4: A 2-input NOR gate

The truth-table for a 2-input NOR gate is shown below:

A B x
0 0 1
0 1 0
1 0 0
1 1 0

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1.3.2 The NAND gate

For three variables A, B and C, the NAND operation is defined as:

x=A·B·C

In this case, we read this as “x equals NOT (A AND B AND C). This is equivalent
to a 3-input AND gate and an inverter connected in series. The symbol for a 3-input
NAND gatePSfrag replacements
is shown on Figure 2.5.

A
A·B·C
B
C

Figure 2.5: A 3-input NAND gate

The truth-table for a 3-input NAND gate is shown below:

A B C x
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

1.3.3 The Exclusive-OR gate

For variables A and B, the Exclusive-OR function is defined as:

x=A⊕B

and the truth-table is shown below:

A B x
0 0 0
0 1 1
1 0 1
1 1 0
The Exclusive-OR operation is sometimes abbreviated as XOR or EXOR. The opera-
tion is implemented using an Exclusive-OR gate, illustrated on Figure 2.6.
Note that the XOR gate has only two inputs.

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 PSfrag replacements
A
A⊕B

Figure 2.6: An Exclusive-OR gate

1.3.4 The Exclusive-NOR gate

This is usually abbreviated as XNOR or EXNOR gate. It is the complement of the XOR
operation. For variables A and B,

x=AB =A⊕B

and the truth-table is shown below:

A B x
0 0 1
0 1 0
1 0 0
1 1 1
The operation is implemented using an Exclusive-NOR gate, illustrated on Figure 2.7.

PSfrag replacements
A
A⊕B

Figure 2.7: An Exclusive-NOR gate

Just as for the XOR gate, the XNOR gate has only two inputs.

1.4 Laws of Boolean Algebra

Basic Theorems
A+0=A A·1 =A
A+1=1 A·0=0
A+A=A A·A=A
A + Ā = 1 A · Ā = 0
Looking at the above table, we can see that the corresponding laws on either side are
related by:

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 i) Interchanging + and · symbols

ii) Interchanging 0 and 1

Theorems which are related to another by this double interchange are known as
duals.
Other theorems, each listed along with its dual, are tabulated below:

1: A+B = B +A A·B =B·A

2: A + (B + C) = (A + B) + C A · (B · C) = (A · B) · C
3: A + B · C = (A + B) · (A + C) A · (B + C) = A · B + A · C
4: A+A·B = A A · (A + B) = A
5: A+A·B =A+B A · (A + B) = A · B
6: A·B+A·B =A (A + B) · (A + B) = A
7: A · B + A · C = (A + C) · (A + B) (A + B) · (A + C) = A · C + A · B
8: A·B +A·C +B ·C = A·B+A·C (A + B) · (A + C) · (B + C) = (A + B) · (A + C)
9: A + B + C +··· = A · B · C ··· A · B · C ··· = A +B + C + ···
Law 1 is the commutative law, 2 the associative law, 3 the distributive law, 4 is
commonly referred to as the absorption theorem, 5 the simplification theorem, 6 the
reduction theorem and 9 are the De Morgan’s Theorems.

1.5 Proving Boolean Theorems

The theorems above may be proved by use of truth-table or by algebraic means.

1.5.1 Proof by truth-table

Example
Use a truth-table to prove that AB + AC + BC = AB + AC.
Solution:

A B C AB AC BC AB + AC + BC AB + AC
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 1
0 1 0 0 0 0 0 0
0 1 1 0 1 1 1 1
1 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 1 0 1 1 1

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Looking at the table above, we can see that the columns for AB + AC + BC and
AB + AC are identical so the two expressions are equivalent. This has been shown
by means of a truth-table. Proving Boolean expressions by use of truth-table is known
as proof by perfect induction.

1.5.2 Proof by Algebraic means

This requires a masterly of the laws of Boolean algebra so a lot of practice is needed
to be able to use this technique effectively.
Example
Use algebraic means to show that A + A · B = A
Solution:
A+A·B =A·1+A·B
= A · (1 + B) = A · 1 = A

Example
Use algebraic means to show that A + A · B = A + B
Solution:
A+A·B =A+A·B +A·B
= A + (A + A) · B = A + B · (1)
=A+B

1.6 Standard Forms for Boolean Functions

There are two standard forms for Boolean expressions: Standard sum of products
form and Standard product of sums form.

1.6.1 Standard Sum of Products form

Given a function:
f (A, B, C) = (AB + C)(B + AC)
we can use the distributive rule (informally known as opening the brackets) to write:

f (A, B, C) = ABB + CB + ABAC + CAC

By use of Boolean rules, we can simplify the above expression to:

f (A, B, C) = AB + BC + ABC + AC

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From the expression above, the terms AB, BC, ABC and AC are products, and
they are all combined with an OR operation (logical addition or summation) so the
expression is said to be in Sum of Products form. (Note however that expressions like
ABC + ABC are not in Sum of Products form since the inversion signs cover more
than one variable).
Now consider the expression we obtained above:

f (A, B, C) = AB + BC + ABC + AC

This is a function of variables A, B and C, but not all the product terms contain all
these variables e.g. the product term AB lacks the variable C, BC lacks the variable
A, and so on. To express the function in Standard Sum of Product form, we must add
the missing variables to all the product terms so that every variable appears in each
product term (either in its true form or in its complement form). To do this, we use
the Boolean algebra laws:

(A + A) = 1 and A·1=A

We can then write the above expression as:

f (A, B, C) = AB(C + C) + (A + A)BC + ABC + AC(B + B)

= ABC + ABC + ABC + ABC + ABC + ABC + ABC

= ABC + ABC + ABC + ABC
This form, in which a sum of products appears, each term involving all variables is
called the Standard Sum of Products form or Canonical Sum of Products form. Each
individual term in the expression is known as a minterm, e.g. ABC is a minterm.
Each minterm will have a logical value of 1 only when all the terms have a logical
value of 1 e.g. minterm ABC will have a logical value of 1 only when A = B = C =
1, AB C = 1 only if A = B = C = 1 (A = 1, B = 1, and C = 0) e.t.c. The table below
shows the minterms of the 3 variables A, B and C.
A B C minterm
0 0 0 m0 = ĀB̄ C̄
0 0 1 m1 = ĀB̄C
0 1 0 m2 = ĀB C̄
0 1 1 m3 = ĀBC
1 0 0 m4 = AB̄ C̄
1 0 1 m5 = AB̄C
1 1 0 m6 = AB C̄
1 1 1 m7 = ABC

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Going back to the function we started off with and using the above table, we can
write:
f (A, B, C) = m7 + m6 + m3 + m5
Sometimes the above expression is written as:

f (A, B, C) = Σm(3, 5, 6, 7)

1.6.2 Standard Product of Sums form

Given a function:
f (A, B, C) = (AB + C)(B + AC)
we can use the distributive rule to write:

f (A, B, C) = (A + C)(B + C)(B + A)(B + C)

= (A + B)(A + C)(B + C)
The above expression is said to be in product of sums form. To convert this to the
Standard product of sums form, we add the missing variables in each term, using the
Boolean rules:
A·A=0 and (A + 0) = A
We can therefore write:

f (A, B, C) = (A + B + C C̄)(A + B B̄ + C)(AĀ + B + C)

Again using the distributive rule:

f (A, B, C) = (A + B + C)(A + B + C̄)(A + B + C)(A + B̄ + C)(A + B + C)(Ā + B + C)

f (A, B, C) = (A + B + C)(A + B + C̄)(A + B̄ + C)(Ā + B + C)

This is known as the Standard Product of Sums form or Canonical Product of Sums
form. Each of the factors in the expression above is known as a maxterm, e.g. A +
B + C is a maxterm. Each maxterm will have a logical value 0 only when all the
terms in it have a logical value 0, e.g. maxterm (A + B̄ + C) will have a logical value
0 when A = 0, B = 1 and C = 0.
The table below shows the maxterms of the 3 variables A, B and C.

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 A B C maxterm
0 0 0 M0 =A+B+C
0 0 1 M1 = A + B + C̄
0 1 0 M2 = A + B̄ + C
0 1 1 M3 = A + B̄ + C̄
1 0 0 M4 = Ā + B + C
1 0 1 M5 = Ā + B + C̄
1 1 0 M6 = Ā + B̄ + C
1 1 1 M7 = Ā + B̄ + C̄
We can therefore write:

f (A, B, C) = M0 · M1 · M2 · M4

Sometimes this is written as:

f (A, B, C) = ΠM (0, 1, 2, 4)

1.7 Simplification of Boolean Expressions

Introduction

Suppose you wanted to implement the Boolean function:

 
x = AB A + BC
We can implement this directly as shown on Figure 3.1.

B x
PSfrag replacements
C

Figure 1.7a: Circuit for the unsimplified expression

This implementation requires a total of five gates.

Suppose now we decided to simplify the expression before implementing it. We first
use De Morgan’s theorems to get:
 
x = AB A · BC

Page 11


= AB A(B + C)


= AB AB + AC
= ABAB + ABAC
= AB C
This canPSfrag
be implemented using only two gates, as shown on Figure 3.2.
replacements
A
B x
C

Figure 1.7b: Circuit for the simplified expression

Generally, it is necessary to reduce Boolean expressions before implementing them

as it makes the final circuit:

i) cheaper - less gates used, needs a smaller circuit board.

ii) more reliable as there are fewer interconnections.

iii) have a lower power consumption.

There are two methods of simplifying logic expressions:

i) Algebraic Simplification - Uses theorems of Boolean Algebra.

ii) The Karnaugh map method - Graphical.

1.7.1 Algebraic Simplification

i) Put the expression in Sum of Products form (not Standard Sum of Products
form). This may require the use of De Morgan’s theorem or the distributive
rules.

ii) Check for common factors and factor out whenever possible. Factoring usually
results in the elimination of some of the terms.

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Example
Simplify algebraically:
ABC + AB C̄ + AB̄C
The expression is already in sum of products form, so we shall just factor out the
expression:


ABC + AB C̄ + AB̄C = AB C + C̄ + AB̄C


= AB + AB̄C = A B + B̄C
= A (B + C) = AB + AC
Example
Simplify algebraically:  
x = ABC + AB ĀC̄
This expression is not in sum of products form, so we shall first apply De Morgan’s
Theorems to get:

 
x = ABC + A + B A + C


= ABC + A + B (A + C)
= ABC + AC + AB + BC
Now the expression is in sum of products form, so we can proceed with the simplifi-
cation:


x = C A + AB + AB + BC


= C A + B + AB + BC
= AC + BC + BC + AB


= AC + B + B C + AB
= AC + C + AB
= C + AB
Example
A student may register for course X only if he satisfies the following conditions:

(1) Has completed at least 20 courses AND is an engineering student AND of good
conduct, OR

(2) Has completed at least 20 courses AND is an engineering student AND has
departmental approval, OR

(3) Has completed fewer than 20 courses AND is an engineering student AND not
of good conduct, OR

(4) Is of good conduct AND has departmental approval, OR

Page 13
 (5) Is an engineering student AND does not have departmental approval.

We can convert the conditions listed to letter symbols as follows:

A: Has completed at least 20 courses

B: Is an engineering student

C: Is of good conduct

D: Has departmental approval

Y: Student may register for course X

We can then write:

Y = ABC + ABD + AB C + CD + B D


= ABC + B D + AD + AB C + CD + B D


= ABC + B D + A + AB C + CD
= (ABC + AB) + B D + AB C + CD
= AB + AB C + B D + CD


= B A + ĀC̄ + B D + CD


= B A + C + B D + CD


= AB + B C + B D + CD
Recall the theorem:
AB + AC + BC = AB + AC
We can use this theorem to rewrite the expression in brackets above as:

BD + CD = BD + CD + BC

Hence:
Y = AB + B C + B D + CD + BC


= AB + B C + C + B D + CD
= AB + B + B D + CD
= B + B D + CD
= B + CD
Hence a student may register for the course X if he is an engineering student OR he
is of good conduct AND has departmental approval.

Page 14
1.7.2 The Karnaugh Map

Introduction

This is a graphical method used to simplify a Boolean expression. It represents the

information in a truth-table in a different format. Each combination of inputs is
represented by a cell in the map.
Once a Karnaugh Map (K-map) has been filled with ones and zeros, the sum of prod-
ucts expression can be obtained by ORing together the those squares that contain 1s.
The product of sums expression can be obtained by ANDing together those squares
that contain 0s.

Two variable K-map

Consider the 2-variable truth-table shown below:

A B x minterm
0 0 1 m0
0 1 1 m1
1 0 0 m2
1 1 0 m3
(This
PSfragtruth-table is arbitrarily chosen - it is for purposes of illustration only). There
replacements
are four input combinations, so this truth-table can be converted to a K-map with 4
cells, as shown on Figure 3.3. Note that in this case, variable A is treated as the MSB.

A A
B 0 1 B 0 1
0 m0 m2 0 1 0

1 m1 m3 1 1 0

Figure 3.3: Two variable K-map

The K-map may be alternatively drawn with the variable A on the vertical side and
variable B on the horizontal side, as shown on Figure 3.4:

3-variable K-map

Consider the 3-input truth-table shown below:

Page 15
 PSfrag replacements

B B
A 0 1 A 0 1
0 m0 m1 0 1 1
PSfrag replacements 1 m2 m3 1 0 0

Figure 3.4: Two variable K-map: alternative representation

A B C x minterm
0 0 0 1 m0
0 0 1 1 m1
0 1 0 1 m2
0 1 1 0 m3
1 0 0 0 m4
1 0 1 0 m5
1 1 0 1 m6
1 1 1 0 m7

This can be represented using a K-map as shown on Figure 3.5.

AB AB
C 00 01 11 10 C 00 01 11 10
0 m0 m2 m6 m4 0 1 1 1 0
PSfrag replacements
1 m1 m3 m7 m5 1 1 0 0 0

Figure 3.5: Three variable K-map

Note that the K-map cells are labelled in such a way that adjacent cells differ only in
one variable.
The 3-variable K-map may be alternatively drawn as shown on Figure 3.6.

C C
AB 0 1 AB 0 1
00 m0 m1 00 1 1

01 m2 m3 01 1 0

11 m6 m7 11 1 0

10 m4 m5 10 0 0

Figure 3.6: Three variable K-map: alternative representation

Note that the two representations shown (Figure 3.5 and Figure 3.6) are equivalent,
and you may work with whichever representation that you are more comfortable

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 with. The only thing you should keep in mind is the order in which the variables
appear – in this case, they appear in the order A (MSB), B and C (LSB).
PSfrag replacements
4-variable K-map

Consider the 4-input truth-table shown below:

A B C D x minterm
0 0 0 0 0 m0
0 0 0 1 1 m1
0 0 1 0 0 m2
0 0 1 1 0 m3
0 1 0 0 0 m4
0 1 0 1 1 m5
0 1 1 0 0 m6
0 1 1 1 0 m7
1 0 0 0 0 m8
1 0 0 1 0 m9
1 0 1 0 0 m10
1 0 1 1 0 m11
1 1 0 0 0 m12
1 1 0 1 1 m13
1 1 1 0 0 m14
1 1 1 1 1 m15

This may be represented using a K-map as shown on Figure 3.7.

AB AB
CD 00 01 11 10 CD 00 01 11 10
00 m0 m4 m12 m8 00 0 0 0 0

01 m1 m5 m13 m9 01 1 1 1 0

11 m3 m7 m15 m11 11 0 0 1 0

10 m2 m6 m14 m10 10 0 0 0 0

Figure 3.7: Four variable K-map

The K-map may be alternatively drawn as shown on Figure 3.8.

1.7.3 Looping

The Logic function can be simplified by properly combining those squares in the that
contain 1s. The process of combining 1s is called looping. The number of 1s that can
be looped together should be a power of 2 (1, 2, 4, 8, 16 e.t.c.).

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 CD CD
AB 00 01 11 10 AB 00 01 11 10
00 m0 m1 m3 m2 00 0 1 0 0

01 m4 m5 m7 m6 01 0 1 0 0

11 m12 m13 m15 m14 11 0 1 1 0

10 m8 m9 m11 m10 10 0 0 0 0

Figure 3.8: Four variable K-map: alternative representation

Groups of 2 (Pairs)

Two ones can be looped together if they are horizontally or vertically adjacent. Two
PSfrag replacements
ones next to each other diagonally are not adjacent. Looping a pair of adjacent 1s in a
K-map eliminates the variable that appears in the complemented and uncomplemented form.
Variables that are the same C
for all cells of the loop must appear in the final expression.
Example
Consider the K-map shown on Figure 3.9.

AB
C ĀB̄ ĀB AB AB̄
C̄ 0 1 1 0

C 0 0 0 0

Figure 3.9: Looping two 1s which are horizontally adjacent

The two 1s shown in the K-map are horizontally adjacent and can be looped together
as a pair as shown in the figure. Looking at the cells enclosed in the loop, we can
see that variable A appears as Ā in one cell (complemented form) and as A (uncom-
plemented form) in the other cell hence it is eliminated. Variable B appears as B in
both cells and variable C appears as C̄ so the simplified expression is:

x = B C̄

Example
Consider the K-map shown on Figure 3.10.
The two ones are vertically adjacent and the variable C is the one that changes and
is eliminated hence:
x = ĀB

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 C

AB
C ĀB̄ ĀB AB AB̄
C̄ 0 1 0 0

C 0 1 0 0

Figure 3.10: Looping two 1s which are vertically adjacent

PSfrag replacements
The leftmost column and the rightmost column of the K-map are considered to be
adjacent. Similarly, the top row and the bottom row of a K-map are considered to be
adjacent. C

Example
Consider the K-map shown on Figure 3.11.

AB
C ĀB̄ ĀB AB AB̄
C̄ 1 0 0 1
C 0 0 0 0

Figure 3.11: Looping two 1s which are horizontally adjacent

In this case,
x = B̄ C̄

Groups of 4 (Quads)

Four 1s PSfrag
can be replacements
looped together if they are horizontally adjacent, vertically adjacent
or form a square. A loop of four 1s eliminates 2 variables that appear in both com-
plemented and uncomplemented
C form.
Example
Consider the K-map shown on Figure 3.12.

AB
C ĀB̄ ĀB AB AB̄
C̄ 0 0 0 0

C 1 1 1 1

Figure 3.12: Looping four 1s which are horizontally adjacent

Page 19
The four 1s are horizontally adjacent and are looped together to give:
PSfrag replacements
x=C

Example
Consider the K-map shown on Figure 3.13.

AB
CD ĀB̄ ĀB AB AB̄
C̄ D̄ 0 1 0 0

C̄D 0 1 0 0

CD 0 1 0 0

C D̄ 0 1 0 0

Figure 3.13: Looping four 1s which are vertically adjacent

The four 1s are vertically adjacent and are looped together to give:
PSfrag replacements
x = ĀB

Example

AB
CD ĀB̄ ĀB AB AB̄
C̄ D̄ 0 1 1 0

C̄D 0 1 1 0

CD 0 0 0 0

C D̄ 0 0 0 0

Figure 3.14: Looping four 1s which form a square

The four 1s in Figure 3.14 form a square and are looped together to give:

x = B C̄

Other examples of quads are shown on Figure 3.15, where x = B̄D for the K-map on
the left and x = B D̄ for the K-map on the right.

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 AB AB
CD ĀB̄ ĀB AB AB̄ CD ĀB̄ ĀB AB AB̄
C̄ D̄ 0 0 0 0 C̄ D̄ 0 1 1 0
C̄D 1 0 0 1 C̄D 0 0 0 0
PSfrag replacements
CD 1 0 0 1 CD 0 0 0 0
C D̄ 0 0 0 0 C D̄ 0 1 1 0

Figure 3.15: Looping four 1s

AB
CD ĀB̄ ĀB AB AB̄
C̄ D̄ 1 0 0 1
C̄D 0 0 0 0
CD 0 0 0 0
C D̄ 1 0 0 1

Figure 3.16: The 1s at the corners are adjacent and can looped together

Since the top row of a K-map is adjacent to the bottom row, and the right column to
the left, the corner cells of a K-map are also considered adjacent and can be looped
together if they all contain 1s, as shown on Figure 3.16.
PSfragInreplacements
this case, x = B̄ D̄.

Groups of 8 (octets)

Eight ones may be looped together if they are adjacent. A loop of eight 1s eliminates
3 variables. Examples of octets are shown on Figure 3.17.

AB AB
CD ĀB̄ ĀB AB AB̄ CD ĀB̄ ĀB AB AB̄
C̄ D̄ 1 1 0 0 C̄ D̄ 1 1 1 1
C̄D 1 1 0 0 C̄D 0 0 0 0
CD 1 1 0 0 CD 0 0 0 0
C D̄ 1 1 0 0 C D̄ 1 1 1 1

x = Ā x = D̄

Figure 3.17: Looping eight 1s (octets)

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1.7.4 Complete Simplification Procedure

1. Construct the K-map and place 1s in those cells corresponding to 1s in the

truth-table. Place 0s in the other squares.

2. Examine the map and loop those 1s which are not adjacent to any other 1s.
these are called isolated 1s.

3. Identify those 1s that are adjacent to only one other 1. Loop any pair containing
such a 1. Adjacent ones which can be combined in more than one way are
temporarily bypassed.

4. Identify those 1s which can be combined with three other 1s in only one way.
If not all four 1s so involved have already been looped as pairs, loop the four
1s. The 1s that can be looped in a group of four in more than one way are
temporarily bypassed.

5. Repeat the preceding steps for groups of 8, 16 e.t.c.

6. Loop any quad that contains one or more 1s that have not yet been looped.

7. Loop any pairs necessary to include any 1s that have not yet been looped, mak-
ing sure to use the minimum number of loops.

8. Form the OR sum of all the terms generated by each loop.

Note: If the expression you obtain using the steps above can be simplified further by
algebraic means, it means you have not looped properly - you may be using too many
loops and/or your loops may not be large enough.
Carefully go through the examples below, and see if you can come up with the same
loops. These examples have been looped in such a way as to obtain the simplest
possible expressions.
Example

From Figure 3.18, x = AB̄ C̄ D̄ + ABC + BD

Example

From Figure 3.19, x = ĀB C̄ + AC̄D + ABC + ĀCD

Example

From Figure 3.20, x = ĀBC D̄ + ĀB̄ C̄ + AB C̄ + C̄D + B̄D + AD

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 PSfrag replacements

AB
CD ĀB̄ ĀB AB AB̄
C̄ D̄ 0 0 0 1

C̄D 0 1 1 0
PSfrag replacements CD 0 1 1 0

C D̄ 0 0 1 0

Figure 3.18: Example

AB
CD ĀB̄ ĀB AB AB̄
C̄ D̄ 0 1 0 0

C̄D 0 1 1 1
PSfrag replacements
CD 1 1 1 0

C D̄ 0 0 1 0

Figure 3.19: Example

AB
CD ĀB̄ ĀB AB AB̄
C̄ D̄ 1 0 1 0
C̄D 1 1 1 1
CD 1 0 1 1
C D̄ 0 1 0 0

Figure 3.20: Example

1.7.5 Obtaining Product of Sums Expressions from K-maps

So far, we have talked about obtaining Sum of Products expressions from K-maps. It
is also possible to obtain Product of Sums expressions – only this time we loop the
zeros together, not the ones. The examples below illustrate the procedure.
Example

From Figure 3.21, x = B̄ + C̄ + D̄ A + D̄
Example

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 AB
CD 00 01 11 10
00 1 1 1 1

01 0 0 1 1

11 0 0 0 1

10 1 1 1 1

Figure 3.21:replacements
PSfrag Example: looping the 0s to obtain a product of sums expression
AB
CD 00 01 11 10
00 0 0 1 1

01 1 0 0 1

11 0 0 0 0

10 1 0 0 1

Figure 3.22: Example: looping the 0s to obtain a product of sums expression

From Figure 3.22, x = (A + C + D) B̄ + D̄ C̄ + D̄ B̄ + C̄

Note that for a given K-map, looping the 1s and looping the zeros gives the same results,
only that the results are expressed in different ways. Consider the example shown on
PSfragFigure 3.23 where in one case the 1s are looped and in the other case the 0s are
replacements
looped.

AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 0 1 1 1 01 0 1 1 1
11 0 1 1 1 11 0 1 1 1
10 0 1 1 1 10 0 1 1 1

Figure 3.23: Example: looping 0s or 1s gives same result expressed in different ways

The Sum of Products expression obtained by looping the 1s is:

x = AD + BD + BC + AC

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 while the Product of Sums expression obtained by looping 0s is:

x = (C + D) (A + B)

Opening the brackets of the Product of Sums expression will yield the Sum of Prod-
ucts expression obtained by looping the 1s, showing the two expressions are equiva-
lent.

1.8 Don’t Care Terms

These are also referred to as Unused terms, Forbidden terms or Redundant terms.
These terms describe combinations of variables which never occur in practice. In a
truth-table or a K-map, these inputs are represented by an X, an R or a d. As an
example, suppose that we have a digital circuit with three inputs and one output,
and the input combinations 000, 001 and 010 give an output 0, input combinations
101, 110 and 111 give an output 1, and input combinations 011 and 100 never occur
in practice. The truth-table for this circuit is as shown below:

A B C output
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 X
1 0 0 X
1 0 1 1
1 1 0 1
PSfrag replacements
1 1 1 1
When designing with K-maps containing don’t care variables, the designer can make
the output of any don’t care condition either a 1 or a 0 in order to produce the sim-
plest output expression. This is illustrated on Figure 3.24 for the truth-table above.

AB AB
C ĀB̄ ĀB AB AB̄ C ĀB̄ ĀB AB AB̄
C̄ 0 0 1 X C̄ 0 0 1 1

C 0 X 1 1 C 0 0 1 1

x = Ā

Figure 3.24: Example: simplifying a Boolean expression with don’t care terms

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1.9 NAND/NOR gate circuit implementation
To implement a logic circuit using NAND gates only:

1. Derive the minimized expression for the function in sum of products form (ob-
tained by minimizing Boolean expressions algebraically or by looping 1s in a
K-map).

2. Apply double negation and De Morgan’s theorem to convert the expression in

a form suitable for NAND gate implementation.

As an example, suppose a design problem resulted in a minimized sum of products

expression:
x = AB + BC + AC
and we were to implement this expression using NAND gates only, we then apply the
above steps as follows:

x = AB + BC + AC = AB + BC + AC

= AB · BC · AC
which is implemented as shown on Figure 3.25.

A
PSfrag replacements
B x

Figure 3.25: Example: implementation using NAND gates only

To implement a logic circuit using NOR gates only:

1. Derive the minimized expression for the function in product of sums form (ob-
tained by looping the 0s in a K-map).

2. Apply double negation and De Morgan’s theorem to convert the expression in

a form suitable for NOR gate implementation.

As an example, suppose a design problem resulted in a minimized product of sums

expression:
x = (A + B) (B + C) (A + C)

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and we were to implement this expression using NOR gates only, we then apply the
above steps as follows:

x = (A + B) (B + C) (A + C) = (A + B) (B + C) (A + C)

= (A + B) + (B + C) + (A + C)
which is implemented as shown on Figure 3.26.

A
PSfrag replacements
B x

Figure 3.26: Example: implementation using NOR gates only

1.10 Combinational Logic Circuit Design

Introduction

SSI Small Scale Integration - Digital ICs with less than 12 gates

MSI Medium Scale Integration - Digital ICs with 12 to 99 gates

LSI Large Scale Integration - Digital ICs with 100-9999 gates

VLSI Very Large Scale Integration - More than 10000 gates

A Combinational logic circuit is a logic circuit whose outputs are functions of the
present inputs only. It cannot ‘remember’ the effects of the previous inputs.

1.10.1 Design Procedure

1. Derivation of the truth-table.

– Understand the problem

– Define the input variables
– Define the output variables
– Relate the output variables to the input variables using a truth-table

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 2. Derivation of Boolean expressions from the truth-table.

– Outputs are expressed as functions of the input variables.

3. Minimization (or Simplification) of the expressions for outputs.

– Done to minimize the number of gates used in the design and hence min-
imize costs, reduce power consumption and increase circuit reliability.

Note: Use of a K-map makes it possible to combine steps 2 and 3 above.

4. Conversion of the minimized expressions to the form that allows the implemen-
tation of the circuit using the available gates.

– In some cases, we might want to implement the circuit using AND-OR-

NOT logic, NAND gates only or NOR gates only. The expression(s) ob-
tained at step 3 can be implemented directly using AND-OR-NOT logic
(using a combination of AND, OR and NOT logic gates). However, AND-
OR-NOT logic design requires three different types of ICs, all of which may
not be available at the time of the design, and in many cases, AND-OR-
NOT logic design leads to the use of a large number of logic gates, so it is
usually preferred to implement the circuits using NAND gates only or NOR
gates only. The expression obtained in step 3 then needs to be converted
to a form suitable for implementation using these gates.

5. Implementation of the circuit.

1.10.2 Examples and exercises

Example

+5V
R

SW1
+5V
R

SW2 COMBINATIONAL LED

+5V
LOGIC
R
CIRCUIT
SW3
+5V
R
SW4

Figure 3.27: Example: combinational logic circuit design

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Figure 3.27 shows four switches that are part of a control circuitry in a copy machine.
The switches are at various points along the path of the copy paper as the paper
passes through the machine. Each switch is normally open and as the paper passes
over a switch, the switch closes. It is impossible for switches SW1 and SW4 to be
closed at the same time (they are far apart and the paper cannot cover them at
the same time). The LED is to light if two or more switches are closed. Design a
combinational logic circuit for the system.
Solution
The inputs in this case are switches SW1, SW2, SW3 and SW4. We shall denote
these switches as A, B, C and D respectively. Note that if a switch is open, the
corresponding input to the circuit is HIGH (Logic 1), and if a switch is closed, the
corresponding input is LOW (Logic 0). The output of the circuit is denoted as z (and
the state of this output is visually indicated by the LED): when two or more switches
closed, the output of the circuit should be HIGH (LED is LIT), otherwise the output
should be 0 (LED NOT LIT). The truth-table for the circuit is shown below:
A B C D z
0 0 0 0 X
0 0 0 1 1
0 0 1 0 X
0 0 1 1 1
0 1 0 0 X
0 1 0 1 1
0 1 1 0 X
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
PSfrag replacements 1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

The K-map corresponding to this is shown on Figure 3.28.

AB
CD ĀB̄ ĀB AB AB̄
C̄ D̄ X X 1 1

C̄D 1 1 0 1

CD 1 0 0 0

C D̄ X X 0 1

Figure 3.28: K-map corresponding to the truth table

Figure 3.29 shows the best way to convert the don’t care variables to 1s and 0s,
achieving the biggest loops possible, and minimizing the number of loops used. The
loops have been made to obtain the minimized sum of products expression.

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 PSfrag replacements

AB
CD ĀB̄ ĀB AB AB̄
C̄ D̄ 1 1 1 1
C̄D 1 1 0 1
CD 1 0 0 0
C D̄ 1 0 0 1

Figure 3.29: Simplification of the Boolean function

From Figure 3.29, we can write:

z = B̄ D̄ + C̄ D̄ + ĀB̄ + ĀC̄ + B̄ C̄

For NAND gate implementation,

z = B̄ D̄ + C̄ D̄ + ĀB̄ + ĀC̄ + B̄ C̄
PSfrag replacements
 
= B̄ D̄ · C̄ D̄ · ĀB̄ · ĀC̄ · B̄ C̄

For implementation using NOR gates only, a simplified product of sums expression is
required, and this is obtained by looping the zeros as shown on Figure 3.30.
AB
CD ĀB̄ ĀB AB AB̄
C̄ D̄ 1 1 1 1

C̄D 1 1 0 1

CD 1 0 0 0

C D̄ 1 0 0 1

Figure 3.30: Looping the 0s to obtain a simplified product of sums expression

From the figure,

z = Ā + B̄ + D̄ Ā + C̄ + D̄ B̄ + C̄

= Ā + B̄ + D̄ Ā + C̄ + D̄ B̄ + C̄




= Ā + B̄ + D̄ + Ā + C̄ + D̄ + B̄ + C̄

Example
Design a circuit to convert (4-bit) BCD code to Xs-3 code.

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Solution
The truth-table for this is shown below:
BCD CODE EXCESS-3 CODE
A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X

Do you understand how to derive the truth-table above? Complete the rest of the
exercise.
Exercise
A majority function combinational logic circuit is a circuit whose output is equal to
1 if the input variables have more ones than zeros. The output is zero otherwise.
Design a 4-input majority function combinational logic circuit and implement the
circuit using NAND gates only.
Exercise
In a certain corporation, the four board members A, B, C and D own all stock, which
is distributed as follows:
A: 40%

B: 30%

C: 20%

D: 10%

Each member has a percentage vote equal to his holdings and a total vote greater
than 50% is required to pass a motion. In the boardroom, each member is to have a
switch with which to indicate a YES or NO vote. A lamp is to light if the total vote
cast is more than 50% indicating the motion being voted on is passed. Design an
electronic voting system for the corporation and implement the circuit using:
i) NAND gates only.

ii) NOR gates only.

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 Exercise
Figure 3.31 shows a diagram for an automobile circuit used to detect certain unde-
sirable conditions. The 4 switches D, I, L and S are used to indicate the status of the
driver’s door, the ignition, the headlights and the driver’s seatbelt respectively. The
LED is to light under the following undesirable conditions:

(i) The headlights are ON while the ignition is OFF

(ii) The door is OPEN while the ignition is ON

(iii) The seatbelt is UNFASTENED while the ignition is ON.

Under any of these undesirable conditions, the logic circuit should produce a HIGH
output z to light the LED. Design a logic circuit to light the LED when an undesirable
condition occurs, and implement the circuit using

• NAND gates only.

• NOR gates only.

+5V
OPEN
DOOR (D)
CLOSED

+5V
ON
IGNITION (I)
OFF
LOGIC LED
z LED
+5V CIRCUIT driver
ON
LIGHTS (L)
OFF

+5V
FASTENED
PSfrag replacementsUNFASTENED SEATBELT (S)

Figure 3.31:

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