ELECTRICAL AND ELECTRONIC ENGINEERING

Intel 8086 Instruction

Format
The 8086 instruction size vary from 1-6 bytes as shown in figure 1(a)

Byte 1
 Occupies 6 bits defining the operation carried out by the instruction
 D bit defines whether operand in byte 2 is source or destination register. D=1, destination register.
 W word /byte operation. W=0 8 bit data hence 8 bit operation

Byte 2
 Contains three fields
o Mode (MOD): specifies whether operand is a register or memory. Refer figure 1 (b).
o Register (REG) defines the first operand which is specified by the D field as source or
destination. Refer figure 1 (c)
o R/M field together with MOD field defines the second field. Depending on the mode field,
R/M field will indicate the direction of the instruction will take. If MOD selects memory then
R/M indicates how the effective address will be calculated. Figure 2 gives the combinations of
byte 2 instruction formulations.
Byte 3 through 6
 Optional fields that normally contain the displacement value of the memory operand and /or the actual
value of an immediate constant operand.
Examples:
MOV CH, BL op-code=100010, if D=0 hence register specified by REG in byte 2 is a source
operand. In byte 2 since the second operand is a register then MOD=11 and R/M=101. The
instruction=10001001 11011101 (byte 1 byte 2) = 89DDH students to verify since solution is wrong

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Types

Intel 8086 categorises the instructions into six types namely Transfer, arithmetic, logic, jumps, misc and
processor control groups.
Transfer group: transfers data to or from registers from or to memory/ IO devices.
Arithmetic group:Does computational activities and any shifting or rotation required during computation.
Logic group: Does and logic operations required on operands
Jump / Loop group: Condition or unconditional jumps / loops as well as branching from the main program
belong to this group of instructions
Miscellaneous (Misc) gp: contains instructions like NOP (no operation), LEA (load effective address) and INT
(interrupt).
Processor control group: Used to directly control the state of some flags, to disable / enable interrupts and to
synchronise the processor to external peripherals. These instructions include; STC
(set carry flag), CLC (clear carry flag, CMC (complement the state of carry flag),
STD (set direction flag (DF) to 1 or decrement string pointer, WAIT, CLD, STI, CLI,
HLT, ESC, LOCK. Refer to instruction set provided.

Flowcharts
When a programmer is confronted by a complex task there is need to break down the task into smaller
manageable units. One method of breaking involves developing and outline of each unit. The outlines are then
sequenced to allow the problem be solved correctly. One method of outlining the problem is by use of
flowcharts. A flowchart is a block diagram using standard symbols to represent operations. Some of the symbols
are shown below.

Addressing Modes
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The power of any instruction set is based on the types of instructions and the number of addressing modes. The
8086 has 12 basic addressing modes that can be grouped into five namely:
1. Accessing immediate and register data (Register and immediate modes)
2. Accessing data in memory (Memory modes)
3. Accessing I/O ports (I/O modes)
4. Relative addressing mode
5. Implied addressing mode

Register and immediate modes

The register addressing mode uses registers as source and destination. Immediate addressing has the 8- or
16-bit data specified by the instruction. NB Even though the data is specified in the instruction, the data
must be located in the memory addressed by the 8086 CS and IP registers.

Memory modes
Execution unit (EU) has direct access to all registers and data for registers and immediate operands. However
the EU cannot access the memory operands. It must use the BIU. The BIU generates the physical address from
the effective and CS base address. There are six (6) addressing modes in this category.

1. Direct memory addressing

A 16-bit effective address is taken directly from the displacement field of the instruction. The
displacement may be 16-bit (unsigned) or 8-bit signed is stored in the location following the instruction
op-code. This EA is the distance of the memory location from the current value of the data segment.
Example
MOV [2000H],AX ;EA is 2000H being the OFFSET value in DS.

2. Register Indirect Addressing

In this mode, the EA is specified in either a pointer or an index register. Pointers are BX and BP while
Index registers are (SI) and (DI).
Example:
MOV [DI],BX ; The inst. Copies contents of BX (as register) into an EA location given by DI

3. Based Addressing
The EA is generated by adding a displacement (unsigned 16-bit or signed 8-bit) value to the contents of
BX or BP. The segment registers are DS and SS. When memory is accessed, use BX and DS while
when the Stack is accessed use BP and SS. The stack can be accessed by the programmer without
affecting its operations since SP is not interfered with.
Example:
MOV AL, ALPHA [BX] ;ALPHA is an 8-bit displacement while BX contains EA.

4. Indexed Addressing
The EA is calculated by adding a displacement (unsigned 16- or signed 8-bit) to the contents of DI or
SI
Example:
MOV BH, START [SI]; contents pointed by DS + EA (displacement START + SI) copied to
BH

5. Based Indexed Addressing

EA is computed by adding the base register (BX or BP), an Index register (SI or DI), and a
displacement (unsigned 16-or signed 8-bit).
Example:
MOV ALPHA [SI] [BX], CL.
Based Indexed addressing mode provides a convenient way for a subroutine to address an array
allocated on a stack.

** Forboth 4 and 5 addressing modes EA=RA+M where RA is reference address and M

the modifier.
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6. String Addressing
 Uses index registers. The string instructions assume SI to point to the first byte or word of the
source operand and DI to point to the first byte or word of destination operand. The contents of SI and
DI are automatically incremented (by clearing DF to 0 by CLD instruction) or decremented (by setting
DF to 1 by SRD instruction). Segment register for the source is DS but can be overridden while the
destination segment is ES that cannot be overridden. DI must always point to the destination operand.
 DF=0, [DS] =2000H, [SI]=0500H, [ES]=4000H, [DI]=0300H, 20500H=38H. The value 38H
is moved to (ES (40000 shifted 4 left) +DI (offset 0300H) 40300H

7. Input output (I/O) Addressing

There are two types of I/O addressing: Direct and Indirect.
Direct port mode
 The port number is an 8-bit immediate operand (0-255 access ports)
o Example: OUT 05H,AL; contents of AL output to 8-bit port 05H
Indirect port mode
 Port number is taken from DX allowing 64K 8-bit ports or 32K 16-bit ports
o Example: DX=5000H, then IN AL, DX; 8-bit contents
from 5000 port to AL. If instruction is: IN AX, DX; port
5000H and 5001 are loaded to AL and AH respectively.
 ** Any transfers must always use AL or AX.

8. Relative Addressing
This mode of addressing require a signed 8-bit displacement relative to PC
Example: JNC START; jump if no carry IP + 8-bit signed value of START. Otherwise next
instruction is executed.

9. Implied Addressing
This mode of addressing has no operands. Example CLC; clears carry flag to zero. Other examples are
CLD, STD, ESC, LOCK, NOP, WAIT, and CLI.

** Notice the flow of reading or decoding an instruction; from right to left. **

Virtual Memory

Is the memory management technique that allows all memory (main and mass storage devices) to be
addressed as part of one large logical address space. The logical address space is larger than the
microprocessor’s physical address space.

When the microprocessor outputs an address, the MMU fetches the descriptor for the addressed page or
segment. The descriptor includes a bit that indicates if the requested data is present in main memory or
if it is in mass storage devices. MMU aborts current instruction if the data is not in the main memory
and requests the OS to read the required page from the mass storage device. After reading the page
into the main memory, the instruction can be restarted or continued. The application program does not
distinguish between data or code in the main memory and in mass storage. Advantage is that larger
programs than main memory can be executed through swapping of pages.