Lecture Notes for Logic Family

P.Chiranjeevi
Assistant Professor
Department of ECE
Kakatiya Institute of Technology and Science
Waranagal-15

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 OVERVIEW

Introduction
Logic Family Classification
Fan IN And Fan Out
Noise Margin
Transistor as a Switch
RTL, DTL, TTL and ECL
Elementary data of CMOS

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 A bit of history
• The first transistors were fabricated in 1947 at
Bell Laboratories (Bell Labs) by Brattain with
Bardeen providing the theoretical background
and Shockley managed the activity.
– The trio received a Nobel Prize in Physics for their
work in 1956.
• The transistor was called a
point-contact transistor and was
a type of bipolar junction transistor
(BJT).
 A bit more history
• The theory on field effect transistors (FETs) was
developed much earlier than our understanding
of BJTs
– First patent on FETs dates from 1925
• Julius Edgar Lilienfeld, an Austro-Hungarian physicist
• However, the quality of the semiconductor and
the oxide materials were barriers to developing
good working devices.
– The first FET was not invented until 1959
• Dawon Kahng and Martin M. (John) Atalla of Bell Labs
 Integrated Circuits
• Integrated circuits (ICs) are chips, pieces of
semiconductor material, that contain all of the
transistors, resistors, and capacitors necessary
to create a digital circuit or system.
– The first ICs were fabricated using Ge BJTs in 1958.
• Jack Kirby of Texas Instruments, Nobel Prize in 2000

• Robert Noyes of Fairchild Semiconductors fabricated

the first Si ICs in 1959.
 Introduction
Logic families represent kind of digital circuit/methodologies for logic expression.

Integration levels :

SSI: Small scale integration 12 gates/chip

MSI: Medium scale integration 100 gates/chip
LSI: Large scale integration 1K gates/chip
VLSI: Very large scale integration 10K gates/chip
ULSI: Ultra large scale integration 100K gates/chip

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 Moore’s law
• A prediction made by Moore (a co-founder of Intel) in
1965: “… a number of transistors to double every 2
years.”

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 Logic Families
• Logic families are sets of chips that may implement different
logical functions, but use the same type of transistors and voltage
levels for logical levels and for the power supplies.
• These families vary by speed, power consumption, cost,
voltage & current levels

• IC digital logic families

– DL (Diode- logic)
– DTL （Diode-transistor logic）
– RTL （Resistor-transistor logic）
– TTL （Transistor -transistor logic）
– ECL （Emitter-coupled logic）
– MOS （Metal-oxide semiconductor）
– CMOS (Complementary Metal-oxide semiconductor）
 Classification

Logic Family

Bipolar Logic Family

ULF(unipolar logic family)

Saturated Non Saturated PMOS(p-channel MOSFET)

NMOS(n-channel MOSFET)
RTL(resistor transistor logic) Schottky TTL CMOS
DCTL(direct coupled transistor logic) ECL(emitter coupled logic)
IIL(integrated injection logic)
DTL(diode transistor logic)
HTL(high threshold logic)
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TTL(transistor transistor logic)
Fan In
• Fan in or gate is the number of inputs that can practically be supported
without degrading practically input voltage level.

Fan Out Fan in = 4

•The maximum number of digital input that the output of a single logic
gate can feed and the gate must be same logic family.

• Fan Out is calculated from the amount of current available in the output of
a gate and the amount of current needed in each input of the connecting
gate.

•It is specified by manufacturer and is provided in the data sheet.

•Exceeding the specified maximum load may cause a malfunction because

the circuit will not be able supply the demanded power.
Fanout = 4
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 Digital IC Terminology
fanout
• The maximum number of standard logic inputs that an output can
drive reliably.
• Also known as the loading factor.
• Related to the current parameters (both in high and low states.)
I OH I OL
DC fanout = min( , )
I IH I IL

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• Voltage Parameters: Digital IC Terminology
– VIH(min): high-level input voltage, the minimum voltage
level required for a logic 1 at an input.
– VIL(max): low-level input voltage
– VOH(min): high-level output voltage
– VOL(max): low-level output voltage
• For proper operation the input voltage levels to a logic must be kept
outside the indeterminate range.
• Lower than VIL(max) and higher than VIH(min).

For TTL
 Digital IC Terminology
Noise Margin
– noise is present in all real systems
– this adds random fluctuations to
voltages representing logic levels
– to cope with noise, the voltage ranges
defining the logic levels are more
tightly constrained at the output of a
gate than at the input
VNH
– thus small amounts of noise will not
affect the circuit
– the maximum noise voltage that can be VNL
tolerated by a circuit is termed its noise
immunity (noise Margin)

VNH = VOH(min) − VIH(min)

VNL = VIL(max) − VOL(max)
 Digital IC Terminology
Noise Margin
 Digital IC Terminology

Current Parameters:

• IOH – Current flowing into an output in the logical “1” state under specified load
conditions
• IOL – Current flowing into an output in the logical “0” state under specified load
conditions
• IIH – Current flowing into an input when a specified HI level is applied to that
input
• IIL – Current flowing into an input when a specified LO level is applied to that
input

IOH IIH IOL IIL

VOH VIH VOL VIL

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Propagation Delay

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 Digital IC Terminology
Power Requirements
• Every IC needs a certain amount of electrical power to
operate.
• Vcc (TTL)
• VDD(MOS)
• Power dissipation determined by Icc and Vcc.
• Average Icc(avg)= (ICCH + ICCL)/2
• PD(avg) = Icc(avg) x Vcc
 Digital IC Terminology

Speed-Power Product

• Desirable properties:
– Short propagation delays (high speed)
– Low power dissipation
• Speed-power product measures the
combined effect.
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 Transistor as a switch

• A circuit that can turn on/off current in

electrical circuit is referred to a switching
circuit and transistor can be employed as
an electronic switch.

• Cut off region - OFF State

Both junctions are reverse biased,
Ic = 0 and V(BE) < 0.7 v

• Saturation region - ON State

Ic = maximum and V(BE)>0.7 v
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 Resistor Transistor Logic(RTL)
 The basic RTL device is a NOR gate.

 The inputs represent either logic level HIGH (1) or LOW (0).

 The logic level LOW is the voltage that drives corresponding transistor in cut-off
region, while logic level HIGH drives it into saturation region.

 If both the inputs are LOW, then both the transistors are in cut-off i.e. they are
turned-off. Thus, voltage Vcc appears at output I.e. HIGH.

 If either transistor or both of them are applied HIGH input, the voltage Vcc drops
across Rc and output is LOW.

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Advantages of RTL Logic circuit:

The primary advantage of RTL technology was that it

involved a minimum number of transistors, which
was an important consideration before integrated
circuit technology, as transistors were the most
expensive component to produce

Limitations:

The obvious disadvantage of RTL is its high current

dissipation when the transistor conducts to
overdrive the output biasing resistor. This requires
that more current be supplied to and heat be
removed from RTL circuits. In contrast, TTL circuits
minimize both of these requirements.• (NOR GATE USING RTL)

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 Diode Transistor Logic
 The diode-transistor logic, also termed as DTL, replaced RTL family because of greater fan-out
capability and more noise margin.

 DTL circuits mainly consists of diodes and transistors that comprises DTL devices.

 The basic DTL device is a NAND gate.

 Two inputs to the gate are applied through diodes viz. D1, D2 . The diode will conduct only when
corresponding input is LOW.

 If any of the diode is conducting i.e. when at least one input is LOW, the voltage at output keeps
transistor T in cut-off and subsequently, output of transistor is HIGH. If all inputs are HIGH, all
diodes are non-conducting, transistor T is in saturation, and its output is LOW.

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Due to number of diodes
used in this circuit, the speed
of the circuit is significantly
low. Hence this family of logic
gates is modified to
transistor-transistor logic i.e. D1
TTL family which has been
discussed on next slide.
D2

(Block Diagram of
(DL AND GATE) DTL)
(SATURATING
INVERTER)

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 Transistor Transistor Logic
 TTL family is a modification to the DTL. It has come to existence so as to
overcome the speed limitations of DTL family. The basic gate of this family is TTL
NAND gate.

 Q3 is cutoff (act like a high RC ) when output transistor Q4 is saturated and Q3 is

saturated (act like a low RC ) when output transistor Q4 is cutoff . Thus one
transistor is ON at one time.

 The combination of Q3 and Q4 is called TOTEM POLE arrangement.

 Q1 is called input transistor, which is multi emitter transistor, that drive

transistor Q2 which is used to control Q3 and Q4.

 Diode D1 and D2 are used to protect Q1 from unwanted negative voltages and
diode D3 ensures when Q4 is ON, Q3 is OFF.
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The output impedance is asymmetrical between the high
and low state, making them unsuitable for driving
transmission lines. This drawback is usually overcome by
buffering the outputs with special line-driver devices where
signals need to be sent through cables. ECL, by virtue of its
symmetric low-impedance output structure, does not have
this drawback.

( BLOCK DIAGRAM OF TTL) 15

 Emitter Coupled Logic

 ECL logic family implements the gates in differential amplifier configuration in

which transistors are never driven in the saturation region thereby improving
the speed of circuit to a great extent. The ECL family is fastest of all logic
families.

 Based on BJT, but removes problems of delay time by preventing the transistors
from saturating.

 Very fast operation - propagation delays of 1ns or less.

 Low noise immunity of about 0.2-0.25 V .

 The input impedance is high and the output impedance is low. As a result, the
transistors change states quickly, gate delays are low, and the fan out capability
is high.
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 (FUNCTION TABLE)

(TRUTH TABLE) (LOGIC SYMBOL)

(Block Diagram of ECL)

(ECL 2 INPUT OR/NOR GATE)

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 Complimentary MOS (CMOS)

 Considerably lower energy consumption than TTL and ECL, which has
made portable electronics possible.

 Most widely used family for large-scale devices

 Combines high speed with low power consumption

 Usually operates from a single supply of 5 – 15 V

 Excellent noise immunity of about 30% of supply voltage

 Can be connected to a large number of gates (about 50) .

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Some statistical characteristics data of different logic families

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 References

 Switching Circuit and Logic Design by Prof. Indranil Sengupta, IIT KGP

 Modern digital Electronics by R P Jain

 NPTEL VIDEO by Dr. Amitava Dasgupta, IITM

 Logic Families by Dr. Basem Elhalawany

 Logic Gates and Family by Dr. A. P. VAJPEYI, IITG

Thank You
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