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Computer Architecture Lab: Name - Roll - 12100119111 Section - (B) Computer Science Engineering

The document contains VHDL code for designing various basic logic gates and combinational circuits like half adder, full adder, half subtractor, and full subtractor. The code contains the design and testbench for each circuit. The design section defines the port maps and logic for the circuit. The testbench section instantiates the design, defines test signals, and contains a process to simulate the circuit by applying different input patterns and checking the output. Sections A through G contain code for logic gates like AND, OR, NOT, NAND, NOR, XNOR, and XOR. Sections A and B contain code for half adder and full adder circuits. Section A of Experiment 3 contains code for a half subtractor

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Sankhadeep Chakrabarti
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161 views

Computer Architecture Lab: Name - Roll - 12100119111 Section - (B) Computer Science Engineering

The document contains VHDL code for designing various basic logic gates and combinational circuits like half adder, full adder, half subtractor, and full subtractor. The code contains the design and testbench for each circuit. The design section defines the port maps and logic for the circuit. The testbench section instantiates the design, defines test signals, and contains a process to simulate the circuit by applying different input patterns and checking the output. Sections A through G contain code for logic gates like AND, OR, NOT, NAND, NOR, XNOR, and XOR. Sections A and B contain code for half adder and full adder circuits. Section A of Experiment 3 contains code for a half subtractor

Uploaded by

Sankhadeep Chakrabarti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 71

Computer architecture lab:

Name -sankhadeep Chakrabarti


Roll -12100119111
Section-(b)
Computer science engineering
Experiment 1: basic gates
A:and gate
VHDL CODE:
Design:
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port ( a: in STD_LOGIC;
b: in STD_LOGIC;
f: out STD_LOGIC);
end and_gate;
architecture Behavioral of and_gate is
begin
f<= a and b;
end Behavioral;

test bench :
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity and_test is
end and_test;
Architecture behavior of and_test is

component and_gate
port(
a: in std_logic;
b: in std_logic;
f: out std_logic
);
end component;

signal a : std_logic :='0';


signal b : std_logic :='0';

signal f : std_logic;

begin

uut: and_gate port map (


a=>a,
b=>b,
f=>f
);

stim_proc: process
begin

wait for 100 ns;


a <= '0';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
wait for 100 ns;
a <= '1';
b <= '1';
wait ;
end process;
end;

OUTPUT:

B: or gate=
VHDL CODE:
DESIGN:
-- Simple OR gate design
library IEEE;
use IEEE.std_logic_1164.all;

entity or_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end or_gate;

architecture rtl of or_gate is


begin
process(a, b) is
begin
q <= a or b;
end process;
end rtl;

TEST BENCH:
-- Testbench for OR gate
library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
-- empty
end testbench;

architecture tb of testbench is
-- DUT component
component or_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end component;

signal a_in, b_in, q_out: std_logic;

begin

-- Connect DUT
DUT: or_gate port map(a_in, b_in, q_out);

process
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
--assert(q_out='0') report "Fail 0/0" severity error;

a_in <= '0';


b_in <= '1';
wait for 1 ns;
--assert(q_out='1') report "Fail 0/1" severity error;

a_in <= '1';


b_in <= '0';
wait for 1 ns;
--assert(q_out='1') report "Fail 1/X" severity error;

a_in <= '1';


b_in <= '1';
wait for 1 ns;
--assert(q_out='1') report "Fail 1/1" severity error;

-- Clear inputs
a_in <= '0';
b_in <= '0';
assert false report "Test done." severity note;
wait;
end process;
end tb;

OUTPUT:

C: not gate :
VHDL CODE:
DESIGN
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity not_gate is
port ( a: in STD_LOGIC;
f: out STD_LOGIC);
end not_gate;
architecture Behavioral of not_gate is
begin
f<= a not a;
end Behavioral;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity not_test is
end not_test;
Architecture behavior of not_test is

component not_gate
port(
a: in std_logic;
f: out std_logic
);
end component;

signal a : std_logic :='0';


signal f : std_logic;

begin

uut: not_gate port map (


a=>a,
f=>f
);

stim_proc: process
begin

wait for 100 ns;


a <= '0';
wait for 100 ns;
a <= '1';
wait ;
end process;
end;

OUTPUT:
D: nand gate :
VHDL CODE:
DESIGN:
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity nand_gate is
port ( a: in STD_LOGIC;
b: in STD_LOGIC;
f: out STD_LOGIC);
end nand_gate;
architecture Behavioral of nand_gate is
begin
f<= a nand b;
end Behavioral;

TEST BENCH :
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity nand_test is
end nand_test;
Architecture behavior of nand_test is

component nand_gate
port(
a: in std_logic;
b: in std_logic;
f: out std_logic
);
end component;
signal a : std_logic :='0';
signal b : std_logic :='0';

signal f : std_logic;

begin

uut: nand_gate port map (


a=>a,
b=>b,
f=>f
);

stim_proc: process
begin

wait for 100 ns;


a <= '0';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
wait for 100 ns;
a <= '1';
b <= '1';
wait ;
end process;
end;

OUTPUT:

E: nor gate :
VHDL CODE:
DESIGN:
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity nor_gate is
port ( a: in STD_LOGIC;
b: in STD_LOGIC;
f: out STD_LOGIC);
end and_gate;
architecture Behavioral of nor_gate is
begin
f<= a nor b;
end Behavioral;

TEST BENCH :
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity nor_test is
end nor_test;
Architecture behavior of nor_test is

component nor_gate
port(
a: in std_logic;
b: in std_logic;
f: out std_logic
);
end component;
signal a : std_logic :='0';
signal b : std_logic :='0';

signal f : std_logic;

begin

uut: nor_gate port map (


a=>a,
b=>b,
f=>f
);

stim_proc: process
begin

wait for 100 ns;


a <= '0';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
wait for 100 ns;
a <= '1';
b <= '1';
wait ;
end process;
end;

OUTPUT:

F: xnor gate :
VHDL CODE:
DESIGN :
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity xnor_gate is
port ( a: in STD_LOGIC;
b: in STD_LOGIC;
f: out STD_LOGIC);
end xnor_gate;
architecture Behavioral of xnor_gate is
begin
f<= a xnor b;
end Behavioral;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity xnor_test is
end xnor_test;
Architecture behavior of xnor_test is

component xnor_gate
port(
a: in std_logic;
b: in std_logic;
f: out std_logic
);
end component;
signal a : std_logic :='0';
signal b : std_logic :='0';

signal f : std_logic;

begin

uut: xnor_gate port map (


a=>a,
b=>b,
f=>f
);

stim_proc: process
begin

wait for 100 ns;


a <= '0';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
wait for 100 ns;
a <= '1';
b <= '1';
wait ;
end process;
end;

OUTPUT:

G: xor gate :
VHDL CODE:
DESIGN :
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity xor_gate is
port ( a: in STD_LOGIC;
b: in STD_LOGIC;
f: out STD_LOGIC);
end xor_gate;
architecture Behavioral of xor_gate is
begin
f<= a xor b;
end Behavioral;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity xor_test is
end xor_test;
Architecture behavior of xor_test is

component xor_gate
port(
a: in std_logic;
b: in std_logic;
f: out std_logic
);
end component;
signal a : std_logic :='0';
signal b : std_logic :='0';

signal f : std_logic;

begin

uut: xor_gate port map (


a=>a,
b=>b,
f=>f
);

stim_proc: process
begin

wait for 100 ns;


a <= '0';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
wait for 100 ns;
a <= '1';
b <= '1';
wait ;
end process;
end;

OUTPUT:

EXPERIMENT :2 A : HALF ADDER:


VHDL CODE:
DESIGN :
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity H_adder is
port(
a,b : IN std_logic;
sum,carry : OUT std_logic);
end H_adder;

architecture dataflow of H_adder is


begin

sum <= a xor b;


carry <= a and b;

end dataflow;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity half_adder_tb is
end entity;

architecture tb of half_adder_tb is
component H_adder is
port( a,b : IN std_logic;
sum,carry : OUT std_logic);
end component;

signal a,b,sum,carry: std_logic;

begin

uut: H_adder port map(


a => a,b => b,
sum => sum,
carry => carry);

stim: process
begin

a <= '0';
b <= '0';
wait for 20 ns;

a <= '0';
b <= '1';
wait for 20 ns;

a <= '1';
b <= '0';
wait for 20 ns;

a <= '1';
b <= '1';
wait for 20 ns;

wait;

end process;

end tb;

OUTPUT:

B : FULL ADDER:
VHDL CODE:
DESIGN:
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity full_adder is
port(
a,b,cin : IN std_logic;
FA_sum,FA_carry : OUT std_logic);
end full_adder;

architecture dataflow of full_adder is


begin

FA_sum <= (a xor b) xor cin;


FA_carry <=(a and b) or (b and cin) or (cin and a);

end dataflow;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity full_adder_tb is
end entity;
architecture tb of full_adder_tb is
component full_adder is
port(a,b,cin : IN std_logic;
FA_sum,FA_carry : OUT std_logic);
end component;

signal a,b,cin,FA_sum,FA_carry : std_logic;

begin

uut: full_adder port map(


a => a, b => b,
cin => cin,
FA_sum => FA_sum,
FA_carry => FA_carry);

stim: process
begin

a <= '0';
b <= '0';
cin <= '0';
wait for 10 ns;

a <= '0';
b <= '0';
cin <= '1';
wait for 10 ns;

a <= '0';
b <= '1';
cin <= '0';
wait for 10 ns;

a <= '0';
b <= '1';
cin <= '1';
wait for 10 ns;
wait;

end process;

end tb;

OUTPUT:
EXPERIMENT 3: A: HALF
SUBTRACTOR
VHDL CODE:
DESIGN:
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity half_sub is
port( a,b : IN std_logic;
diff,borrow : OUT std_logic);
end half_sub;

architecture dataflow of half_sub is


begin

diff <= a xor b;


borrow <= (not a) and b;

end dataflow;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity half_sub_tb is
end entity;

architecture tb of half_sub_tb is
component half_sub is
port(a,b : IN std_logic;
diff,borrow : OUT std_logic);
end component;

signal a,b,diff,borrow : std_logic;

begin

uut: half_sub port map(


a => a, b => b,
diff => diff,
borrow => borrow);

stim: process
begin

a <= '0';
b <= '0';
wait for 20 ns;

a <= '0';
b <= '1';
wait for 20 ns;

a <= '1';
b <= '0';
wait for 20 ns;

a <= '1';
b <= '1';
wait for 20 ns;
wait;

end process;

end tb;

OUTPUT :

B : FULL SUBTRACTOR.
VHDL CODE:
DESIGN :
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity full_sub is
port( a,b,c : IN std_logic;
diff,borrow : OUT std_logic);
end full_sub;

architecture dataflow of full_sub is


begin

diff <= (a xor b) xor c;


borrow <=((not a) and (b or c)) or (b and c);

end dataflow;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity full_sub_tb is
end entity;

architecture tb of full_sub_tb is
component full_sub is
port(a,b,c : IN std_logic;
diff,borrow : OUT std_logic);
end component;

signal a,b,c,diff,borrow : std_logic;

begin

uut: full_sub port map(


a => a, b => b,
c => c,
diff => diff,
borrow => borrow);

stim: process
begin

a <= '0';
b <= '0';
c <= '0';
wait for 20 ns;

a <= '0';
b <= '0';
c <= '1';
wait for 20 ns;

a <= '0';
b <= '1';
c <= '0';
wait for 20 ns;
a <= '0';
b <= '1';
c <= '1';
wait for 20 ns;
wait;

end process;

end tb;

OUTPUT:

EXPERIMENT 4: 4*1 MULTIPLEXER.


VHDL CODE:
DESIGN:
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH. ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX4_1 is

Port (i : in STD_LOGIC_VECTOR (3 downto 0);


s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);

end MUX4_1;

architecture dataflow of MUX4_1 is

begin

with s select

y <= i(0) when "00",


i(1) when "01",
i(2) when "10",
i(3) when others;

end dataflow;
TEST BENCH :
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED. ALL;

entity Mux4_1_tb is

end entity;

architecture tb of Mux4_1_tb is

component MUX4_1 is

Port (i : in STD_LOGIC_VECTOR (3 downto 0);


s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end component;

signal i : STD_LOGIC_VECTOR (3 downto 0);

signal s : STD_LOGIC_VECTOR (1 downto 0);

signal y :STD_LOGIC;
begin

uut: MUX4_1 port map(

i => i,
s => s,
y => y);

stim: process

begin

i <= "1010";

s <= "00";

wait for 20 ns;

s <= "01"; wait for 20 ns;

s <= "10"; wait for 20 ns;

s <= "11";

wait for 20 ns;

wait;

end process;

end tb;

OUTPUT :
EXPERIMENT 5: 2*4 DECODER:
VHDL CODE:
DESIGN:
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH. ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX4_1 is

Port (i : in STD_LOGIC_VECTOR (3 downto 0);


s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);

end MUX4_1;

architecture dataflow of MUX4_1 is

begin

with s select

y <= i(0) when "00",


i(1) when "01",
i(2) when "10",
i(3) when others;

end dataflow;
TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED. ALL;

entity Mux4_1_tb is

end entity;

architecture tb of Mux4_1_tb is

component MUX4_1 is

Port (i : in STD_LOGIC_VECTOR (3 downto 0);


s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end component;

signal i : STD_LOGIC_VECTOR (3 downto 0);

signal s : STD_LOGIC_VECTOR (1 downto 0);

signal y :STD_LOGIC;
begin

uut: MUX4_1 port map(

i => i,
s => s,
y => y);

stim: process

begin

i <= "1010";

s <= "00";

wait for 20 ns;

s <= "01"; wait for 20 ns;

s <= "10"; wait for 20 ns;

s <= "11";

wait for 20 ns;

wait;

end process;

end tb;

OUTPUT:
EXPERIMENT 6:
FULL ADDER USING HALF ADDER:
VHDL CODE:
DESIGN :
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity halfadder is
port(a,b:in std_logic;
sum,carry: out std_logic
);
end halfadder;

architecture behavioural of halfadder is


begin
process(a,b,sum,carry) is
begin
sum<=a xor b;
carry<=a and b;

end process;
end behavioural;

-- Code your design here


library IEEE;
use IEEE.std_logic_1164.all;

entity fulladder is

port(A,B,C:in std_logic;
SUM,CARRY: out std_logic
);
end fulladder;

architecture bhv of fulladder is


begin
process (A,B,C,SUM,CARRY) is
begin
SUM<=A xor B xor C;
CARRY<= (A and B) or (B and C) or (C and A);
end process;
end bhv;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is

end testbench;

architecture tb of testbench is
component halfadder is

port(a,b:in std_logic;
sum,carry: out std_logic
);
end component;
component fulladder is
port(
A,B,C: in STD_LOGIC;
SUM,CARRY: out STD_logic);
end component;

signal a_in, b_in,c_in,SUM_out,CARRY_out:std_logic;

begin
DUT: fulladder port map(a_in, b_in,c_in,SUM_out,CARRY_out);

process
begin
a_in <= '1';
b_in <= '0';
c_in <= '1';
wait for 1 ns;

a_in <= '0';


b_in <= '0';
c_in <= '0';
wait for 1 ns;

a_in <= '0';


b_in <= '0';
c_in <= '1';
wait;
end process;
end tb;

OUTPUT:
EXPERIMENT 7:
RIPPLE CARRY ADDER:
VHDL CODE:
DESIGN:
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity Ripple_Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Ripple_Adder;
architecture Structural of Ripple_Adder is
component full_adder_vhdl_code
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal c1,c2,c3: STD_LOGIC;
begin
FA1: full_adder_vhdl_code port map( A(0), B(0),'0', S(0), c1);
FA2: full_adder_vhdl_code port map( A(1), B(1), c1, S(1), c2);
FA3: full_adder_vhdl_code port map( A(2), B(2), c2, S(2), c3);
FA4: full_adder_vhdl_code port map( A(3), B(3), c3, S(3), Cout);
end Structural;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

ENTITY Tb_Ripple_Adder IS
END Tb_Ripple_Adder;
ARCHITECTURE tb OF Tb_Ripple_Adder IS
COMPONENT Ripple_Adder
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';
signal S : std_logic_vector(3 downto 0);
signal Cout : std_logic;
BEGIN
uut: Ripple_Adder PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout);
stim_proc: process
begin
wait for 100 ns;
A <= "0110";
B <= "1100";

wait for 100 ns;


A <= "1111";
B <= "1100";

wait for 100 ns;


A <= "0110";
B <= "0111";

wait for 100 ns;


A <= "0110";
B <= "1110";

wait for 100 ns;


A <= "1111";
B <= "1111";

wait;
end process;
END tb;

OUTPUT:
EXPERIMENT 8: SR FLIP FLOP:
VHDL CODE:
DESIGN :
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;
entity SR_FLIPFLOP_SOURCE is
port ( S,R,RST,CLK : in STD_LOGIC;
Q,Qb : out STD_LOGIC);
end SR_FLIPFLOP_SOURCE;

architecture Behavioral of SR_FLIPFLOP_SOURCE is

begin
process (S,R,RST,CLK)

begin
if (RST = '1') then
Q <= '0';
elsif (RISING_EDGE (CLK))then
if (S /= R) then
Q <= S;
Qb <= R;
elsif (S = '1' AND R = '1') then
Q<= 'Z';
Qb <= 'Z';end if;
end if;
end process;
end behavioral;
TEST BENCH :
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH. ALL;
use IEEE.STD_LOGIC_UNSIGNED. ALL;
entity SR_FF_tb is
end entity;
architecture tb of SR_FF_tb is

component SR_FLIPFLOP_SOURCE is
Port (S,R,RST, CLK : in STD_LOGIC;
Q,Qb : out STD_LOGIC);
end component;

signal S, R, RST, CLK, Q, Qb: STD_LOGIC;

begin
uut: SR_FLIPFLOP_SOURCE port map(
S => S,
R => R,
RST => RST,
CLK => CLK,
Q => Q,
Qb => Qb);

Clock: process
begin

CLK <= '0';


wait for 10 ns;
CLK <= '1';
wait for 10 ns;

end process;

Stim: process
begin

RST <= '0';

S <= '0';
R <= '0';
wait for 20 ns;

S <= '0';
R <= '1';
wait for 20 ns;

S <= '1';
R <= '0';
wait for 20 ns;
S <= '1';
R <= '1';
wait for 20 ns;
end process;
end tb;

OUTPUT:
………………………
………………………
…….

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