Memory Mapping, Bit-Band Operations and Cmsis: Arm Microcontroller & Embedded Systems (17ec62)

The document discusses key features of the ARM Cortex-M3 microcontroller memory system including its predefined memory map, bit-band support for atomic bit operations, and support for unaligned transfers and exclusive accesses. It describes the various memory regions, their access attributes, and default access permissions. The memory map defines which bus interface is used for different memory locations and allows flexibility for manufacturers. Bit-band support maps each word address to a single bit to enable setting or clearing individual bits.

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Memory Mapping, Bit-Band Operations and Cmsis: Arm Microcontroller & Embedded Systems (17ec62)

Uploaded by

Sammed Upadhye

Available Formats

Download as PDF, TXT or read online on Scribd

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ARM MICROCONTROLLER & EMBEDDED SYSTEMS (17EC62)

MODULE – 2 (SELECTED TOPICS)

Memory Mapping, Bit-Band

Operations and
CMSIS
Shrishail Bhat, Dept. of ECE, AITM Bhatkal 1
Memory System Features Overview
• The Cortex-M3 processor has different memory architecture from that of traditional
ARM processors.
• First, it has a predefined memory map that specifies which bus interface is to be used
when a memory location is accessed.
• This feature also allows the processor design to optimize the access behavior when different
devices are accessed.
• Another feature of the memory system in the Cortex-M3 is the bit-band support.
• This provides atomic operations to bit data in memory or peripherals.
• The bit-band operations are supported only in special memory regions.
• The Cortex-M3 memory system also supports unaligned transfers and exclusive
accesses.
• These features are part of the v7-M architecture.
• Finally, the Cortex-M3 supports both little endian and big endian memory
configuration.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 2

Memory Maps
• The Cortex-M3 processor has a fixed memory map.
• This makes it easier to port software from one Cortex-M3 product to another.
• For example, components described in previous sections, such as Nested
Vectored Interrupt Controller (NVIC) and Memory Protection Unit (MPU), have
the same memory locations in all Cortex-M3 products.
• Nevertheless, the memory map definition allows great flexibility so that
manufacturers can differentiate their Cortex-M3-based product from others.
• Some of the memory locations are allocated for private peripherals such as
debugging components.
• They are located in the private peripheral memory region.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 3

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 4
Shrishail Bhat, Dept. of ECE, AITM Bhatkal 5
Memory Maps (continued)
• The Cortex-M3 processor has a total of 4 GB of address space.
• Program code can be located in the code region, the Static Random Access
Memory (SRAM) region, or the external RAM region.
• However, it is best to put the program code in the code region because with
this arrangement, the instruction fetches and data accesses are carried out
simultaneously on two separate bus interfaces.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 6

Memory Maps (continued)
• The SRAM memory range is for connecting internal SRAM.
• Access to this region is carried out via the system interface bus.
• In this region, a 32-MB range is defined as a bit-band alias.
• Within the 32-bit-band alias memory range, each word address represents a single bit
in the 1-MB bit-band region.
• A data write access to this bit-band alias memory range will be converted to an atomic
READ-MODIFY-WRITE operation to the bit-band region so as to allow a program to set
or clear individual data bits in the memory.
• The bit-band operation applies only to data accesses not instruction fetches.
• By putting Boolean information (single bits) in the bit-band region, we can pack
multiple Boolean data in a single word while still allowing them to be accessible
individually via bit-band alias, thus saving memory space without the need for
handling READ-MODIFY-WRITE in software.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 7

Memory Maps (continued)
• Another 0.5-GB block of address range is allocated to on-chip
peripherals.
• Similar to the SRAM region, this region supports bit-band alias and
is accessed via the system bus interface.
• However, instruction execution in this region is not allowed.
• The bit-band support in the peripheral region makes it easy to
access or change control and status bits of peripherals, making it
easier to program peripheral control.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 8

Memory Maps (continued)
• Two slots of 1-GB memory space are allocated for external RAM
and external devices.
• The difference between the two is that program execution in the
external device region is not allowed, and there are some
differences with the caching behaviors.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 9

Memory Maps (continued)
• The last 0.5-GB memory is for the system-level components,
internal peripheral buses, external peripheral bus, and vendor-
specific system peripherals.
• There are two segments of the private peripheral bus (PPB):
• Advanced High-Performance Bus (AHB) PPB, for Cortex-M3 internal AHB
peripherals only
• This includes NVIC, FPB, DWT, and ITM
• Advance Peripheral Bus (APB) PPB, for Cortex-M3 internal APB devices as
well as external peripherals (external to the Cortex-M3 processor)
• The Cortex-M3 allows chip vendors to add additional on-chip APB peripherals on this
private peripheral bus via an APB interface

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 10

Memory Maps (continued)
• The NVIC is located in a memory region called the system control
space (SCS).
• Besides providing interrupt control features, this region also
provides the control registers for SYSTICK, MPU, and code
debugging control.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 11

Memory Maps (continued)
• The remaining unused vendor-specific memory range can be
accessed via the system bus interface.
• However, instruction execution in this region is not allowed.
• The Cortex-M3 processor also comes with an optional MPU.
• Chip manufacturers can decide whether to include the MPU in their
products.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 12

Memory Access Attributes
• The memory map shows what is included in each memory region.
• Aside from decoding which memory block or device is accessed, the memory
map also defines the memory attributes of the access.
• The memory attributes you can find in the Cortex-M3 processor include the
following:
• Bufferable: Write to memory can be carried out by a write buffer while the
processor continues on next instruction execution.
• Cacheable: Data obtained from memory read can be copied to a memory cache so
that next time it is accessed the value can be obtained from the cache to speed up
the program execution.
• Executable: The processor can fetch and execute program code from this memory
region.
• Sharable: Data in this memory region could be shared by multiple bus masters.
Memory system needs to ensure coherency of data between different bus masters
in shareable memory region.
Shrishail Bhat, Dept. of ECE, AITM Bhatkal 13
Memory Access Attributes (continued)
• The memory access attributes for each memory region are as follows:
• Code memory region (0x00000000–0x1FFFFFFF): This region is executable, and the
cache attribute is write through (WT). You can put data memory in this region as
well. If data operations are carried out for this region, they will take place via the
data bus interface. Write transfers to this region are bufferable.
• SRAM memory region (0x20000000–0x3FFFFFFF): This region is intended for on-
chip RAM. Write transfers to this region are bufferable, and the cache attribute is
write back, write allocated (WB-WA). This region is executable, so you can copy
program code here and execute it.
• Peripheral region (0x40000000–0x5FFFFFFF): This region is intended for peripherals.
The accesses are noncacheable. You cannot execute instruction code in this region
(Execute Never, or XN in ARM documentation, such as the Cortex-M3 TRM).

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 14

Memory Access Attributes (continued)
• External RAM region (0x60000000–0x7FFFFFFF): This region is intended for
either on-chip or off-chip memory. The accesses are cacheable (WB-WA), and
you can execute code in this region.
• External RAM region (0x80000000–0x9FFFFFFF): This region is intended for
either on-chip or off-chip memory. The accesses are cacheable (WT), and you
can execute code in this region.
• External devices (0xA0000000–0xBFFFFFFF): This region is intended for external
devices and/or shared memory that needs ordering/nonbuffered accesses. It is
also a nonexecutable region.
• External devices (0xC0000000–0xDFFFFFFF): This region is intended for external
devices and/or shared memory that needs ordering/nonbuffered accesses. It is
also a nonexecutable region.
• System region (0xE0000000–0xFFFFFFFF): This region is for private peripherals
and vendor-specific devices. It is nonexecutable. For the PPB memory range,
the accesses are strongly ordered (noncacheable, nonbufferable). For the
vendor-specific memory region, the accesses are bufferable and noncacheable.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 15

Default Memory Access Permissions
• The Cortex-M3 memory map has a default configuration for
memory access permissions.
• This prevents user programs (non-privileged) from accessing system
control memory spaces such as the NVIC.
• The default memory access permission is used when either no MPU
is present or MPU is present but disabled.
• If MPU is present and enabled, the access permission in the MPU
setup will determine whether user accesses are allowed.

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 16

Shrishail Bhat, Dept. of ECE, AITM Bhatkal 17
Bit-Band Operations
• Bit-band operation support allows a single load/store operation to
access (read/write) to a single data bit.
• In the Cortex-M3, this is supported in two predefined memory regions
called bit-band regions.
• One of them is located in the first 1 MB of the SRAM region, and the
other is located in the first 1 MB of the peripheral region.
• These two memory regions can be accessed like normal memory, but
they can also be accessed via a separate memory region called the bit-
band alias.
• When the bit-band alias address is used, each individual bit can be
accessed separately in the least significant bit (LSB) of each word-aligned
address.