DLD Lecture Notes (Compatibility Mode)
DLD Lecture Notes (Compatibility Mode)
EEE365
Digital Logic Design
output analog
signals
Digital Signal
Advantages of Digital Techniques
Very much easier to design.
Voltage Level
High = 1
– Used in processors and digital circuits
– High voltage = 1, Low voltage = 0 Unused
• Using electric charge
Low = 0
– Used in memory cells
– Charged memory cell = 1, discharged memory cell = 0
• Using magnetic field
– Used in magnetic disks, magnetic polarity indicates 1 or 0
• Using light
– Used in optical disks, surface pit indicates 1 or 0
Binary Numbers
– Fractions
Most Least
– Characters Significant Bit Significant Bit
7 6 5 4 3 2 1 0
1 0 0 1 1 1 0 1
27 26 25 24 23 22 21 20
Some common
powers of 2
Positional Number Systems
Different Representations of Natural Numbers
3 5 3 0 5 5 2 3 6 2 4 Octal
1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 0 1 0 1 0 0 32-bit binary
E B 1 6 A 7 9 4 Hexadecimal
Conversion from Decimal to base r
37 = (100101)2
OR operation with OR gates, AND operation with AND gates, NOR operation
with NOR gates, Describing logic circuits algebraically, Evaluating logic circuit
outputs, Implementing circuits from Boolean expressions, NOR gates & NAND
gates.
Boolean Algebra
AND GATE
OR GATE
NOT GATE
NAND GATE
NOR GATE
Ex-OR GATE
Ex-NOR GATE
Truth Tables
Used to describe the functional behavior of a Boolean
expression and/or Logic circuit.
Each row in the truth table represents a unique combination
of the input variables.
− For n input variables, there are 2n rows.
The output of the logic function is defined for each row.
Each row is assigned a numerical value, with the rows listed
in ascending order.
The order of the input variables defined in the logic
function is important.
AND Gate
The AND gate is an electronic circuit that gives a high
output only if all its inputs are high.
A dot(.) is used to show the AND operation.
Truth table
Circuit Symbol
2 Input AND gate
A Z=A.B A B Z=A.B
0 0 0
B
0 1 0
AND 1 0 0
1 1 1
Summary of the AND gates
An AND gate output will be 1 only for the case when all
inputs are 1; for all other cases, the output will be 0.
2 Input OR gate
A Z=A+B A B Z=A+B
B 0 0 0
0 1 1
OR 1 0 1
1 1 1
Summary of the OR gates
NOT GATE
A A A A
0 1
1 0
NAND Gate
Truth table
Truth table
A A⊕B A B A ⊕B
B 0 0 0
0 1 1
EX-OR 1 0 1
1 1 0
EX-NOR Gate
The Exclusive –NOR gate is circuit does the opposite to the
EX-NOR gate. The symbol is an EX-NOR gate with a small
circle on the output. The small circle represents inversion.
Truth table
A⊕B A B A ⊕B
A
0 0 1
B
0 1 0
EX-NOR 1 0 0
1 1 1
Universal Gates
NAND and NOR are known as universal gates because
they are inexpensive to manufacture and any Boolean
function can be constructed using only NAND or only
NOR gates.
Boolean Expressions
F = (A+B+C').(A'+B'+C).(A+B+C)
F = A.B'.C' + A.(B.C' + B'.C)
Boolean Expressions
f
Boolean Expressions
Boolean expressions are evaluated by
Substituting a 0 or 1 for each literal.
Calculating the logical value of the expression.
x1
x1 x1
x2 x2
x2
(a) x1 x2 = x1 + x2
x1
x1 x1
x2 x2
x2
(b) x1 + x2 = x1 x2
Importance of Boolean Algebra
Boolean Algebra is used to simplify Boolean expressions.
– Through application of the Laws and Theorems
discussed
Simpler expressions lead to simpler circuit realization,
which, generally, reduces cost, area requirements, and
power consumption.
The objective of the digital circuit designer is to design
and realize optimal digital circuits.
Algebraic Simplification
Justification for simplifying Boolean expressions:
– Reduces the cost associated with realizing the
expression using logic gates.
– Reduces the area (i.e. silicon) required to
fabricate the switching function.
– Reduces the power consumption of the circuit.
In general, there is no easy way to determine when a
Boolean expression has been simplified to a minimum
number of terms or minimum number of literals.
– No unique solution
Algebraic Simplification
Sum-of-Products (SOP)
− Derived from the Truth table for a function by
considering those rows for which F = 1.
− The logical sum (OR) of product (AND) terms.
− Realized using an AND-OR circuit.
Product-of-Sums (POS)
− Derived from the Truth table for a function by
considering those rows for which F = 0.
− The logical product (AND) of sum (OR) terms.
− Realized using an OR-AND circuit.
Sum-of-Products
Any function F can be represented by a sum of minterms,
where each minterm is ANDed with the corresponding
value of the output for F.
− F = ∑ (mi . fi)
where mi is a minterm
Denotes the logical
sum operation and fi is the corresponding functional
output
− Only the minterms for which fi = 1 appear in the
expression for function F.
− F = ∑ (mi) = ∑ m(i) shorthand notation
Sum-of-Products
AND sum
Y' + X'YZ' + XY
X.Y
OR
F = (A + B).(C + D).(E)
F = (A.C + A.D + B.C + B.D).(E)
Product terms are
F = A.C.E + A.D.E + B.C.E + B.D.E of single variables
Answe The function has three variables, A, B, and C. The first term A is missing
r: two variables; therefore:
Product-of-Sums (POS)
Product-of-Sums
Any function F can be represented by a product of
Maxterms, where each Maxterm is ANDed with the
complement of the corresponding value of the
output for F.
− F = Π (Mi . f 'i)
where Mi is a Maxterm
Denotes the logical and f 'i is the complement of the
product operation
corresponding functional output
− Only the Maxterms for which fi = 0 appear
in the expression for function F.
− F = Π (Mi) = Π M(i) shorthand notation
Product-of-Sums
OR product term
X.(Y' + Z).(X' + Y + Z)
X' + Y + Z
AND
sum term
OR
F=B’D’+B’C’+A’C’D
Combine ‘0’ terms for F’
F’ = ∑(3,4,6,7,11,12,13,14,15)
= AB + CD + BD’
By DeMorgan,
F = (A’+B’)(C’+D’)(B’+D)
F=B’D’+B’C’+A’C’D F = (A’+B’)(C’+D’)(B’+D)
x y z F (a) SOP
0 0 0 0 F(x,y,z) = Σ (1,3,4,6)
0 0 1 1 = x’z + xz’
0 1 0 0
0 1 1 1
1 0 0 1 (b) Combine 0’s
1 0 1 0
(b) POS
1 1 0 1
1 1 1 0 F’(x,y,z) = Σ (0,2,5,7)
= xz + x’z’
F(x,y,z)=(x’+z’)(x+z)
don’t care!
• You don’t always need all 2n input combinations in an n-variable function.
– If you can guarantee that certain input combinations never occur.
– If some outputs aren’t used in the rest of the circuit.
• We mark don’t-care outputs in truth tables and K-maps with Xs.
x y z f(x,y,z)
0 0 0 0
0 0 1 1
0 1 0 X
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 X
1 1 1 1
AB 0 0
AB X 0
CD 7 0 1 1 1 0
00 01 11 10
AB 8 1 0 0 0 1
00 1 0 0 1 9 1 0 0 1 0
X X
01 0 0 0 1
X X
11 X X X X X X
10 1 0 X X X X
X X
CD’ + B’D’
X X
Example: Seven Segment Display
A B C D a
a
0 0 0 0 0 1
f b
Table for a 1 0 0 0 1 0
g 2 0 0 1 0 1
e c
3 0 0 1 1 1
d 4 0 1 0 0 0
5 0 1 0 1 1
CD 6 0 1 1 0 1
00 01 11 10
AB
7 0 1 1 1 1
00 1 1 1 1 0 0 0 1
8
01 1 1 1 9 1 0 0 1 1
X X
11 X X X X
X X
10 1 1 X X X X
X X
A + C + BD + B’D’
X X
X X
BCD Display (1/6)
BCD Display (2/6)
BCD Display (3/6)
BCD Display (4/6)
a = w + y + x’z’ + xz
b = y’ + xz’
c = w + y’z’ + yz + x’z’
d = w + xy’ + yz’ + x’y
e = yz’ + x’z’ + w’x’y’
f = w + x + y’z’ + yz
g = x’z’ + yz’ + x’y + xy’z
BCD Display (5/6)
BCD Display (6/6)
NAND gate implementation
NAND & NOR Implementation (1/2)
• NAND / NOR
– basic gates used in all IC digital logic families
– Need conversion from AND/OR/NOT into
NAND/NOR
• Compare with AND/OR
– Digital circuits are frequently constructed with
NAND/NOR rather than with AND/OR gates.
– NAND and NOR gates are easier to fabricate with
electronic components than AND/OR
– Cheaper (lower cost) and faster (less delay)
NAND & NOR Implementation (2/2)
Real delay
depends on
the VLSI
process tech.
.35
.25
.18
.13 um
.09 90 nm
NAND
• A “universal” gate
– any digital system can be implemented with it
• AND, OR, NOT can be obtained from NAND gates
NAND
= x
0
y
0
(xy)’
1
0 1 1
1 0 1
1 1 0
One-input
NAND
x x’
0 1
1 0
Two Graphic Symbols for NAND Gate
AB+CD
CD
(AB)’
= ((AB)’(CD)’)’
= (CD)’
= (AB)’’+(CD)’’
=AB+CD
2-Level NAND Implementation
Ex 3-10 Implement F(x,y,z)=∑(1,2,3,4,5,7)
with NAND gates
1. Simplify F(x,y,z) in sum of products by
means of “map”.
1
2. Draw a NAND gate for each product term 2
with at least 2 literals. 3
F = A(CD + B) + BC’
3-Level of Gating
Ex.2 F = (AB’ + A’B)(C+D’)
NOR Implementation
• A universal gate
• The dual of NAND
– All procedures/rules for NAND are dual of the
corresponding procedures/rules for NOR
NOR
• NOT OR AND implemented with NOR x y (x+y)’
0 0 1
0 1 0
1 0 0
1 1 0
One-input
NOR
x x’
0 1
1 0
Graphic Symbols for NOR Gate
• Requirement
– the Boolean function in product of sums
• map combining 0’s complementing
• “OR-AND” diagram → all-NOR diagram
“NOR-NOR”
• Multilevel implementation – similar to
the one for NAND
2-level NOR Implementation
Fig. 3.26
Implementing
F = (A + B)(C + D)E
3-level NOR Implementation
(combining 1’s)
(combining 0’s)
OR-AND-INVERT Functions
• Implement the circuit with OR-NAND or NOR-OR
• OR-NAND = NOR-OR F = [(A+B)(C+D)E)]’
Example of Function Implementations (2/2)
F = x’y’z’ + xyz’
F’=(x+y+z)(x’+y’+z) F = [(x+y+z)(x’+y’+z)]’
(combining 1’s)
(combining 0’s)
Three-Input Circuit
Mir has three girl friends. He want to design an alarm.
w= xy + yz+ xz 1 1 1 1
Three-Input Circuit
X Y Z W z x y 00 01 11 10
0 0 0 0
input 0 0 1 0 1
0
0 1 0 0
0 1 1 1 output 1 1 1 1
1 0 0 0
1 0 1 1
w= xy + yz+ xz
1 1 0 1
1 1 1 1
x x xy
Low cost y o y yz o
Less delay
z z xz
Exclusive-OR (Ex-OR)
Ex-OR
x y x⊕y
• Exclusive-OR (Ex-OR) 0 0 0
0 1 1
x y = xy’ + x’y 1 0 1
1 1 0
• x=1 or y=1 but not both
• different inputs output = 1 Ex-NOR
x y (x⊕y)’
• only one input equal to 1 output = 1 0 0 1
0 1 0
• Exclusive-NOR 1 0 0
1 1 1
(x ʘ y) = xy + x’y’
• same inputs (both=1 or both=0) ⇒ output = 1
• Ex-OR is the complement of Exclusive-NOR
[proof] (x y)’ = (xy’+x’y)’ = (x’+y)(x+y’)
= xy +x’y’
Properties of Ex-OR
x 0=x
Ex-OR
x 1 = x’ x y x⊕y
x x=0 0 0 0
0 1 1
x x’ = 1 1 0 1
x y’ = x’ y = (x y)’ 1 1 0
The truth table that defines the required relationships between inputs and
outputs is derived.
The practical design method would have to consider such constraints as ---
This is a block
diagram for a
decoder.
3 x 8 Decoder
The output lines generate the binary code corresponding to the input value.
• This shifter
moves the bits
of a nibble one
position to the
left or right.
The selection of a specific output line is controlled by the bit values of n selection
lines.