CHAPTER 5

INSTRUCTION SET OF 8031/8051

5.1 MACHINE CYCLES AND TIMING DIAGRAM

The external basic operations performed by a microcontroller are called machine cycles.
The executive of an instruction involves execution of one or more machine cycles in a specified
order. The 8031/8051 microcontroller takes one to four machine cycles to execute an instruction.
The basic timing of the 8031/8051 machine cycle is shown in Fig. 5.1.
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
® ® ® ® ® ® ®® ® ® ® ® ®® ® ®® ® ®
® ® ® ® ®

® ® ® ® ® ® ® ®® ® ® ®
S1 S2 S3 S4 S5 S6
One Machine Cycle. ®
®
Fig. 5.1 : Basic timing of a machine cycle.

The entire timing of a machine cycle of 8031/8051 is divided into 6 states and they are
denoted as S1, S2, S3, S4, S5 and S6. The timing of each state is two clock periods and they are
denoted as P1 and P2.
A state in a machine cycle is a basic time interval for discrete operation of the microcontroller
such as fetching an opcode byte, decoding an opcode, executing an opcode, writing a data, etc. The
time taken to execute a machine cycle is 12 clock periods and so the time taken to execute an instruction
is obtained by multiplying the number of machine cycles of that instruction by 12 clock periods.
Instruction execution time = C × 12 × T
1
= C × 12 × f
where, C = Number of machine cycles of an instruction.
T = Time period of crystal frequency in seconds.
f = Crystal frequency in Hz.

The 8031/8051 microcontroller has four machine cycles. These are:

1. External program memory fetch cycle
2. External data memory read cycle
3. External data memory write cycle
4. Port operation cycle
The timing diagram provides information about the various conditions of the signal while a
machine cycle is executed. The following section describes the timing diagram of the various
machine cycles.
5. 2 MICROPROCESSORS AND MICROCONTROLLERS

External Program Memory Fetch Cycle

The External program memory fetch machine cycle is executed by the 8031/8051 to fetch
the opcode and subsequent instruction bytes from the memory. The timing diagram of an external
memory fetch cycle is shown in the Fig. 5.2. During one machine cycle (6 states), two consecutive
bytes of program memory are read. In one-byte instruction, the second byte is discarded. The
timing of various signals involved in the fetch operation are shown in the timing diagram in Fig. 5.2.
Read Second Byte of the Instruction
or Read Opcode of next Instruction
Read Opcode or Memory Read/Write Cycle
® ® ® ®
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
CLK

S1 S2 S3 S4 S5 S6 ®
® ® ® ® ® ® ® ® ®
® ®

ALE

PSEN

AD7 - AD0 Low Byte Address Low Byte Address

Opcode D7 - D0
(P0.7 - P0.0) A7 - A0(PClb) A7 - A0(PClb/DPlb)

A15 - A8
(P2.7 - P2.0) High Byte Address A15 - A8(PChb) High Byte Address A15 - A8(PChb/DPhb )

Fig. 5.2 : Timing diagram of an external program memory fetch cycle.

1. At the falling edge of phase P2 of first state S1, the microcontroller outputs the low byte address on AD7-AD0 lines
and high byte address on A15-A8 lines. For program memory fetch, the content of the Program Counter (PC) is the
address of the program code. The ALE is asserted high to enable the address Latch.
2. At the middle of state S2, the ALE is asserted low and this enables the Latch to take low byte of the address and
keep on its output lines.
3. The program store enable PSEN is asserted low to fetch the opcode from the memory and load on the
AD7-AD0 lines at the state S3.
4. The microcontroller utilizes the first three states (S1, S2 and S3) to fetch the opcode from the memory.
5. During the remaining three states of one machine cycle (S4, S5 and S6), the microcontroller fetches the second byte
of the same instruction or opcode of the next instruction or executes the external memory read/write cycle.
6. When executing the one-byte instruction, the states S4, S5 and S6 are used by the processor for internal
operations to decode the instructions and for completing the task specified by the one-byte instruction.
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051 5. 3

External Data Memory Read Cycle

The memory read cycle is executed by the 8031/8051 to read a data from the external data
memory. The data memory read cycle is executed immediately after an opcode fetch if the instruction
execution requires an external data memory access. The timing diagram of the external memory
read cycle is shown in Fig. 5.3. The timings of various signals involved in read operation are shown
in the timing diagram.
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

CLK
S4 ® S5 ® S6 S1 S2 S3 ®
® ® ® ® ® ® ® ® ®

ALE
RD

AD7 - AD0 Low Byte Address

Data D7 - D0
(P0.7 - P0.0) A 7 - A0(DP lb)

A15 - A8
(P2.7 - P2.0) High Byte Address A15 - A8(DPhb)

Fig. 5.3 : Timing diagram of an external data memory read cycle.

1. External memory read operation needs six states. In one-byte instruction, when the external memory access is
required, these six states are S4, S5 and S6 of the first machine cycle and S1, S2 and S3 of the second machine
cycle. (In two-byte instruction, when external memory access is required these six states are S1 to S6 of the
second machine cycle.)

2. At the first half of the state S4, the ALE is asserted high to enable the address latch.In this state, the microcontroller
outputs the content of the Data Pointer low (DPl b ) on AD7- AD0 lines and the content of the Data Pointer high (DP hb)
on A15-A8 lines.

3. At the S1 state of the second machine cycle, the memory read signal is asserted low and the data in the specified
address can be read and placed on the AD 7-AD0 lines. The read signal is asserted low for the three states S1, S2
and S3 of the second machine cycle.

4. At the end of the S3 state of the second cycle, the RD signal is asserted low and at this time the data is latched
into the microcontroller.

5. The high byte of address A 15-A8 is valid for six states, i.e., from the S4 of the first machine cycle to S3 of second
machine cycle.

6. At the last three states of the second machine cycle, the microcontroller reads the next byte of program memory
and discards it.
5. 4 MICROPROCESSORS AND MICROCONTROLLERS

External Data Memory Write Cycle

The memory write cycle is executed by the 8031/8051 to store the data to the external data
memory. The timing diagram of the memory write cycle is shown in Fig. 5.4. The timings of
various signals involved in write operation are shown in the timing diagram.
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

CLK
S4 ® S5 ® S6 ® S1 ® S2 ® S3 ®
® ® ® ® ® ®

ALE
WR

AD7 - AD0 Low Byte Address

Data D7 - D0
(P0.7 - P0.0) A7 - A0(DPlb)

A15 - A8
(P2.7 - P2.0) High Byte Address A15 - A8(DPhb)

Fig. 5.4 : Timing diagram of an external data memory write cycle.

1. This write operation needs six states. In one-byte instruction, when the external memory access is required,
these six states are S4, S5 and S6 of the first machine cycle and S1, S2 and S3 of the second machine cycle.
(In two-byte instruction, when external memory access is required these six states are S1 to S6 of the second
machine cycle.)
2. At the first half of the state S4, the ALE is asserted high to enable the address latch. In this state, the
microcontroller outputs the content of the Data Pointer low (DPlb) on the AD7- AD0 lines and the content of Data
Pointer high (DPhb) on the A15-A8 lines.
3. At the S1 state of the second machine cycle, the memory write signal is asserted low and the data is output
on the AD7-AD0 lines. The write signal is asserted low by the microcontroller for three states S1, S2 and S3
of the second machine cycle.
4. At the end of the S3 state of the second cycle, the WR signal is asserted low and at this time the data is
latched into the external memory.
5. The high byte of address A8-A15 valid for six states, i.e., from S4 of the first machine cycle to S3 of the second
machine cycle.
6. At the last three states of the second machine cycle, the microcontroller reads the next byte of the program
memory and discards it.
Port Operation Cycle
The port value can be changed during the port operation machine cycle. The timing diagram
of the port operation cycle is shown in the Fig. 5.5. The various signals during the port operation
cycle are shown in the timing diagram. By using some instructions we can change the port value
immediately. For this, the 8031/8051 executes the port operation cycle.
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051 5. 5

1. The port operation cycle needs six states. When port operation is required in 1-byte instruction, these six states
are S4, S5 and S6 of the first machine cycle and S1, S2 and S3 of the second machine cycle.
2. In the fifth state S5 of the every machine cycle, all the port values are sampled.
3. The ports P0 and P1 are sampled at phase P1 of state S5. The ports P2, P3, RST are sampled at phase P2 of the
state S5 in the first machine cycle.
4. The port values are changed by placing the new value on the specified port.
5. The changes in the new value takes place at the S1 state of the second machine cycle.
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

CLK
S4 S5 S6 S1 S2 S3 ®
® ® ® ® ® ® ® ® ® ®
®

ALE
Sampling
Time
®
®
P0, P1 Inputs
Sampled Sampling
® Time
®
P2, P3, RST
Inputs Sampled

Port Old Data New Data

Fig. 5.5 : Timing diagram of a port operation cycle.

Timing Diagram of 8031/8051 Instructions

The size of an 8031/8051 instruction is one to three bytes. The first byte is opcode and the
subsequent bytes are address or data. The 8031/8051 microcontroller executes the instructions in one to
four machine cycles. Based on the method of execution of the machine cycles, the instructions can be
classified as shown below. The various operations performed during execution is also shown below.
Case (i) : 1-byte, 1-cycle - Opcode fetch (3 states) + Dummy program memory fetch (3 states)
Case (ii) : 2-byte, 1-cycle - Opcode fetch (3 states) + Fetch second byte of instruction (3 states)
Case (iii) : 1-byte, 2-cycle - Opcode fetch (3 states) + Data memory read/write (6 states) +
dummy program memory fetch (3 states)
Case (iv) : 2-byte, 2-cycle - Opcode fetch (3 states) + Fetch second byte of instruction (3 states)
+ Data memory read/write (6 states)
Case (v) : 3-byte, 2-cycle - Opcode fetch (3 states) + Fetch second byte (3 states) + fetch
third byte (3 states) + dummy program memory fetch (3 states)
Case (vi) : 1-byte, 4-cycle - Opcode fetch (3 states) + Dummy fetches (7 × 3 states)
The timing diagram of MOVX and ADD instructions are shown in Fig. 5.6 and Fig. 5.7 respectively:
 5. 6
Read Opcode of Next
Instruction from Program
Read Opcode Read Data from Memory ® Memory and Discard
® ® ® ® ®
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
CLK

® ® ® ® ® ® ®
S1 ® ® S2 ® S3 ® ® S4 ® S5 ® ® S6 ® S1 ® S2 ® ® S3 ® ® S4 ® S5 ® S6 ®

ALE

PSEN

RD

AD7 - AD0 Opcode of Next

1AH(PClb) Opcode E0H 4CH(DPlb) Data 7FH from Memory IBH(PClb )
(P0.7 - P0.0) Instruction

A15 - A8
20H(PChb) 35H(DPhb) 20H(PChb)
(P2.7 - P2.0)

Fig. 5.6 : Timing diagram of MOVX A, @DPTR.

MICROPROCESSORS AND MICROCONTROLLERS
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051 5. 7

Timing diagram of MOVX A,@DPTR

The MOVX A,@DPTR instruction is used to move the content of the data memory addressed
by the DPTR to the A-register (or accumulator). The timing diagram of this instruction is shown in
Fig. 5.6.

The MOVX A,@DPTR is a one-byte instruction and executed in two machine cycles. In
the first three states (S1, S2 and S3) of the first machine cycle, the opcode is fetched and the next
six states (S4, S5 and S6 of the first machine cycle and S1, S2 and S3 of the second machine
cycle) are used for data memory read operation. During the last three states (S4, S5 and S6) of the
second machine cycle, a dummy program memory fetch is performed and it is discarded. The
controller will not increment the program counter for this dummy fetch.

In the timing diagram shown in Fig. 5.6 it is assumed that 201AH is the address of the
program memory where the instruction is stored. Also, it is assumed that the content of the DPTR
(Data Pointer) is 354CH and the content of the data memory location with address 354CH be 7FH.
The opcode of the MOVX A,@ DPTR instruction is E0H.
Timing diagram of ADD A, #DATA

The instruction ADD A,#data is used to add an 8-bit immediate data to the A-register
(accumulator). The timing diagram of this instruction is shown in Fig. 5.7. The ADD A,#data is a
two-byte instruction and executed in one machine cycle. In the first three states (S1, S2 and S3) of
the machine cycle, the opcode is fetched from the program memory. In the next three states (S4,
S5 and S6), the immediate data (which is the second byte of instruction) is fetched from the
program memory.
® Read Opcode Read 2nd Byte of the Instruction
®
® ®
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
CLK

S1 S2 ® S3 S4 S5 ® S6 ®
® ® ® ® ® ® ® ® ®

ALE

PSEN

AD7 - AD0
FFH(PClb) Opcode 24H 00H(PClb) Data C2H
(P0.7 - P0.0)

A15 - A8
(P2.7 - P2.0) 20H(PChb) 21H(PChb)

Fig. 5.7 : Timing diagram of ADD A, #10H.

5. 8 MICROPROCESSORS AND MICROCONTROLLERS

In the timing diagram shown in Fig. 5.7, it is assumed that 20FFH and 2100H are the address
of the program memory where the two bytes of the instruction are stored. Also, it is assumed that
the immediate data in the instruction is C2H. The opcode of ADD A,#data instruction is 24H.
5.2 A DD RES S ING M OD ES
Every instruction of a program has to operate on a data. The method of specifying the data to
be operated by the instruction is called addressing. The 8031/8051 has the following types of addressing:
1. Immediate addressing
2. Direct addressing
3. Register addressing
4. Register indirect addressing
5. Implied addressing
6. Relative addressing
Immediate Addressing
In immediate addressing mode, an 8/16-bit immediate data/constant is specified in the instruction itself.
Example :
MOV A, #6CH
Move the immediate data 6CH given in the instruction to the A-register. (Accumulator).
Example :
MOV DPTR, #0100H
Load the immediate 16-bit constant given in the instruction in the DPTR (Data pointer). This constant will be an
address of the data memory location.
Direct Addressing
In direct addressing mode, the address of the data is directly specified in the instruction. The direct address can be
the address of an internal data RAM location (00H to 7F H ) or the address of a special function register (80H to FF H ).
Example :
MOV A,07 H
The address of the R7-register of bank-0 is 07. This instruction will move the content of the R7-register to the
A-register (Accumulator).
Register Addressing
In register addressing mode, the instruction will specify the name of the register in which the data is available.
Example :
MOV R2,A
The content of the A-register (accumulator) is moved to register R2 of the currently selected memory bank.

Register Indirect Addressing

In this mode, the instruction specifies the name of the register in which the address of the data is available. The
internal data RAM locations (00H to 7FH ) can be addressed indirectly through registers R1 and R0. The external RAM can be
addressed indirectly through DPTR.
Example :
MOV A,@R0
The internal RAM location R0 holds the address of the data. The content of the RAM location addressed by R0 is
moved to the A-register (Accumulator).
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051 5. 9

Implied Addressing
In implied addressing mode, the instruction itself specifies the data to be operated by the instruction.
Example :
CPL C
Complement carry flag.
Relative Addressing

In relative addressing mode, the instruction specifies the address relative to the program counter . The instruction
will carry an offset whose range is -12810 to + 12710 . The offset is added to the PC to generate the 16-bit physical address.
Example :
JC Offset
If carry is one, the program control jumps to an address obtained by adding the content of the program counter
and offset value in the instruction.

5.3 CLASSIFICATION OF 8031/8051 INSTRUCTIONS

The 8031/8051 instructions can be classified into the following five groups:
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branching instructions
5. Boolean instructions
The summary of 8031/8051 instructions are provided in Table-5.1. The meaning of mnemonics
used in the instruction set are listed in Table-5.2. The instructions affecting the flags are also listed
in Table-5.3.
TABLE-5.1 : SUMMARY OF 8031/8051 INSTRUCTION SET

S.No. Mnemonic Opcode Size of Time taken to execute

instruction the instruction
in bytes in clock periods

I. DATA TRANSFER INSTRUCTIONS

1. MOV A,Rn 11 1 0 1 r r r 1 12
2. MOV A,direct 11 1 0 0 1 0 1 2 12
3. MOV A,@Ri 11 1 0 0 1 1 i 1 12
4. MOV A, #data 01 1 1 0 1 0 0 2 12
5. MOV Rn,A 11 1 1 1 r r r 1 12
6. MOV Rn,direct 10 1 0 1 r r r 2 24
7. MOV Rn,#data 01 1 1 1 r r r 2 12
8. MOV direct,A 11 1 1 0 1 0 1 2 12
9. MOV direct,Rn 10 0 0 1 r r r 2 24
5. 10 MICROPROCESSORS AND MICROCONTROLLERS

Table-5.1 continued ...

S.No. Mnemonic Opcode Size of Time taken to execute

instruction the instruction
in bytes in clock periods
10. MOV direct,direct 1 0 0 0 0 1 0 1 3 24
11. MOV direct,@ Ri 1 0 0 0 0 1 1 i 2 24
12. MOV direct,#data 0 1 1 1 0 1 0 1 3 24
13. MOV @Ri,A 1 1 1 1 0 1 1 i 1 12
14. MOV @Ri,direct 1 0 1 0 0 1 1 i 2 24
15. MOV @Ri,#data 0 1 1 1 0 1 1 i 2 12
16. MOV DPTR,#data16 1 0 0 1 0 0 0 0 3 24
17. MOVC A,@A+ DPTR 1 0 0 1 0 0 1 1 1 24
18. MOVC A,@A+PC 1 0 0 0 0 0 1 1 1 24
19. MOVX A,@ Ri 1 1 1 0 0 0 1 i 1 24
20. MOVX A,@DPTR 1 1 1 0 0 0 0 0 1 24
21. MOVX @Ri,A 1 1 1 1 0 0 1 i 1 24
22. MOVX @DPTR,A 1 1 1 1 0 0 0 0 1 24
23. PUSH direct 11 0 0 0 0 0 0 2 24
24. POP direct 1 1 0 1 0 0 0 0 2 24
25. XCH A,Rn 1 1 0 0 1 r r r 1 12
26. XCH A,direct 1 1 0 0 0 1 0 1 2 12
27. XCH A,@Ri 1 1 0 0 0 1 1 i 1 12
28. XCHD A,@Ri 1 1 0 1 0 1 1 i 1 12
II. ARITHMETIC INSTRUCTIONS
29. ADD A,Rn 00 1 0 1 r r r 1 12
30. ADD A,direct 0 0 1 0 0 1 0 1 2 12
31. ADD A, @Ri 0 0 1 0 0 1 1 i 1 12
32. ADD A,#data 0 0 1 0 0 1 0 0 2 12
33. ADDC A,Rn 0 0 1 1 1 r r r 1 12
34. ADDC A,direct 0 0 1 1 0 1 0 1 2 12
35. ADDC A,@Ri 0 0 1 1 0 1 1 i 1 12
36. ADDC A,#data 0 0 1 1 0 1 0 0 2 12
37. SUBB A,Rn 10 0 1 1 r r r 1 12
38. SUBB A,direct 1 0 0 1 0 1 0 1 2 12
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051 5. 11

Table-5.1 continued ...

S.No. Mnemonic Opcode Size of Time taken to execute

instruction the instruction
in bytes in clock periods
39. SUBB A,@Ri 1 0 0 1 01 1 i 1 12

40. SUBB A,#data 1 0 0 1 01 0 0 2 12

41. INC A 0 0 0 0 01 0 0 1 12
42. INC Rn 0 0 0 0 1 r r r 1 12
43. INC direct 0 0 0 0 0 1 0 1 2 12
44. INC @Ri 0 0 0 0 0 1 1 i 1 12
45. DEC A 0 0 0 1 0 1 0 0 1 12
46. DEC Rn 0 0 0 1 1 r r r 1 12
47. DEC direct 0 0 0 1 0 1 0 1 2 12
48. DEC @Ri 0 0 0 1 0 1 1 i 1 12
49. INC DPTR 1 0 1 0 0 0 1 1 1 24
50. MUL AB 1 0 1 0 0 1 0 0 1 48
51. DIV AB 1 0 0 0 0 1 0 0 1 48
52. DA A 1 1 0 1 0 1 0 0 1 12

III. LOGICAL INSTRUCTIONS

53. ANL A,Rn 0 1 0 1 1 r r r 1 12
54. ANL A,direct 0 1 0 1 0 1 0 1 2 12
55. ANL A,@ Ri 0 1 0 1 0 1 1 i 1 12
56. ANL A,#data 0 1 0 1 0 1 0 0 2 12
57. ANL direct,A 0 1 0 1 0 0 1 0 2 12
58. ANL direct,#data 0 1 0 1 0 0 1 1 3 24
59. ORL A,Rn 0 1 0 0 1 r r r 1 12
60. ORL A,direct 0 1 00 0 1 0 1 2 12
61. ORL A,@Ri 0 1 0 0 0 1 1 i 1 12
62. ORL A,#data 0 1 0 0 0 1 0 0 2 12
63. ORL direct,A 0 1 0 0 0 0 1 0 2 12
64. ORL direct,#data 0 1 0 0 0 0 1 1 3 24
65. XRL A,Rn 0 1 1 0 1 r r r 1 12
66. XRL A,direct 0 1 1 0 0 1 0 1 2 12
5. 12 MICROPROCESSORS AND MICROCONTROLLERS

Table-5.1 continued …
Size of Time taken to execute
S.No. Mnemonic Opcode instruction the instruction
in bytes in clock periods
67. XRL A,@ Ri 0 1 1 0 0 1 1 i 1 12
68. XRL A,#data 0 1 1 0 0 1 0 0 2 12
69. XRL direct,A 0 1 1 0 0 0 1 0 2 12
70. XRL direct,#data 0 1 1 0 0 0 1 1 3 24
71. CLR A 1 1 1 0 0 1 0 0 1 12
72. CPL A 1 1 1 1 0 1 0 0 1 12
73. RL A 0 0 1 0 0 0 1 1 1 12
74. RLC A 0 0 1 1 0 0 1 1 1 12
75. RR A 0 0 0 0 0 0 1 1 1 12
76. RRC A 0 0 0 1 0 0 1 1 1 12
77. SWAP A 1 1 0 0 0 1 0 0 1 12
IV. BRANCHING INSTRUCTIONS
78. ACALL addr11 a10 a9 a8 1 0 0 0 1 2 24
79. LCALL addr16 0 0 0 1 0 0 1 0 3 24
80. RET 0 0 1 0 0 0 1 0 1 24

81. RETI 0 0 1 1 0 0 1 0 1 24

82. AJMP addr 11 a10 a9 a8 0 0 0 0 1 2 24

83. LJMP addr 16 0 0 0 0 0 0 1 0 3 24
84. SJMP offset 1 0 0 0 0 0 0 0 2 24
85. JMP @A+ DPTR 0 1 1 1 0 0 1 1 1 24
86. JZ offset 0 1 1 0 0 0 0 0 2 24
87. JNZ offset 0 1 1 1 0 0 0 0 2 24
88. CJNE A,direct,offset 1 0 1 1 0 1 0 1 3 24
89. CJNE A,#data,offset 1 0 1 1 0 1 0 0 3 24
90. CJNE @Rn,#data,offset 1 0 1 1 1 r r r 3 24
91. CJNE @Ri,#data,offset 1 0 1 1 0 1 1 i 3 24
92. DJNZ Rn,offset 1 0 1 1 1 r r r 2 24
93. DJNZ direct,offset 1 1 0 1 0 1 0 1 3 24
94. NOP 0 0 0 0 0 0 0 0 1 12
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051 5. 13

Table-5.1 continued …

Size of Time taken to execute

S.No. Mnemonic Opcode instruction the instruction
in bytes in clock periods
V. BOOLEAN INSTRUCTIONS
95. CLR C 1 1 0 000 1 1 1 12
96. CLR bit 1 1 0 0 00 1 0 2 12
97. SETB C 1 1 0 1 00 1 1 1 12
98. SETB bit 1 1 0 1 00 1 0 2 12
99. CPL C 1 0 1 100 11 1 12
100. CPL bit 1 0 1 1 00 1 0 2 12
101. ANL C,bit 1 0 0 0 00 1 0 2 24
102. ANL C,/bit 1 0 1 1 00 00 2 24
103. ORL C,bit 0 1 1 100 1 0 2 24
104. ORL C,/bit 1 0 1 0 00 0 0 2 24
105. MOV C,bit 1 0 1 0 00 1 0 2 12
106. MOV bit,C 1 0 0 1 00 10 2 24
107. JC offset 0 1 0 000 0 0 2 24
108. JNC offset 0 1 0 1 00 0 0 2 24
109. JB bit,offset 0 0 1 0 00 0 0 3 24
110. JNB bit,offset 0 0 1 1 00 0 0 3 24
111. JBC bit,offset 0 0 0 100 0 0 3 24

Symbols Used in Summary of Instruction Set (Table-5.1)

Rn Register R7-R 0 of the currently selected register bank

direct 8-bit address of the internal RAM/SFR
@Ri Internal RAM addressed indirectly through R 1 or R0
#data Immediate 8-bit data/constant
#data16 Immediate 16-bit data/constant
addr16 Immediate 16-bit address of memory
addr11 lower 8 bits of the immediate 11-bit address
offset signed 8-bit offset
bit 8-bit address of the bit in bit-addressable RAM/SFR
A Accumulator
@A+ Memory addressed indirectly through the accumulator
@DPTR Data memory addressed indirectly through the DPTR.
5. 14 MICROPROCESSORS AND MICROCONTROLLERS

Symbols Used in Opcode

rrr 3-bit register field representing the 8 registers of a bank. The code 000 to 111
represents the registers R0 to R7 respectively.
i 1-bit register field representing R0 or R1. For R 0, i = 0 and for R1, i = 1.
a10 a9 a8 Upper 3 bits of 11-bit address and can take eight possible values 000 to 111.

TABLE - 5.2 : MEANING OF MNEMONICS USED IN THE INSTRUCTION SET

Mnemonic Meaning/Expansion Mnemonic Meaning/Expansion

ACALL Absolute subroutine call MOV C Move code byte

ADD Add MOV X Move to/from external RAM
ADDC Add including carry MOV Move to/from internal RAM
AJMP Absolute jump MUL Multiply
ANL AND Logic operation NOP No operation
CJNE Compare and jump if not equal ORL OR logic operation

CLR Clear POP Retrieve from stack (POP from

stack)
CPL Complement
PUSH Store in stack (push to stack)
DA Decimal adjust
RET Return from subroutine
DEC Decrement
RETI Return from interrupt
DIV Divide
RL Rotate left
DJNZ Decrement and jump if not zero
RLC Rotate left through carry
INC Increment
RR Rotate right
JB Jump if bit is set
RRC Rotate right through carry
JBC Jump if bit is set and clear bit
SETB Set bit
JC Jump on carry
SJMP Short jump
JMP Jump
SUBB Subtract with borrow
JNB Jump if bit is not set
SWAP Swap/Exchange lower and upper
JNC Jump on no carry nibble
JNZ Jump on not zero XCH Exchange
JZ Jump on zero XCHD Exchange digit
LCALL Long subroutine call XRL Exclusive-OR logic
LJMP Long jump
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051 5. 15

TABLE - 5.3 : INSTRUCTIONS AFFECTING FLAGS OF 8031/8051

Instruction CF AF OF PF
ADD + + + +
ADDC + + + +
ANL C,bit + - - -
ANL C,/bit + - - -
CJNE + - - -
CLR C 0 - - -
CPL C + - - -
DIV 0 - 0 -
DA + + - +
MUL 0 - + -
MOV C, bit + - - -
ORL C, bit + - - -
ORL C,/bit + - - -
RRC A + - - -
RLC A + - - -
SETB C 1 - - -
SUBB + + + +

Note : "+" indicate that the flag is modified

"0" indicates that the flag is always 0
"1" indicates that the flag is always 1

5.4 D ATA TRANSFER I NS TRUCTION S

The instruction set of the 8031/8051 microcontroller includes a variety of instructions for
data transfer between the registers and the memory locations. The various mnemonics used for
data transfer instructions are MOV, MOVC, MOVX, PUSH, POP, XCH and XCHD, and they
perform any one of the following operations:
� Copy the content of an SFR to the internal memory or vice versa.
� Load an immediate operand to the SFR/internal memory.
� Exchange the content of the SFR/internal memory with the accumulator.
� Copy the content of the program memory to the accumulator.
� Copy the content of the data memory to the accumulator or vice versa.
The data transfer instructions of 8031/8051 are listed in Table-5.4 with a brief explanation
about each instruction.
TABLE - 5.4 : DATA TRANSFER INSTRUCTIONS

S.No. Instruction Symbolic representation Explanation 5. 16

1. MOV A,Rn (A) ← (Rn) The content of register Rn is moved to the accumulator (A-register).
The Rn can be any one of the 8 registers of the currently selected bank.
2. MOV A,direct direct = 8-bit address of The content of internal RAM/SFR (whose address is specified directly
internal RAM/SFR in the instruction) is moved to accumulator (A-register).
(A) ← (RAM/SFR)
3. MOV A,@Ri (Ri) = Internal RAM address The content of internal RAM memory (whose address is specified by
(A) ← (RAM) the Ri-register) is moved to the accumulator (A-register). The register
Ri can be either R0 or R1 or the currently selected register bank.
4. MOV A,#data (A) ← data The data given in the instruction is moved to the accumulator (A-register).
5. MOV Rn,A (Rn) ← (A) The content of the accumulator is moved to register Rn, where Rn is
any one of the 8 registers of the currently selected register bank.
6. MOV Rn,direct direct = 8-bit address of The content of internal RAM/SFR (whose address is directly specified
internal RAM/SFR in the instruction) is moved to register Rn, where Rn is any one of the
(Rn)← (RAM/SFR) 8 registers of the currently selected register bank.
7. MOV Rn,#data (Rn) ← data The immediate data given in the instruction is moved to register Rn,
where Rn is any one of the 8 registers of the currently selected register
bank.
8. MOV direct,A direct = 8-bit address of internal The content of the accumulator is moved to internal RAM/SFR
RAM/SFR (RAM/SFR) ← (A) whose address is directly specified in the instruction.
9. MOV direct,Rn direct = 8-bit address of internal The content of register Rn is moved to internal RAM/SFR
RAM/SFR (RAM/SFR) ← (Rn) whose address is directly specified in the instruction.
10. MOV direct,direct direct = 8-bit address of internal The content of one internal RAM/SFR is moved to another
RAM/SFR internal RAM/SFR. The address of the source and destination
(RAM/SFR) ←(RAM/SFR) are directly specified in the instruction.
11. MOV direct,@Ri (Ri) = Internal RAM address The content of internal RAM whose address is specified by Ri
of source operand is moved to another internal RAM/SFR whose address is
direct = Internal RAM/SFR directly specified in the instruction. The register Ri can be
address of destination operand either R0 or R1.
(RAM/SFR) ← (RAM)
MICROPROCESSORS AND MICROCONTROLLERS
Table-5.4 continued …
S.No. Instruction Symbolic representation Explanation
12. MOV direct,#data direct = Address of internal RAM/SFR The immediate data given in the instruction is moved to the
(RAM/SFR) ← data internal RAM/SFR, whose address is directly specified in the
instruction.
13. MOV @Ri,A (Ri) = Internal RAM address The content of the accumulator is moved to an internal RAM
(RAM) ← (A) location whose address is specified by the Ri-register. The
register Ri can be either R0 or R1.
14. MOV @Ri,direct direct = Internal RAM/SFR address The content of the internal RAM/SFR whose address is directly
of source operand specified in the instruction is moved to another internal RAM
(Ri) = Internal RAM address of location whose address is specified by the Ri-register. The
destination operand. register Ri can be either R0 or R1.
(RAM) ← (RAM/SFR)
15. MOV @Ri,#data (Ri) = Internal RAM address The immediate data given in the instruction is moved to an
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051

(RAM) ← data internal RAM location, whose address is specified by the

Ri-register. The register Ri can be R0 or R1.
16. MOV DPTR,#data16 (DPTR) ← data16 The 16-bit constant (data16) given in the instruction is moved
to the DPTR. (The content of the DPTR is used as address of
external data memory in the subsequent instruction.)
17. MOVC A,@A+DPTR (A) + (DPTR) = Address of program memory This instruction will copy a byte from the code/program memory
(A) ← (program memory) to the accumulator. The address of the program memory is given
by the sum of the content of the DPTR and accumulator before
the move operation.
18. MOVC A,@A+PC (PC) ← (PC)+1 This instruction will copy a byte from the code/program memory
(A) + (PC) = Address of program memory to the accumulator. The address of the program memory is given
(A) ← (program memory) by the sum of the PC and the accumulator. Here, the content of
the PC is incremented before adding to A to get the address of
the code memory.
19. MOVX A,@Ri (Ri) = 8-bit address external data RAM The content of external data RAM is moved to the accumulator.
(A) ← (RAM) The content of register Ri is the 8-bit address of the external
memory. The register Ri can be either R0 or R1 of the currently
selected register bank.
20. MOVX A,@DPTR (DPTR) = 16-bit address of external The content of external data RAM is moved to the accumulator.
data RAM (A) ← (RAM) The content of DPTR is the 16-bit address of the external RAM.
5. 17
Table-5.4 continued …
S.No. Instruction Symbolic representation Explanation 5. 18

21. MOVX @Ri,A (Ri) = 8-bit address of external data RAM The content of the accumulator is moved to the external data
(RAM) ← (A) RAM. The content of the Ri is the 8-bit address of external
RAM. The register Ri can be either R0 or R1 of the currently
selected register bank.
22. MOVX @DPTR,A (DPTR) = 16-bit address of external data RAM The content of the accumulator is moved to the external data
(RAM) ← (A) RAM. The content of the DPTR is the 16-bit address of the
external RAM.

23. PUSH direct (SP) ← (SP) + 1 The stack pointer is incremented by one. The content of the internal
direct = 8-bit address of internal RAM/SFRinternal RAM/SFR (whose address is directly specified in the instruction)
((SP)) ← (RAM/SFR) is moved to the internal RAM memory pointed by the SP.

24. POP direct direct = 8-bit address of internal RAM/SFR The content of the internal RAM memory pointed by the SP is
(RAM/SFR) ← ((SP)) moved to the internal RAM/SFR (whose address is directly
(SP) ← (SP) − 1 specified in the instruction). Then the stack pointer is
decremented by one.

25. XCH A,Rn (A) →

← (Rn) The content of register Rn is exchanged with the accumulator.
The register Rn can be any one of the eight registers of the
currently selected register bank.

26. XCH A,direct direct = 8-bit address of internal RAM/SFR The content of the internal RAM /SFR whose address is directly
(A) → (RAM/SFR) specified in the instruction is exchanged with the accumulator.
←

27. XCH A,@Ri (Ri) = 8-bit address of internal RAM The content of the internal RAM whose address is specified by
(A) →
← (RAM) the Ri-register is exchanged with the accumulator. The register
Ri can be either R0 or R1 of the currently selected register bank.

28. XCHD A,@Ri (Ri) = 8-bit address of internal RAM The lower nibble of the internal RAM addressed by Ri-register
(A) → ← (RAM) is exchanged with the lower nibble of the accumulator. The
3-0 3-0
content of the upper nibble of RAM and accumulator are not
altered. The Register Ri can be either R0 or R1 of the currently
selected register bank.
MICROPROCESSORS AND MICROCONTROLLERS
5.5 ARI THM ETI C I NST RU CTION S

The arithmetic group includes instructions for performing addition, subtraction, multiplication, division, increment and decrement
operation on the binary data. The mnemonic used in arithmetic instructions are ADD, ADDC, SUBB, INC, DEC, MUL, DIV and DA. The
results of most of the arithmetic operations are stored in the accumulator except a few decrement and increment operations. The
arithmetic instructions except increment and decrement instructions modify the flags of 8031/8051. The arithmetic instructions of 8031/
8051 are listed in Table-5.5.
TABLE- 5.5 : ARITHMETIC INSTRUCTIONS OF 8031/8051

S.No. Instruction Symbolic representation Explanation

29. ADD A,Rn (A) ← (A) + (Rn) The content of register Rn and the accumulator are added. The
result is stored in the accumulator. The register Rn can be any
one of the eight registers of the currently selected register bank.
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051

30. ADD A,direct direct = 8-bit address of internal RAM/SFR The content of internal RAM/SFR and accumulator are added.
(A) ← (A) + (RAM/SFR) The result is stored in the accumulator. The address of internal
RAM/SFR is directly specified in the instruction.
31. ADD A,@Ri (Ri) = Address of internal RAM The content of the internal RAM and the accumulator are added.
(A) ← (A) + (RAM) The result is stored in the accumulator. The register Ri holds the
address of the internal RAM and Ri can be either R0 or R1
of the currently selected register bank.

32. ADD A,#data (A) ← (A) + data The immediate data given in the instruction is added to
accumulator.
33. ADDC A,Rn (A) ← (A) + CF + (Rn) This instruction is same as ADD A,Rn except that the current
value of carry flag (i.e., previous carry) is also added to the sum.
34. ADDC A,direct direct = address of internal RAM/SFR This instruction is same as ADD A,direct except that the
(A) ← (A) + CF + (RAM/SFR) current value of carry flag (i.e., previous carry) is also added
to the sum.
35. ADDC A,@Ri (Ri) = address of internal RAM This instruction is same as ADD A,@Ri except that the current
(A) ← (A) + CF + (RAM) value of the carry flag (i.e., previous carry) is also added
to sum.
5. 19
Table-5.5 continued …
S.No. Instruction Symbolic representation Explanation 5. 20
36. ADDC A,#data (A) ← (A) + CF + data The immediate data given in the instruction, the carry flag and
the content of the accumulator are added. The result is stored
in the accumulator.
37. SUBB A,Rn (A) ← (A) − CF − (Rn) The carry flag and the content of the Rn-register are subtracted
from the content of the accumulator. The result is stored in the
accumulator. The register Rn can be any one of the 8 registers
of the currently selected register bank.
38. SUBB A,direct direct = Address of internal RAM/SFR The carry flag and the content of RAM/SFR (specified by
(A) ← (A) − CF− (RAM/SFR) direct address) are subtracted from the content of the
accumulator. The result is stored in the accumulator.

39. SUBB A,@Ri (Ri) = Address of internal RAM The carry flag and the content of RAM (specified by the Ri-register)
(A) ← (A) − CF − (RAM) are subtracted from the content of the accumulator. The result is
stored in the accumulator. The register Ri can be either R0 or R1 of
the currently selected register bank.
40. SUBB A,#data (A)← (A) − CF − data The carry flag and the data given in the instruction are subtracted
from the accumulator. The result is stored in the accumulator.
41. INC A (A) ← (A) + 1 The content of the accumulator is incremented by one.
42. INC Rn (Rn) ← (Rn) +1 The content of register Rn is incremented by one. The Rn can be
any one of the eight registers of the currently selected register
bank.
43. INC direct direct = Address of internal RAM/SFR The content of RAM/SFR (whose address is directly given in the
(RAM/SFR) ← (RAM/SFR) +1 instruction) is incremented by one.
44. INC @Ri (Ri) = Address of internal RAM/SFR The content of RAM (whose address is specified by Ri) is
(RAM) ← (RAM) +1 incremented by one. The Ri can be either R0 or R1 of the currently
selected register bank.
45. DEC A (A) ← (A) − 1 The content of the accumulator is decremented by one.
46. DEC Rn (Rn) ← (Rn) − 1 The content of register Rn is decremented by one. The Rn can be
any one of the eight registers of the currently selected register bank.
MICROPROCESSORS AND MICROCONTROLLERS
Table-5.5 continued …
S.No. Instruction Symbolic representation Explanation

47. DEC direct direct = Address of internal RAM/SFR The content of RAM/SFR (whose address is directly given in the
(RAM/SFR) ← (RAM/SFR) − 1 instruction) is decremented by one.
48. DEC @Ri (Ri) = Address of internal RAM The content of RAM (whose address is specified by Ri) is
(RAM) ← (RAM) −1 decremented by one. The Ri can be either R0 or R1 of the currently
selected register bank.
49. INC DPTR (DPTR) ← (DPTR) + 1 The 16-bit content of the DPTR (Data Pointer) is incremented by one.
50. MUL AB (B) (A) ← (A) × (B) The contents of A and B registers are multiplied. The low byte of the
high low product is stored in the A-register and high byte of the product is stored
byte byte
in the B-register.
51. DIV AB (A) ← (A) ÷ (B) The content of the A-register is divided by the content of the B-register.
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051

Quotient The quotient is stored in the A-register and the remainder is stored in
(B) ← (A) MOD (B) B-register.
Remainder

52. DAA i) If (A)3 − 0 > 9 or AF = 1 then This instruction is executed after the addition of two packed BCD data,
(A)3 − 0 ← (A) 3 − 0 + 06 to convert the result in the accumulator to the packed BCD data. If the
lower nibble of the accumulator is greater than 09 or the AF is set,
ii) If (A)7 − 4 > 9 or CF = 1 then
then it is corrected by adding 06. If the upper nibble of the accumulator
(A) 7 − 4 ← (A) 7 − 4 + 06 is greater than 09 or the CF is set, then it is corrected by adding 06.

5.6 L OGI C AL I NST RUCTION S

The logical group includes instructions for performing logical AND, OR, Exclusive-OR, and Complement operations, and instructions
for right and left rotation. The mnemonic used in logical operations are ANL, ORL, XRL, CLR, CPL, RL, RLC, RR, RRC and SWAP. The
logical operations except rotate through carry do not modify the flags of 8031/8051. In rotate through carry, the carry flag alone is
modified. In most of the logical instructions, the result is stored in the accumulator and in some instructions the result is stored in the
internal RAM/SFR. The logical instructions of 8031/8051 are listed in Table-5.6 with a brief explanation about each instruction.
5. 21
TABLE - 5.6 : LOGICAL INSTRUCTIONS

S.No. Instruction Symbolic representation Explanation 5. 22

53. ANL A,Rn (A) ← (A) & (Rn) The content of the register Rn and the accumulator are bit by bit logically
ANDed, and the result is stored in the accumulator. The register Rn can
be any one of the 8 registers of the currently selected register bank.
54. ANL A,direct direct = Address of internal RAM/SFR The content of the RAM/SFR (whose address is directly given in the
(A) ← (RAM/SFR) & (A) instruction) and the accumulator are bit by bit logically ANDed, and the
result is stored in the accumulator.
55. ANL A,@Ri (Ri) = Address of internal RAM The content of the RAM (whose address is specified by Ri) and the
(A) ← (RAM) & (A) accumulator are bit by bit logically ANDed, and the result is stored in
the accumulator. The register Ri can be either R0 or R1 of the currently
selected register bank.
56. ANL A,#data (A) ← (A) & data The data given in the instruction and the content of the accumulator
are bit by bit logically ANDed, and the result is stored in the accumulator.
57. ANL direct, A direct = Address of internal RAM/SFR The content of the accumulator and the RAM/SFR are bit by bit logically
(RAM/SFR) ← (RAM/SFR) & (A) ANDed, and the result is stored in the RAM/SFR. The address of the
RAM/SFR is directly specified in the instruction.
58. ANL direct,#data direct = Address of internal RAM/SFR The data given in the instruction and the content of RAM/SFR are bit by
(RAM/SFR) ← (RAM/SFR) & data bit logically ANDed, and the result is stored in RAM/SFR. The address
of the RAM/SFR is directly specified in the instruction.
59. ORL A,Rn (A) ← (A) | (Rn) The content of the register Rn and the accumulator are bit by bit logically
ORed, and the result is stored in the accumulator. The register Rn can
be any one of the 8 registers of the currently selected register bank.
60. ORL A,direct direct = Address of internal RAM/SFR The content of the RAM/SFR (whose address is directly given in the
(A) ← (RAM/SFR) | (A) instruction) and the accumulator are bit by bit logically ORed, and the
result is stored in the accumulator.
61. ORL A,@Ri (Ri) = Address of internal RAM The contents of the RAM (whose address is specified by Ri) and the
(A) ← (RAM) | (A) accumulator are bit by bit logically ORed, and the result is stored in
the accumulator. The register Ri can be either R0 or R1 of the currently
selected register bank.
MICROPROCESSORS AND MICROCONTROLLERS
Table-5.6 continued …

S.No. Instruction Symbolic representation Explanation

62. ORL A,#data (A) ← (A) | data The data given in the instruction and the content of the accumulator are
bit by bit logically ORed, and the result is stored in the accumulator.
63. ORL direct,A direct = Address of internal RAM/SFR The contents of the accumulator and the RAM/SFR are bit by bit logically
(RAM/SFR) ← (RAM/SFR) | (A) ORed, and the result is stored in the RAM/SFR. The address of the
RAM/SFR is directly specified in the instruction.
64. ORL direct,#data direct = Address of internal RAM/SFR The data given in the instruction and the content of the RAM/SFR are bit
(RAM/SFR) ← (RAM/SFR) | data by bit logically ORed, and the result is stored in the RAM/SFR. The
address of the RAM/SFR is directly specified in the instruction.
65. XRL A,Rn (A) ← (A) ^ (Rn) The contents of register Rn and accumulator are bit by bit logically
exclusive-ORed, and the result is stored in the accumulator. The register
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051

Rn can be any one of the 8 registers of the currently selected register bank.

66. XRL A,direct direct = Address of internal RAM/SFR The contents of the RAM/SFR (whose address is directly given in the
(A) ← (RAM/SFR) ^ (A) instruction) and the accumulator are bit by bit logically exclusive-ORed,
and the result is stored in the accumulator.
67. XRL A,@Ri (Ri) = Address of internal RAM The contents of the RAM (whose address is specified by Ri) and the
(A) ← (RAM) ^ (A) accumulator are bit by bit logically exclusive-ORed, and the result
is stored in the accumulator. The register Ri can be either R0 or R1
of the currently selected register bank.
68. XRL A,#data (A) ← (A) ^ data The data given in the instruction and the content of the accumulator
are bit by bit logically exclusive-ORed, and the result is stored in the
accumulator.
69. XRL direct,A direct = Address of internal RAM/SFR The contents of the accumulator and RAM/SFR are bit by bit logically
(RAM/SFR) ← (RAM/SFR)^ (A) exclusive-ORed, and the result is stored in the RAM/SFR. The address
of the RAM/SFR is directly specified in the instruction.
70. XRL direct,#data direct = Address of internal RAM/SFR The data given in the instruction and the content of RAM/SFR are bit
(RAM/SFR) ← (RAM/SFR)^ data by bit logically exclusive-ORed, and the result is stored in the RAM/SFR.
The address of the RAM/SFR is directly specified in the instruction.
5. 23
Table-5.6 continued …
S.No. Instruction Symbolic representation Explanation 5. 24
71. CLR A (A) ← 0 The content of the accumulator is cleared.
72. CPL A (A) ← ~ (A) The content of the accumulator is complemented.

73. RL A The content of the accumulator is rotated left by one bit. The most
A
significant digit (B7) is moved to the least significant digit (B0) position.
B7 B6 B5 B4 B3 B2 B1 B0

Bn+1 ¬ Bn ; B0 ¬ B7

A
74. RLC A The content of the accumulator along with the carry is rotated left by
CF B7 B6 B5 B4 B3 B2 B1 B0
one bit. The carry is moved to the least significant digit position and
Bn+1 ¬ Bn ; B0 ¬ CF ; CF ¬ B7 the most significant digit is moved to the carry.

75. RR A The content of the accumulator is rotated right by one bit. The least
A
significant digit (B0) is moved to the most significant digit (B7) position.
B7 B6 B5 B4 B3 B2 B1 B0

Bn ¬ Bn+1 ; B7 ¬ B0

76. RRC A A The content of the accumulator along with the carry is rotated right by
CF B7 B6 B5 B4 B3 B2 B1 B0 one bit. The carry is moved to the most significant digit (position) and
the least significant digit (B0) is moved to carry.
Bn ¬ Bn+1 ; B7 ¬ CF ; CF ¬ B0

77. SWAP A (A)3-0 (A)7-4 The higher nibble of the accumulator is exchanged with the lower
nibble of the accumulator.
5.7 PROGR AM BRANCHING I NSTRUCTI ONS
Normally a program is executed sequentially and the PC (Program Counter) keeps track of the address of the instructions and it
is incremented appropriately after each fetch operation. The program branching instructions will modify the content of the PC so that,
the program control branches to a new address. The program branching instructions of 8031/8051 includes conditional and unconditional
branching instruction. In conditional branching instructions, the content of the PC is modified, only if the condition specified in the
MICROPROCESSORS AND MICROCONTROLLERS
instruction is true, whereas in unconditional branching instruction, the PC is always modified. The instructions like ACALL and LCALL
will save the previous value of the PC in the stack before modifying the PC. The program branching instructions of 8031/8051 are listed
in Table-5.7 with a brief explanation about each instruction.
TABLE - 5.7 : PROGRAM BRANCHING INSTRUCTIONS

S.No. Instruction Symbolic representation Explanation

78. ACALL addr11 (PC) ← (PC) + 2 This instruction is used to unconditionally call a subroutine which
(SP) ← (SP) + 1 resides within the same 2 k block of the program memory in which the
((SP)) ← (PC)7-0 instruction following ACALL is stored. This instruction first increments
(SP) ← (SP) + 1 the PC by two, to point to the address of the instruction next to ACALL.
((SP)) ← (PC)15-8 Next, the content of the SP is incremented by one and the low byte of PC
(PC)10-0 ← addr11 is saved in the stack memory pointed by SP. Again, the content of the SP
is incremented by one and then, high byte of PC is saved in the stack
memory pointed by the SP. Then, the 11-bit address given in the instruction
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051

is moved to the lower 11-bit position of the PC. (The 11- bit address is the
second byte of the instruction and upper 3 bits of the opcode.) Now, the
controller starts fetching the instructions from this new address.
79. LCALL addr16 (PC) ← (PC) + 3 This instruction is used to unconditionally call a subroutine anywhere
(SP) ← (SP) + 1 in the 64 k memory space. First, the PC is incremented by three to point
((SP)) ← (PC)7-0 to the next instruction. Next, the SP is incremented and the content of the
(SP) ← (SP) + 1 PC is saved in the stack memory pointed by the SP. Then, the 16-bit
((SP)) ← (PC)15-8 address given in the instruction is moved to the PC and so the controller
(PC) ← addr16 starts fetching the instruction from this new address.

80. RET (PC)15-8 ← ((SP)) This instruction is used to terminate a subroutine. On execution of this
(SP) ← (SP) − 1 instruction, the content of the stack memory pointed by the SP is moved
(PC)7-0 ← ((SP)) to the high byte of PC and SP is decremented by one. Then, the content of
(SP) ← (SP) − 1 the stack memory pointed by SP is moved to the low byte of PC and again
the SP is decremented by one.

81. RETI (PC)15-8← ((SP)) This RETI instruction is used to terminate an interrupt service subroutine.
(SP) ← (SP) − 1 This instruction moves the top of the stack to the PC similar to that of RET
(PC)7-0 ← ((SP)) instruction and in addition restores the interrupt logic to accept additional
(SP) ← (SP) − 1 interrupts of the same priority level as the one just processed.
5. 25
Table-5.7 continued …
S.No. Instruction Symbolic representation Explanation 5. 26

82. AJMP addr11 (PC) ← (PC) + 2 This instruction is used to unconditionally jump to a memory location
(PC)10-0 ← addr11 within the same 2 k block of program memory in which the instruction
following AJMP is stored. First, the PC is incremented by two to point to
the address of next instruction and then the 11-bit address given in the
instruction is moved to the lower 11-bit position of the PC. The 11-bit
address is the second byte of the instruction and upper 3 bits of opcode.

83. LJMP addr16 (PC) ← addr16 This instruction is used to unconditionally jump to any location in the
64 k memory space. Upon execution of this instruction, the 16-bit
address given in the instruction is moved to the PC, and so the controller
starts fetching the instruction from this new address.

84. SJMP offset (PC) ← (PC) + 2 This instruction is used to unconditionally transfer the program control
(PC) ← (PC) + offset to a new address obtained by adding the 8-bit signed offset to the
content of the PC. The offset will be in the range of −12810 to +12710.

85. JMP @A+DPTR (A) + (DPTR) = Address This instruction computes the address to which the program control
(PC) ← Address has to be transferred and loads this address in the PC. The address is
given by the sum of the signed 8-bit in the accumulator and the 16-bit
content of the DPTR.

86. JZ offset (PC) ← (PC) + 2 First, the content of the PC is incremented by two. Next, the content of
If (A) = 0 then the accumulator is checked. If the content of the accumulator is zero,
(PC) ← (PC) + offset then the 8-bit signed offset given in the instruction is added to the PC,
so that the program control branches to new address. If the accumulator
is not zero then PC is not modified, so that the next instruction of the
program is fetched and executed.

87. JNZ offset (PC) ← (PC) + 2 First, the content of the PC is incremented by two. Next the content of
If (A) ≠ 0 then the accumulator is checked, if the content of the accumulator is not
(PC) ← (PC) + offset zero, then the 8-bit signed offset given in the instruction is added to the
PC, so that the program control branches to a new address. If the
accumulator is zero, then PC is not modified so that the next instruction
of the program is fetched and executed.
MICROPROCESSORS AND MICROCONTROLLERS
Table-5.7 continued …

S.No. Instruction Symbolic representation Explanation

88. CJNE A,direct,offset (PC) ← (PC) + 3 First, the PC is incremented by three to point to the next instruction. The
direct = Address of internal RAM/SFR content of the accumulator and the internal RAM/SFR (whose address
If (A) ≠ (RAM/SFR) then is directly specified in the instruction) are compared. If the contents
(PC) ← (PC) + offset are not equal then the program control is transferred to a new address.
If (A) < (RAM/SFR) then, CF ← 1 The new address is the sum of the PC and offset given in the instruction.
If (A) > (RAM/SFR) then, CF ← 0 Also, if the content of the accumulator is less than RAM/SFR, then the
carry flag is set, otherwise it is cleared.

89. CJNE A,#data,offset (PC) ← (PC) + 3 This instruction is same as CJNE A,direct,offset except that the
If (A) ≠ data then comparison is performed with the immediate data given in the
(PC) ← (PC) + offset instruction and the accumulator.
If (A) < data then, CF ← 1
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051

If (A) > data then, CF ← 0

90. CJNE Rn,#data,offset (PC) ← (PC) + 3 This instruction is same as CJNE A,direct,offset except that the
If (Rn) ≠ data then comparison is performed with the content of the Rn and the immediate
(PC) ← (PC) + offset data. The Rn can be any one of the eight registers of the currently
If (Rn) < data then, CF ← 1 selected register bank.
If (Rn) > data then, CF ← 0

91. CJNE @Ri,#data,offset (PC) ← (PC) + 3 This instruction is same as CJNE A,direct,offset except that the
(Ri) = Address of internal RAM comparison is performed between the RAM (whose address is specified
If (RAM) ≠ data then by Ri) and the immediate data given in the instruction. The register Ri
(PC) ← (PC) + offset can be either R0 or R1 of the currently selected register bank.
If (Ri) < data then, CF ← 1
If (Ri) > data then, CF ← 0

92. DJNZ Rn,offset (PC) ← (PC) + 2 First, the PC is incremented by two to point to the address of the next
(Rn) ← (Rn) − 1 instruction. Then, the content of register Rn is decremented by one.
If (Rn) ≠ 0 then If the content of Rn (after decrement) is not equal to zero then, the offset
(PC) ← (PC) + offset given in the instruction is added to the PC so that, the program control
branches to a new address. The register Rn can be any one of the
eight registers of the currently selected register bank.
5. 27
Table-5.7 continued …
S.No. Instruction Symbolic representation Explanation 5. 28

93. DJNZ direct,offset (PC) ← (PC) + 2 This instruction is same as DJNZ Rn, offset except that the content
direct = Address of RAM/SFR of the RAM/SFR is decremented and compared. The address of the
(RAM/SFR) ← (RAM/SFR) −1 RAM/SFR is directly specified in the instruction.
If (RAM/SFR) ≠ 0 then
(PC) ← (PC) + offset

94. NOP (PC) ← (PC) + 1 This instruction will not perform any operation, except that the PC is
incremented by one to point to the next instruction. Execution of NOP
will produce a delay of one machine cycle time and so, this instruction
can be used to create small delays in multiplies of machine cycle time.

5.8 BOO LEA N I N STRUC TI ONS

The boolean instructions operate on a particular bit of a data. This group includes instructions which clear, complement or move
a particular bit of bit-addressable RAM/SFR or carry flag. It also include jump instructions, which transfers the program control to a new
address, if a particular bit is set or cleared. The boolean instructions of the 8031/8051 are listed in Table-5.8 with a brief explanation about
each instruction.

TABLE - 5.8 : BOOLEAN INSTRUCTIONS

S.No. Instruction Symbolic representation Explanation

95. CLR C CF ← 0 Clear carry flag.

96. CLR bit bit = Address of particular bit The particular bit of RAM/SFR whose address is specified in the
of RAM/SFR instruction is cleared to zero.
(bit) ← 0

97. SETB C CF ← 1 The carry flag is set to one.

MICROPROCESSORS AND MICROCONTROLLERS
Table-5.8 continued …

S.No. Instruction Symbolic representation Explanation

98. SETB bit bit = Address of particular bit The particular bit of RAM/SFR whose address is specified
of RAM/SFR in the instruction is set to one.
(bit) ← 1

99. CPL C CF ← ~ CF The carry flag is complemented.

100. CPL bit bit = Address of particular bit of RAM/SFR The particular bit of RAM/SFR whose address is
(bit) ← ~ (bit) specified in the instruction is complemented.

101. ANL C,bit bit = Address of particular bit of RAM/SFR The particular bit of RAM/SFR is logically ANDed with the
CF ← CF & (bit) carry flag and the result is stored in the carry flag.
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051

102. ANL C,/bit bit = Address of particular bit of RAM/SFR The complement of the particular bit of RAM/SFR is
(bit) ← ~ (bit) logically ANDed with the carry flag and the result is stored
CF ← CF & (bit) in the carry flag.

103. ORL C,bit bit = Address of particular bit of RAM/SFR The particular bit of RAM/SFR is logically ORed with the
CF ← CF | (bit) carry flag and the result is stored in the carry flag.

104. ORL C,/bit bit = Address of particular bit of RAM/SFR The complement of the particular bit of RAM/SFR is
(bit) ← ~ (bit) logically ORed with the carry flag and the result is stored in
CF ← CF | (bit) the carry flag.

105. MOV C,bit bit = Address of particular bit of RAM/SFR The particular bit of RAM/SFR is moved to the carry flag. The
CF ← (bit) address of the bit is directly given in the instruction.

106. MOV bit,C bit = Address of particular bit of RAM/SFR The carry flag is moved to a particular bit of RAM/SFR whose
(bit) ← CF address is directly specified in the instruction.
5. 29
Table-5.8 continued …
5. 30
S.No. Instruction Symbolic representation Explanation
107. JC offset (PC) ← (PC) + 2 The content of the PC is incremented by two to point to the
If CF = 1 then, (PC) ← (PC) + offset next instruction. Then the carry flag is checked. If the carry flag
is one, then the offset given in the instruction is added to the
PC so that the program control is transferred to a new address.

108. JNC offset (PC) ← (PC) + 2 Same as JC offset, except that the branching will take place
If CF = 0 then, (PC) ← (PC) + offset if the carry flag is zero.

109. JB bit, offset bit = Address of particular bit of RAM/SFR The content of the PC is incremented by three to point to the
(PC) ← (PC) + 3 next instruction. The particular bit of RAM/SFR is tested. If
If (bit) = 1, then (PC) ← (PC) + offset the bit is one, then the offset given in the instruction is added
to PC so that the program control is transferred to a new
address.

110. JNB bit, offset bit = Address of particular bit of RAM/SFR The content of the PC is incremented by three to point to the
(PC) ← (PC) + 3 next instruction. The particular bit of RAM/SFR is tested. If the
If (bit) = 0, then (PC) ← (PC) + offset bit is zero, then the offset given in the instruction is added to the
PC so that the program control is transferred to a new address.

111. JBC bit, offset bit = Address of particular bit of RAM/SFR The content of the PC is incremented by three to point to the
(PC) ← (PC) + 3 next instruction. The particular bit of RAM/SFR is tested. If
If (bit) = 1, then bit ← 0 ; (PC) ← (PC) +offset the bit is one, then clear the bit and the offset given in the
instruction is added to the PC, so that the program control is
transferred to a new address.
MICROPROCESSORS AND MICROCONTROLLERS
C HAPTER 5 I NSTRUCTION S ET O F 8031/8051 5. 31

Symbols/Abbreviations Used in Instruction Set

Rn Register R7 to R0 of currently & Logical AND
selected register bank | Logical OR
direct 8-bit address of internal RAM/SFR ~ Complement/Logical NOT
@Ri Internal RAM addressed indirectly ^ Logical Exclusive-OR
through R0 or R1 CF Carry flag
@DPTR External data memory addressed Bn nth bit of register/memory
indirectly through DPTR Bn+1 (n + 1)th bit of register/memory
#data 8-bit immediate data/constant (A)3-0 Lower nibble of accumulator
#data16 16-bit immediate data/constant (A)7-4 Upper nibble of accumulator
addr11 11-bit address (PC)7-0 Lower byte of program counter
addr16 16-bit address (PC)15-8 Upper byte of program counter
offset 8-bit signed offset value in the (PC)10-0 Lower 11 bits of program counter
range −128 10 to + 127 10 (RAM)3-0 Lower nibble of RAM.
bit Address of bit-addressable
RAM/SFR

5.9 SHOR T QUESTIONS AND ANSWERS

5.1 What is state in an 8031/8051 microcontroller ?
The state is the basic time unit for discrete operation of the controller such as fetching an opcode,
executing an opcode, writing a data, etc. A machine cycle consists of six states and the timing of
each state is 2 oscillator clock periods.
5.2 How many machine cycles are needed to execute an instruction in an 8031/8051 controller ?
The 8031/8051 microcontroller executes an instruction in one to four machine cycles.
5.3 How can the time taken to execute an instruction be estimated in an 8031/8051 controller ?
The time taken to execute an instruction by an 8031/8051 controller is obtained by multiplying the
time to execute a machine cycle by the number of machine cycles of the instruction. The time to
execute a machine cycle is 12 clock periods.
1
∴ Time to execute an instruction = C × 12 × T = C × 12 ×
f
where, C = Number of machine cycles of an instruction.
T = Time period of crystal frequency in seconds.
f = Crystal frequency in Hz.
5.4 What is the size of 8031/8051 instructions ?
The size of 8031/8051 instructions is one to three bytes. The first byte is an opcode and the
subsequent bytes are the address or data.
5.5 List the various machine cycles of an 8031/8051 controller.
The various machine cycles of 8031/8051 microcontroller are:
(i) External program memory fetch cycle.
(ii) External data memory read cycle.
(iii) External data memory write cycle.
(iv) Port operation cycle.
5. 32 MICROPROCESSORS AND MICROCONTROLLERS

5.6 How does an 8051 microcontroller differentiate between external program memory access and
data memory access ?
With external program memory, the controller can perform only read operations but with external
data memory, the controller can perform both read and write operations. For reading program
memory, the controller asserts PSEN as low, for reading data memory the controller asserts RD as
low, and for writing data memory the controller asserts WR as low.
5.7 What are the addressing modes available in an 8051 controller ?
The addressing modes available in the 8051 microcontroller are:
� Immediate addressing � Register indirect addressing
� Direct addressing � Implied addressing
� Register addressing � Relative addressing

5.8 Explain register indirect addressing in an 8051.

In register indirect addressing, the instruction specifies the name of the register in which the address of the data is
available. The internal data RAM locations can be addressed indirectly through registers R1 and R0. The external RAM
can be addressed indirectly through the DPTR (Data pointer).
Example : MOV A,@R0 - The content of the RAM location addressed by the R0 is moved to theA-register.
5.9 Explain relative addressing in an 8051.
In relative addressing mode, the instruction specifies the address relative to theProgram Counter (PC). The instruction
will carry an offset whose range is –12810 to +12710. The offset is added to the PC to generate the 16-bit physical address.
Example : JC offset - If carry is one, then the program control jumps to an address obtained by adding the content of
the PC and the offset value in the instruction.
5.10 How can the 8051 instructions be classified ?
The 8051 instructions can be classified into the following five groups:
(i) Data transfer instructions
(ii) Arithmetic instructions
(iii) Logical instructions
(iv) Branching instructions
(v) Boolean instructions
5.11 List the instructions of 8051 that affect all the flags of 8051.
The 8051 instructions that affects all the flags are ADD, ADDC, and SUBB.
5.12 List the instructions of 8051 that affect the overflow flag in 8051.
The 8051 instructions that affect overflow flag are ADD, ADDC, DIV, MUL and SUBB.
5.13 List the instructions of 8051 that affect only the carry flag.
The 8051 instructions that affect only the carry flag are:
ANL C,bit CPL C RRC A
ANL C,/bit MOV C,bit RLC A
CJNE ORL C,bit SETB C
CLR C ORL C,/bit
5.14 List the instructions of 8051 that always clear the carry flag.
The instructions that always clear the carry flag are: CLR C, DIV and MUL.
5.15 What are the operations performed by the boolean variable instructions of an 8051 ?
The boolean variable instructions can clear or complement or move a particular bit of bit-addressable
RAM/SFR or carry flag. They can also transfer the program control to a new address if a particular
bit is set or cleared.