Abu Dhabi University

CEN 466 - Advanced Digital Design

Project Report
Digital Clock

Author: Supervisor:
Muhammad Obaidullah 1030313 Dr. Mohammed Assad Ghazal

Section 1

December 15, 2012

1 Introduction
Typically it is possible to write a single VHDL code for the whole design you require, but using
components as pre-programmed blocks to perform simple tasks is a intelligent and professional way
to solve a design problem. Take for example a BCD to seven segment Decoder. This Decoder take
a input of 4 bits which represents a number from 0-15 and converts it into a output which a seven
segment display can understand and display. When designing larger systems, you can just take
the output from your component and connect it to the input of this decoder and there you go,
You have just displayed what the output was from your component in a seven segment display. By
combining and embedding many such blocks of components, one can end up making sophisticated
systems to solve huge problems.

2 List of Equipment used

• Quartus II Web Edition.

• Altera Cyclone II board.

• Cyclone II Pin Map.

1
3 Project Design Set-up
The aim of the project was to use the basic components provided to us from blackboard and use
them to design a top level entity which contained and used these components. My design layout
for the project was as follows:-

2
 4 Procedure
• Open Quartus II and create a new project.

• Name the project to my liking but without spaces in the name.

• Download the VHDL code for Seven Segment Display Decoder, 4-bit comparator, 4-bit
counter, and Clock Divider from blackboard and include them in my project directory.

• Click on new and create a blank VHDL file.

• Name the new VHDL file to be the same as the project name. This is essential as this VHDL
file will be set as my top level entity.

• now write the following code into the VHDL file.

1 library ieee ;
use i e e e . s t d l o g i c 1 1 6 4 . a l l ;
3
e n t i t y FifteenSecondsTimer i s
5 port (

7
hour0 : out s t d l o g i c v e c t o r ( 6 downto 0 ) ;
9 hour1 : out s t d l o g i c v e c t o r ( 6 downto 0 ) ;
minute0 : out s t d l o g i c v e c t o r ( 6 downto 0 ) ;
11 minute1 : out s t d l o g i c v e c t o r ( 6 downto 0 ) ;
s e c o n d 0 : out s t d l o g i c v e c t o r ( 6 downto 0 ) ;
13 s e c o n d 1 : out s t d l o g i c v e c t o r ( 6 downto 0 ) ;
clk : in std logic
15 );
end F i f t e e n S e c o n d s T i m e r ;
17
a r c h i t e c t u r e FifteenSecondsTimer arch of FifteenSecondsTimer i s
19
component SevenSegmentDecoder i s
21 port (
output : out s t d l o g i c v e c t o r ( 6 downto 0 ) ;
23 input : in s t d l o g i c v e c t o r ( 3 downto 0 )

25 );
end component ;
27
component c l k d i v IS
29 PORT(
clock 50Mhz : IN STD LOGIC ;
31 clock 1MHz : OUT STD LOGIC ;
clock 100KHz : OUT STD LOGIC ;
33 clock 10KHz : OUT STD LOGIC ;
clock 1KHz : OUT STD LOGIC ;
35 clock 100Hz : OUT STD LOGIC ;
clock 10Hz : OUT STD LOGIC ;
37 clock 1Hz : OUT STD LOGIC) ;
END component ;
39
component c o u n t e r i s
41 port (

3
 clock : in std logic ;
43 clear : in std logic ;
count : in std logic ;
45 Q: out s t d l o g i c v e c t o r ( 3 downto 0 )
);
47 end component ;

49
component Comparator i s
51 port (
A: in s t d l o g i c v e c t o r ( 3 downto 0 ) ;
53 B: in s t d l o g i c v e c t o r ( 3 downto 0 ) ;
less : out s t d l o g i c ;
55 equal : out s t d l o g i c ;
g r e a t e r : out s t d l o g i c
57 );
end component ;
59

61
s i g n a l s e c 0 , s e c 1 , min0 , min1 , hr0 , hr1 : s t d l o g i c v e c t o r ( 3 downto 0 ) ;
63 signal reset0 , reset1 , reset2 , reset3 , reset4 , reset5 , myclocksignal : s t d l o g i c ;

65

67 begin

69
ClockDivider : c l k d i v p o r t map( clock 50Mhz=>c l k , c l o c k 1 H z=>m y c l o c k s i g n a l ) ;
71
−−−− FOR 1ST SECONDS DIGIT −−−−
73
s1 : counter p o r t map( c l o c k=>m y c l o c k s i g n a l , c l e a r=>r e s e t 0 , count = > ’1 ’ ,Q=>s e c 0 )
;
75 s 2 : SevenSegmentDecoder p o r t map( i n p u t=>s e c 0 , output=>s e c o n d 0 ) ;
s 3 : Comparator p o r t map(A=>s e c 0 , B=>” 1010 ” , e q u a l=>r e s e t 0 ) ;
77
−−−− FOR 2ND SECONDS DIGIT −−−−
79
s4 : counter p o r t map( c l o c k=>r e s e t 0 , c l e a r=>r e s e t 1 , count = > ’1 ’ ,Q=>s e c 1 ) ;
81 s 5 : SevenSegmentDecoder p o r t map( i n p u t=>s e c 1 , output=>s e c o n d 1 ) ;
s 6 : Comparator p o r t map(A=>s e c 1 , B=>” 0110 ” , e q u a l=>r e s e t 1 ) ;
83
−−−− FOR 1ST MINUTES DIGIT −−−−
85
m1 : c o u n t e r p o r t map( c l o c k=>r e s e t 1 , c l e a r=>r e s e t 2 , count = > ’1 ’ ,Q=>min0 ) ;
87 m2 : SevenSegmentDecoder p o r t map( i n p u t=>min0 , output=>minute0 ) ;
m3 : Comparator p o r t map(A=>min0 , B=>” 1010 ” , e q u a l=>r e s e t 2 ) ;
89
−−−− FOR 2ND MINUTES DIGIT −−−−
91
m4 : c o u n t e r p o r t map( c l o c k=>r e s e t 2 , c l e a r=>r e s e t 3 , count = > ’1 ’ ,Q=>min1 ) ;
93 m5 : SevenSegmentDecoder p o r t map( i n p u t=>min1 , output=>minute1 ) ;
m6 : Comparator p o r t map(A=>min1 , B=>” 0110 ” , e q u a l=>r e s e t 3 ) ;
95
−−−− FOR 1ST HOURS DIGIT −−−−
97
h1 : c o u n t e r p o r t map( c l o c k=>r e s e t 3 , c l e a r=>r e s e t 4 , count = > ’1 ’ ,Q=>hr0 ) ;
99 h2 : SevenSegmentDecoder p o r t map( i n p u t=>hr0 , output=>hour0 ) ;

4
 h3 : Comparator p o r t map(A=>hr0 , B=>” 1010 ” , e q u a l=>r e s e t 4 ) ;
101
−−−− FOR 2ND HOURS DIGIT −−−−
103
h4 : c o u n t e r p o r t map( c l o c k=>r e s e t 4 , c l e a r=>r e s e t 5 , count = > ’1 ’ ,Q=>hr1 ) ;
105 h5 : SevenSegmentDecoder p o r t map( i n p u t=>hr1 , output=>hour1 ) ;
h6 : Comparator p o r t map(A=>hr1 , B=>” 0010 ” , e q u a l=>r e s e t 5 ) ;
107

109

111

113 end F I F t e e n S e c o n d s T i m e r a r c h ;

5
5 Results and Discussions
At the end of the project, I uploaded the code onto the Altera board and got the following results:-

• Build was complete with some warnings but no errors.

• At first the segments were showing inverted outputs but I figured it out that I had planned
the pins in the reverse order.

• For testing purposes I used 100Hz or sometimes 10KHz clock output from the clock divider
to quickly reach hours so that I can test the hours working.

• The seven segment display of the Altera board uses inverted input. For example for lighting
up 1 on the segment display you have to give input to it ”1111001”

Figure 1: The clock is now showing 32 seconds past one minute

6
Figure 2: The left two seven segment displays are for seconds and the right ones are for the minutes

7
Figure 3: Initially I used the push button as the clock but it got tiring and was slow. So I used a
100Hz clock from the clock divider to just test out all the digits were working fine or not

8
Figure 4: The seven segment display showing the clock now at 02:00 minutes mark

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6 Conclusion
• This type of implementation is called the combinational implementation where I have used
combinational circuits to make a large entity.

• Statistically, Combinational implementations are more faster than the sequential implementa-
tions because sequential implementations use sequence and timing to execute the instructions
which is time consuming and depends heavily on the hardware’s CPU clock.

7 For more Information:

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