Lockup Elements - The Timing Perspective
Lockup Elements - The Timing Perspective
Lockup latch: A lockup latch can be inserted both in the launching and
capturing domain. The polarity of course will have to be taken care of based
on the physical feasibility to insert the latch in that domain.
Figure 1 above shows a hold critical positive skew path. While a physical
solution would be to insert buffers in the data path which would in turn
create issues in meeting timing across Process-Voltage-Temperature
variations, this can also be tackled architecturally in following ways by
inserting elements in launching/capturing domains.
Figure 3: negative lockup latch insertion in launch domain
Figure 2 and 3 show how lock up insertion relaxes the critical hold timing. It
must be noted that the lockup element must be balanced with the flop of the
domain in which it is placed.
Figure 5 above differs from Fig 4 in the sense that the final capture domain
flop is negative edge triggered here. While this might not be a typical hold-
driven requirement since the hold check was already half cycle before the
lockup was introduced, this helps illustrate a unique timing scenario. Note
that here the critical setup timing from the lockup latch to the negative flop
is to be met here since scan enable is not yet down to zero. By extension,
the setup check to the positive level sensitive latch is also to be met.
Let us now compare the Fig 5 scenario with the lockup element replaced by a
register.
Figure 7 and 8 illustrate that while the setup check to the latch is not
required to be met to a negative level sensitive lockup latch (which remains
transparent for a long time from the second capture pulse to the first shift
edge), the requirement is present in a negative level triggered lockup
register.
Below table captures atspeed setup timing requirement to and from the latch
for all possible combinations:
Normally, positive register is not followed by a negative register in a scan
chain because both the sequential elements will be unintentionally crossed in
a single shift pulse. However, wherever present, the above FALSE paths can
be marked as exceptions (for setup timing only) while meeting atspeed
timing to and from the lockup elements which enables smoother and
accurate timing closure of the atspeed test modes.