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DLD Lab Report #9

This lab report describes designing and implementing a BCD to 7-segment decoder on an FPGA board. The objectives are to design and test a BCD to 7-segment decoder using a CD4511 IC with a 7-segment display and implement the decoder on an FPGA board. The report explains the background theory of BCD encoding and 7-segment displays. It then details the tasks of testing the IC implementation and designing the decoder with Verilog code using case statements, and simulating, synthesizing and testing the FPGA implementation.

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846 views

DLD Lab Report #9

This lab report describes designing and implementing a BCD to 7-segment decoder on an FPGA board. The objectives are to design and test a BCD to 7-segment decoder using a CD4511 IC with a 7-segment display and implement the decoder on an FPGA board. The report explains the background theory of BCD encoding and 7-segment displays. It then details the tasks of testing the IC implementation and designing the decoder with Verilog code using case statements, and simulating, synthesizing and testing the FPGA implementation.

Uploaded by

waleed
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DIGITAL LOGIC DESIGN

LAB REPORT

Name: Muhammad Mamoon Akber


Registration No.FA17-BEE-084
Section: BEE-2B
LAB # 7
Dated: 16 April, 2018
Submitted to: Maam Asma Ramay
LAB #09: Design and Implementation of BCD to
7-Segment decoder on FPGA

Objectives:
In this lab, we design and implement BCD to 7-Segment decoder. Moreover, we
learn how to use the 7-segment display of Nexys2 FPGA board.

Pre-Lab:
Background Theory:

Binary to BCD Decoder:

In digital, binary-coded decimal (BCD) is a class of binary encodings of decimal


numbers where each decimal digit is represented by a fixed number of bits, usually
four. Table 9.1 gives the four-bit code for one decimal digit. A number with k decimal
digits will require 4k bits in BCD.

Decimal Value BCD


0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
Table #1: Binary coded decimal (BCD)

BCD to 7-Segment Decoder:

BCD to 7-segment decoder decodes the BCD value on 7-Segment display.

7-Segment Display:

A seven-segment display (SSD) is a form of the electronic display device for displaying
decimal numerals. The seven elements of the display can be selected in different
combinations to represent the decimal numerals. Often the seven segments are
arranged in an oblique (slanted) arrangement, which aids readability. Seven-segment
displays may use a light-emitting diode (LED) or a liquid crystal display (LCD), for
each segment, or other light-generating or controlling techniques. There are two types
of simple LED package 7-Segment display:

1. Common Anode
2. Common Cathode

7-Segment (Common Anode) Displays on Nexys2 board:

Nexys2 board contains a four-digit common anode seven-segment LED display.


Each of the four digits is composed of seven segments arranged in a pattern (as
shown in Figure 9.1), with an LED embedded in each segment. Segment LEDs can
be individually illuminated, so any one of 128 patterns can be displayed on a digit
by illuminating certain LED segments and leaving the others dark. The anodes of
the seven LEDs forming each digit are tied together into one “common anode”
circuit node, but the LED cathodes remain separate. The common anode signals
are available as four “digit enable” input signals to the 4-digit display. The
cathodes of similar segments on all four displays are connected into seven circuit
nodes labeled CA through CG (so, for example, the four “D” cathodes from the four
digits are grouped together into a single circuit node called “CD”). These seven
cathode signals are available as inputs to the 4-digit display. This signal
connection scheme creates a multiplexed display, where the cathode signals are
common to all digits, but they can only illuminate the segments of the digit whose
corresponding anode signal is asserted.

Figure #1 Nexys2 Board 7-Segment Displays


Figure #1 Nexys2 Board I/O devices and circuits

CASE statement in Verilog:

case (switching variable)

Label Value1: statement(s);

Label Value2: statement(s);

Label Value n: statement(s);

default: statement(s);

endcase

Example (4-to-1 MUX using CASE statement)


module mux_4_1( Y, I, S );

output reg Y;

input [3:0]I;

input [1:0]S;

always @ ( I or S)

begin
case ( S) //As MUX output is selected by selection line, here ‘S’, so
it is a switching variable

2’b00: Y = I[0]; // when S=00 then I0 is selected for output

2’b01: Y = I[1]; // when S=01 then I1 is selected for output

2’b10: Y = I[2]; // when S=10 then I2 is selected for output

2’b11: Y = I[3]; // when S=11 then I3 is selected for output

default: Y = 1’b0; // when S=zz or xx then output is 0 (By default)

endcase

end

endmodule

In-Lab Task 1: Test the functionality of a BCD to 7-Segment decoder IC


(CD4511) with common cathode 7-Segment display:

Procedure
Make a circuitry as shown. Connect all the inputs and with the switches. Observe the
behaviour of a BCD to 7-Segment decoder on 7-Segment by choosing different BCD
values.

Figure #3: BCD to 7-Segment decoder (CD4511) with common cathode circuitry
Figure #4: BCD to 7-Segment decoder (CD4511) with common cathode circuitry
made on bread board

In-Lab Task 2: Design and implementation of a BCD to 7-Segment


decoder on FPGA (Nexys2):

Figure #2: BCD to 7-Segment decoder module


Procedure: First, make a truth table for BCD to 7-Segment decoder which has 4-inputs
(BCD) and 8-outputs (A to G and DP) of the 7-Segment display. Using Behavioral model, write
a Verilog description of BCD to 7-Segment decoder using Case statements. Implement it on
FPGA (Only one 7-Segment should be on). Remember 7-Segment displays on Nexys2 board are
common anode with driver circuitry.
HINT: Activate only one segment anode by assign keyword. You have four 7-Segment anodes
(AN3, AN2, AN1, AN0) on Nexys2 board.
Truth table for BCD to 7-Segment decoder

Inputs Outputs
A B C D a b c d e f g D He
P x
0 0 0 0 0 0 0 0 0 0 1 0 02
0 0 0 1 1 0 0 1 1 1 1 0 9e
0 0 1 0 0 0 1 0 0 1 0 0 24
0 0 1 1 0 0 0 0 1 1 0 0 0c
0 1 0 0 1 0 0 1 1 0 0 0 98
0 1 0 1 0 1 0 0 1 0 0 0 48
0 1 1 0 0 1 0 0 0 0 0 0 c0
0 1 1 1 0 0 0 1 1 1 1 0 1e
1 0 0 0 0 0 0 0 0 0 0 0 00
1 0 0 1 0 0 0 1 1 0 0 0 18

Figure #6: Verilog code of BCD to 7-segment display


Figure #3: Verilog code for FPGA of BCD to 7-segment display

Post-Lab Task:
Make a stimulus for BCD to 7-Segment decoder (In-Lab Task 2).
Report synthesize key parameters such as resource utilization and critical path delay.

Data Flow Model:


Simulation:

Wave Form:
Device Utilization Summary:

Net Delay:

Critical Analysis:
7-segment LED or LCD type displays, provide a very convenient way of displaying information or digital
data in the form of numbers, letters or even alpha-numerical characters. So, In this lab we are using it
for the display of 7 segment decoder for BCD. The seven elements of the display can be selected in
different combinations to represent the decimal numerals. Often the seven segments are arranged in an
oblique (slanted) arrangement, which aids readability. Seven-segment displays may use a light-emitting
diode (LED) or a liquid crystal display (LCD), for each segment, or other light-generating or controlling
techniques. There are two types of simple LED package 7-Segment display. We can use common anode
and common cathode depending upon device.

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