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FPGA Implementation of AES Encryption and Decryption

The document discusses an FPGA implementation of the Advanced Encryption Standard (AES) algorithm for both encryption and decryption. It presents the AES algorithm and describes implementing it using Very High Speed Integrated Circuit Hardware Description Language (VHDL) on a Xilinx FPGA. The AES encrypter and decrypter were integrated into a single architecture to minimize hardware usage. This combined architecture allows both encryption and decryption to be performed with high data rates while reducing resource requirements, making it suitable for hardware-constrained applications like smart cards, PDAs, and mobile phones.

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62 views

FPGA Implementation of AES Encryption and Decryption

The document discusses an FPGA implementation of the Advanced Encryption Standard (AES) algorithm for both encryption and decryption. It presents the AES algorithm and describes implementing it using Very High Speed Integrated Circuit Hardware Description Language (VHDL) on a Xilinx FPGA. The AES encrypter and decrypter were integrated into a single architecture to minimize hardware usage. This combined architecture allows both encryption and decryption to be performed with high data rates while reducing resource requirements, making it suitable for hardware-constrained applications like smart cards, PDAs, and mobile phones.

Uploaded by

vijayhall
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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FPGA implementation of AES encryption

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Deshpande, A.M.;   Deshpande, M.S.;   Kayatanavar, D.N.;  


+Deshpande, A.M

Dept. of Electron. & Telecommun. Eng., SRES Coll. of Eng., Kopargaon, India 

This paper appears in: Control, Automation, Communication and Energy Conservation, 2009.
INCACEC 2009. 2009 International Conference on
Issue Date: 4-6 June 2009
On page(s): 1 - 6
Location: Perundurai, Tamilnadu
Print ISBN: 978-1-4244-4789-3
References Cited: 8
INSPEC Accession Number: 10835663
Date of Current Version: 18 August 2009

Abstract
Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an
approved cryptographic algorithm that can be used to protect electronic data. The AES can be
programmed in software or built with pure hardware. However Field Programmable Gate Arrays
(FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm
with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description
language (VHDL). ModelSim SE PLUS 5.7g software is used for simulation and optimization of
the synthesizable VHDL code. Synthesizing and implementation (i.e. Translate, Map and Place
and Route) of the code is carried out on Xilinx - Project Navigator, ISE 8.2i suite. All the
transformations of both Encryption and Decryption are simulated using an iterative design
approach in order to minimize the hardware consumption. Xilinx XC3S400 device of Spartan
Family is used for hardware evaluation. This paper proposes a method to integrate the AES
encrypter and the AES decrypter. This method can make it a very low-complexity architecture,
especially in saving the hardware resource in implementing the AES (Inv) Sub Bytes module and
(Inv) Mix columns module etc. Most designed modules can be used for both AES encryption and
decryption. Besides, the architecture can still deliver a high data rate in both
encryption/decryption operations. The proposed architecture is suited for hardware-critical
applications, such as smart card, PDA, and mobile phone, etc.

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