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Chapter 11 Datapath Subsystems: Enhanced

This document discusses various topics related to sequential and datapath circuits including state retention registers, level-converter flip-flops, sequencing dynamic circuits, synchronizers, wave pipelining, and addition/subtraction circuits. Specific sections cover state retention registers, level-converter flip-flops, two-phase timing, sequencing dynamic circuits, synchronizers, wave pipelining, case studies of Pentium 4 and Itanium 2 sequencing, and addition/subtraction, one/zero detectors, comparators, counters, logical operations, and coding.

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Carlos Saavedra
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50 views1 page

Chapter 11 Datapath Subsystems: Enhanced

This document discusses various topics related to sequential and datapath circuits including state retention registers, level-converter flip-flops, sequencing dynamic circuits, synchronizers, wave pipelining, and addition/subtraction circuits. Specific sections cover state retention registers, level-converter flip-flops, two-phase timing, sequencing dynamic circuits, synchronizers, wave pipelining, case studies of Pentium 4 and Itanium 2 sequencing, and addition/subtraction, one/zero detectors, comparators, counters, logical operations, and coding.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Contents xv

10.4.3 State Retention Registers 408


10.4.4 Level-Converter Flip-Flops 408
10.4.5 Design Margin and Adaptive Sequential Elements 409
WEB
ENHANCED 10.4.6 Two-Phase Timing Types 411
WEB
ENHANCED 10.5 Sequencing Dynamic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
10.6 Synchronizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
10.6.1 Metastability 412
10.6.2 A Simple Synchronizer 415
10.6.3 Communicating Between Asynchronous Clock Domains 416
10.6.4 Common Synchronizer Mistakes 417
10.6.5 Arbiters 419
10.6.6 Degrees of Synchrony 419
10.7 Wave Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
10.8 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
WEB
ENHANCED 10.9 Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies . . . . . 423
Summary 423
Exercises 425

Chapter 11 Datapath Subsystems


11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
11.2 Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
11.2.1 Single-Bit Addition 430
11.2.2 Carry-Propagate Addition 434
11.2.3 Subtraction 458
11.2.4 Multiple-Input Addition 458
11.2.5 Flagged Prefix Adders 459
11.3 One/Zero Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
11.4 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
11.4.1 Magnitude Comparator 462
11.4.2 Equality Comparator 462
11.4.3 K = A + B Comparator 463
11.5 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
11.5.1 Binary Counters 464
11.5.2 Fast Binary Counters 465
11.5.3 Ring and Johnson Counters 466
11.5.4 Linear-Feedback Shift Registers 466
11.6 Boolean Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
11.7 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
11.7.1 Parity 468
11.7.2 Error-Correcting Codes 468
11.7.3 Gray Codes 470
11.7.4 XOR/XNOR Circuit Forms 471

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