Compal La-8611p r0.1 Schematics
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miloshCompal La-8611p r0.1 Schematics
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miloshA B C D E
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Compal Confidential
2 2
QAWGH Schematics Document
AMD APU Trinity FS1r2 + FCH Hudson-M3 + GPU Seymourr XT
2011-10-07
3
REV:0.1 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 1 of 51
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ZZZ QAWGH
Compal confidential
File Name : QAWGH LA8611P LS7986P CardReader/B
LS7982P USB/B
DA_PCB
DA80000S600
LS7983P PWR/B
AMD Seymour XT LS8612P LED/B
LS7985P ODD/B
VRAM PCIE x 16 Gen2 LS8617P Cap Sensor/B
1 1
64M16/128M16 Memory BUS(DDRIII)
DDR3 x 4 AMD FS1r2 APU Dual Channel
page 17 ~ 23
1.5V DDRIII 1866 204pin DDRIII-SO-DIMM X2
DP Port0 Trinity BANK 0, 1, 2 page 10,11
LVDS
translator
uPGA 722 pin
RTDS2132S HDMI Conn. DP Port2 35mm x 35mm
page 24 page 26
DP Port1 page 5,~9
4 * x1 PCI-E 2.0 x4 UMI Gen. 1
LVDS Conn. 2.5GT/s per lane
page 25 GPP1 GPP0 2Channel Speaker
page 30
LAN
AR8161/8162
2 AZALIA Audio Codec Internal MIC 2
page 28~29 page 30
Hudson M3 CX20671-21Z
page 30
PCI Express USB(WiMAX) uFCBGA-656 Audio Jacks
CRT Conn. FCH CRT (VGA DAC)
Mini Card Slot 1 page 27 24.5mm x 24.5mm Sub-board
4*USB3.0,10*USB2.0
WLAN/WiMAX page 32 4 * x1 PCI-E 2.0
CMOS Camera page 25
page 12~16 6*SATA serial
BlueTooth Conn page 31
USB Port 3.0 x2(Left) page 37,38
LPC Bus
SPI ROM USB Port 2.0 x 1 (Right) Sub-board
page 13
RTS5178
3
EC Card Reader 2 in 1 Conn. 3
Cap Sensor USB 2.0 x 1 Sub-board SD/SDXC/MMC
Sub-board ENE KB930/ KB9012
page 34
Touch Pad Int. KBD
page 35 page 35 SATA0 SATA 3.0 HDD Conn.
page 31
SATA1 SATA ODD Conn.
page 31
Thermal Sensor
EMC1403
4
page 32 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 2 of 51
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Voltage Rails
Power Plane Description S1 S3 S5 FCH Hudson-M2/3 Comal FCH Hudson-M2/3 FCH Hudson-M2/3
VIN Adapter power supply (19V) N/A N/A N/A
SATA Port List PCIE Port List USB Port List USB OC PIN
B+ AC or battery power rail for power circuit. N/A N/A N/A SATA0 NC PCIE0 LAN USB1.1 USB_OC0# USB3.0 (LP1, LP2)
+APU_CORE Core voltage for APU ON OFF OFF
SATA1 HDD PCIE1 WLAN Port0 NC USB_OC1# USB2.0 (RP1)
APU
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF
1 1
+1.5V 1.5V power rail for APU VDDIO and DDR ON ON OFF SATA2 ODD PCIE2 NC Port1 NC USB_OC2# USB2.0 (RP2)
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF
+1.2VS 1.2V (VDDR, VDDP) switched power rail for APU ON OFF OFF
SATA3 NC PCIE3 NC USB2.0 USB_OC3# NC
+2.5VS 2.5V for APU VDDA ON OFF OFF SATA4 NC PCIE0 NC Port0 Right USB1 USB_OC4# NC
+1.1VALW 1.1V switched power rail for FCH ON ON ON*
SATA5 NC PCIE1 NC Port1 Right USB2 USB_OC5# NC
FCH
+1.1VS 1.1V switched power rail for FCH ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF PCIE2 NC Port2 Mini PCIE USB_OC6# NC
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF
+1.5VGS 1.5V switched power rail ON OFF OFF
PCIE3 NC Port3 USB Camera USB_OC7# NC
+1.8VGS 1.8V switched power rail ON OFF OFF Port4 BT
+1.0VGS 1.0V switched power rail for VGA ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
Port5 Card Reader
+3V_LAN 3.3V power rail for LAN ON ON ON* Port6 NC
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
Port7 NC
+5VS 5V switched power rail ON OFF OFF Port8 NC
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
Port9 NC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Port10 USB3.0 LP1
Port11 USB3.0 LP2
Port12 NC
EC SM Bus1 address EC SM Bus2 address BOM Structure Port13 NC
Device Address HEX Device Address HEX UMA@ : UMA only
Smart Battery 0001-011xb 15H EMC1403(VGA, DDR,WLAN) 1001-101xb 9AH PX@ : DIS muxluss
SB-TSI (default) 1001-100xb 98H CMOS@ : USB camera
VGA Thermal 1000-001xb 82H HDMI@ : HDMI function
Cap Sensor 1000-0000b 80H nonHDMI@ : w/o HDMI function
RTDS2132S-E 1010-1000b A8H BT@ : BT function
ME@ : ME components
X76@ : VRAM
3 3
45@ : 45 Level
SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
PX4@ : PX4
PX5@ : PX5
Device Address HEX 8162@ : 10/100 LAN
GIGA@ : giga LAN
14@ : G 14"
15@ : G 15"
BBH@ : Best Buy high-end
nonBBH@ : non Best Buy high-end
SM Bus Controller 1 (FCH_SMB0)
AN@ : Apple & Nokia combo
A@ : Apple only
Device Address HEX
DDR DIMM1 (FCH_SMB0) 1001-000xb 90H
DDR DIMM2 (FCH_SMB0) 1001-001xb 92H
WLAN (FCH_SMB0)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 3 of 51
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5 4 3 2 1
Without BACO option :
Power-Up/Down Sequence PE_GPIO0 (PXS_RST#) : Low ‐> Reset dGPU ; High ‐>Normal operation
PE_GPIO1 (PXS_PWREN) : Low ‐> dGPU Power OFF ; High ‐> dGPU Power ON
"Seymour" has the following requirements with regards to power-supply sequencing
to avoid damaging the ASIC: BACO option :
‧ All the ASIC supplies, except for VDDR3, must fully reach their respective PE_GPIO0 (PXS_RST#) : High ‐>Normal operation (dGPU is not reset on BACO mode)
PE_GPIO1 (PXS_PWREN) : Low ‐> dGPU Power OFF ; High ‐> dGPU Power ON (always High)
nominal voltages within 20 ms of the start of the ramp-up sequence, though a
shorter ramp-up duration is preferred. There is no timing requirement on the dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
D ramp up of VDDR3 relative to other power rails. PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA D
‧ The external pull-up resistors on the DDC/AUX signals (if applicable) should DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
ramp up before or after both VDDC and VDD_CT have ramped up. DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
‧ VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC DPLL_PVDD, MPV18, and SPV18
should reach 90% before VDD_CT starts to ramp up (or vice versa). For BACO DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 775mA
enabled designs, VDDC must ramp up before VDD_CT at system power up. SPV10
‧ For power down, reversing the ramp-up sequence is recommended
PCIE_VDDC 1.0V OFF ON 1.1A
VDDR3 3.3V OFF ON 60mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
BACO mode) VDDC Same as
PCIE_VDDC
VDDR1 1.5V OFF OFF 1.2A
VDDR3(3.3VGS) VDDC/VDDCI TBD OFF OFF 28
PCIE_VDDC(1.0V)
PX4.0
C
VDDR1(1.5VGS) C
PE_GPIO0(PXS_RST#) PE_EN BACO Switch
iGPU dGPU
VDDC/VDDCI(1.12V) BIF_VDDC
PE_GPIO1(PXS_PWREN)
VDD_CT(1.8V) PX_mode
+3.3VALW MOS
+3.3VGS
PERSTb 1
B+ Regulator
+1.5VGS
REFCLK +1.5V +1.0VGS
LDO
2 3
Straps Reset
+B Regulator
+VGA_CORE
+5VLAW +1.8VGS
Regulator
5 4
Straps Valid
PWRGOOD
B B
Global ASIC Reset
PX5.0
T4+16clock
PE_GPIO0(PXS_RST#) +VGA_CORE
iGPU dGPU
BIF_VDDC
PE_GPIO1(PXS_PWREN)
+3.3VALW MOS
+3.3VGS Short PX_MODE and PX_PWREN
1
B+ Regulator
+1.5VGS
+1.5V +1.0VGS
LDO
2 3
A
+B Regulator
+VGA_CORE A
+5VLAW +1.8VGS
Regulator
5 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
dGPU Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 4 of 51
5 4 3 2 1
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<17> PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_P[0..15] <17>
<17> PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N[0..15] <17>
JCPU1A
PCI EXPRESS
PCIE_CRX_GTX_P0 AB8 AB2 PCIE_CTX_C_GRX_P0 C1 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 P_GFX_RXP0 P_GFX_TXP0 PCIE_CTX_C_GRX_N0 C2 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_N0
AB7 P_GFX_RXN0 P_GFX_TXN0 AB1 1 2
PCIE_CRX_GTX_P1 AA9 AA3 PCIE_CTX_C_GRX_P1 C3 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 P_GFX_RXP1 P_GFX_TXP1 PCIE_CTX_C_GRX_N1 C4 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_N1
AA8 P_GFX_RXN1 P_GFX_TXN1 AA2 1 2
PCIE_CRX_GTX_P2 AA5 Y5 PCIE_CTX_C_GRX_P2 C5 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P2
PCIE_CRX_GTX_N2 P_GFX_RXP2 P_GFX_TXP2 PCIE_CTX_C_GRX_N2 C6 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_N2
AA6 P_GFX_RXN2 P_GFX_TXN2 Y4 1 2
1 PCIE_CRX_GTX_P3 PCIE_CTX_C_GRX_P3 C7 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P3 1
Y8 P_GFX_RXP3 P_GFX_TXP3 Y2 1 2
PCIE_CRX_GTX_N3 Y7 Y1 PCIE_CTX_C_GRX_N3 C8 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N3
PCIE_CRX_GTX_P4 P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_P4 C9 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P4
W9 P_GFX_RXP4 P_GFX_TXP4 W3 1 2
PCIE_CRX_GTX_N4 W8 W2 PCIE_CTX_C_GRX_N4 C10 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 P_GFX_RXN4 P_GFX_TXN4 PCIE_CTX_C_GRX_P5 C11 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P5
W5 P_GFX_RXP5 P_GFX_TXP5 V5 1 2
PCIE_CRX_GTX_N5 W6 V4 PCIE_CTX_C_GRX_N5 C12 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N5
PCIE_CRX_GTX_P6 P_GFX_RXN5 P_GFX_TXN5 PCIE_CTX_C_GRX_P6 C13 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P6
V8 P_GFX_RXP6 P_GFX_TXP6 V2 1 2
PCIE_CRX_GTX_N6 PCIE_CTX_C_GRX_N6 PCIE_CTX_GRX_N6
GRAPHICS
V7 V1 C14 PX@ 1 2 0.1U_0402_16V7K
PCIE_CRX_GTX_P7 P_GFX_RXN6 P_GFX_TXN6 PCIE_CTX_C_GRX_P7 C15 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P7
U9 P_GFX_RXP7 P_GFX_TXP7 U3 1 2
PCIE_CRX_GTX_N7 U8 U2 PCIE_CTX_C_GRX_N7 C16 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N7
PCIE_CRX_GTX_P8 P_GFX_RXN7 P_GFX_TXN7 PCIE_CTX_C_GRX_P8 C17 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P8
U5 P_GFX_RXP8 P_GFX_TXP8 T5 1 2
PCIE_CRX_GTX_N8 U6 T4 PCIE_CTX_C_GRX_N8 C18 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N8
PCIE_CRX_GTX_P9 P_GFX_RXN8 P_GFX_TXN8 PCIE_CTX_C_GRX_P9 C19 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P9
T8 P_GFX_RXP9 P_GFX_TXP9 T2 1 2
PCIE_CRX_GTX_N9 T7 T1 PCIE_CTX_C_GRX_N9 C20 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N9
PCIE_CRX_GTX_P10 P_GFX_RXN9 P_GFX_TXN9 PCIE_CTX_C_GRX_P10 C21 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P10
R9 P_GFX_RXP10 P_GFX_TXP10 R3 1 2
PCIE_CRX_GTX_N10 R8 R2 PCIE_CTX_C_GRX_N10 C22 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N10
PCIE_CRX_GTX_P11 P_GFX_RXN10 P_GFX_TXN10 PCIE_CTX_C_GRX_P11 C23 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P11
R5 P_GFX_RXP11 P_GFX_TXP11 P5 1 2
PCIE_CRX_GTX_N11 R6 P4 PCIE_CTX_C_GRX_N11 C24 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N11
PCIE_CRX_GTX_P12 P_GFX_RXN11 P_GFX_TXN11 PCIE_CTX_C_GRX_P12 C25 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P12
P8 P_GFX_RXP12 P_GFX_TXP12 P2 1 2
PCIE_CRX_GTX_N12 P7 P1 PCIE_CTX_C_GRX_N12 C26 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N12
PCIE_CRX_GTX_P13 P_GFX_RXN12 P_GFX_TXN12 PCIE_CTX_C_GRX_P13 C27 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P13
N9 P_GFX_RXP13 P_GFX_TXP13 N3 1 2
PCIE_CRX_GTX_N13 N8 N2 PCIE_CTX_C_GRX_N13 C28 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N13
PCIE_CRX_GTX_P14 P_GFX_RXN13 P_GFX_TXN13 PCIE_CTX_C_GRX_P14 C29 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P14
N5 P_GFX_RXP14 P_GFX_TXP14 M5 1 2
PCIE_CRX_GTX_N14 N6 M4 PCIE_CTX_C_GRX_N14 C30 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N14
PCIE_CRX_GTX_P15 P_GFX_RXN14 P_GFX_TXN14 PCIE_CTX_C_GRX_P15 C31 PX@ 0.1U_0402_16V7K PCIE_CTX_GRX_P15
M8 P_GFX_RXP15 P_GFX_TXP15 M2 1 2
PCIE_CRX_GTX_N15 M7 M1 PCIE_CTX_C_GRX_N15 C32 PX@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N15
P_GFX_RXN15 P_GFX_TXN15
AE5 AD5 PCIE_CTX_C_DRX_P0 C33 1 2 0.1U_0402_16V7K
<28> PCIE_CRX_DTX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_CTX_DRX_P0 <28>
LAN AE6 AD4 PCIE_CTX_C_DRX_N0 C34 1 2 0.1U_0402_16V7K
<28> PCIE_CRX_DTX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_CTX_DRX_N0 <28>
AD8 AD2 PCIE_CTX_C_DRX_P1 C35 1 2 0.1U_0402_16V7K
<32> PCIE_CRX_DTX_P1 P_GPP_RXP1 P_GPP_TXP1 PCIE_CTX_DRX_P1 <32>
WLAN AD7 AD1 PCIE_CTX_C_DRX_N1 C36 1 2 0.1U_0402_16V7K
<32> PCIE_CRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_CTX_DRX_N1 <32>
AC9 P_GPP_RXP2 P_GPP_TXP2 AC3
GPP
2 2
AC8 P_GPP_RXN2 P_GPP_TXN2 AC2
AC5 P_GPP_RXP3 P_GPP_TXP3 AB5
AC6 P_GPP_RXN3 P_GPP_TXN3 AB4
AG8 AG2 UMI_TXP0_C C37 1 2 0.1U_0402_16V7K
<12> UMI_RXP0 P_UMI_RXP0 P_UMI_TXP0 UMI_TXP0 <12>
AG9 AG3 UMI_TXN0_C C38 1 2 0.1U_0402_16V7K
<12> UMI_RXN0 P_UMI_RXN0 P_UMI_TXN0 UMI_TXN0 <12>
AG6 AF4 UMI_TXP1_C C39 1 2 0.1U_0402_16V7K
<12> UMI_RXP1 P_UMI_RXP1 P_UMI_TXP1 UMI_TXP1 <12>
AG5 AF5 UMI_TXN1_C C40 1 2 0.1U_0402_16V7K
<12> UMI_RXN1 P_UMI_RXN1 P_UMI_TXN1 UMI_TXN1 <12>
AF7 AF1 UMI_TXP2_C C41 1 2 0.1U_0402_16V7K
<12> UMI_RXP2 P_UMI_RXP2 P_UMI_TXP2 UMI_TXP2 <12>
AF8 AF2 UMI_TXN2_C C42 1 2 0.1U_0402_16V7K
<12> UMI_RXN2 P_UMI_RXN2 P_UMI_TXN2 UMI_TXN2 <12>
AE8 AE2 UMI_TXP3_C C43 1 2 0.1U_0402_16V7K
<12> UMI_RXP3 UMI_TXP3 <12>
UMI
P_UMI_RXP3 P_UMI_TXP3 UMI_TXN3_C C44 0.1U_0402_16V7K
<12> UMI_RXN3 AE9 P_UMI_RXN3 P_UMI_TXN3 AE3 1 2 UMI_TXN3 <12>
+1.2VS 1 2 P_ZVDDP AG11 P_ZVDDP P_ZVSS AH11 P_ZVSS 1 2
R1 196_0402_1% R2 196_0402_1%
ME@ LOTES_ACA-ZIF-109-P12-A_FS1R2
3 3
Power Sequence of APU
+1.5V
+2.5VS Group A
+1.5VS
+APU_CORE
Group B
4 +APU_CORE_NB 4
+1.2VS
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FS1r2 PCIE/UMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 5 of 51
A B C D E
A B C D E
1 1
JCPU1B JCPU1C
MEMORY CHANNEL A MEMORY CHANNEL B
<10> DDRA_SMA[15..0] DDRA_SDQ[63..0] <10> <11> DDRB_SMA[15..0] DDRB_SDQ[63..0] <11>
DDRA_SMA0 U20 E13 DDRA_SDQ0 DDRB_SMA0 T27 A14 DDRB_SDQ0
DDRA_SMA1 MA_ADD0 MA_DATA0 DDRA_SDQ1 DDRB_SMA1 MB_ADD0 MB_DATA0 DDRB_SDQ1
R20 MA_ADD1 MA_DATA1 J13 P24 MB_ADD1 MB_DATA1 B14
DDRA_SMA2 R21 H15 DDRA_SDQ2 DDRB_SMA2 P25 D16 DDRB_SDQ2
DDRA_SMA3 MA_ADD2 MA_DATA2 DDRA_SDQ3 DDRB_SMA3 MB_ADD2 MB_DATA2 DDRB_SDQ3
P22 MA_ADD3 MA_DATA3 J15 N27 MB_ADD3 MB_DATA3 E16
DDRA_SMA4 P21 H13 DDRA_SDQ4 DDRB_SMA4 N26 B13 DDRB_SDQ4
DDRA_SMA5 MA_ADD4 MA_DATA4 DDRA_SDQ5 DDRB_SMA5 MB_ADD4 MB_DATA4 DDRB_SDQ5
N24 MA_ADD5 MA_DATA5 F13 M28 MB_ADD5 MB_DATA5 C13
DDRA_SMA6 N23 F15 DDRA_SDQ6 DDRB_SMA6 M27 B16 DDRB_SDQ6
DDRA_SMA7 MA_ADD6 MA_DATA6 DDRA_SDQ7 DDRB_SMA7 MB_ADD6 MB_DATA6 DDRB_SDQ7
N20 MA_ADD7 MA_DATA7 E15 M24 MB_ADD7 MB_DATA7 A16
DDRA_SMA8 N21 DDRB_SMA8 M25
DDRA_SMA9 MA_ADD8 DDRA_SDQ8 DDRB_SMA9 MB_ADD8 DDRB_SDQ8
M21 MA_ADD9 MA_DATA8 H17 L26 MB_ADD9 MB_DATA8 C17
DDRA_SMA10 U23 F17 DDRA_SDQ9 DDRB_SMA10 U26 B18 DDRB_SDQ9
DDRA_SMA11 MA_ADD10 MA_DATA9 DDRA_SDQ10 DDRB_SMA11 MB_ADD10 MB_DATA9 DDRB_SDQ10
M22 MA_ADD11 MA_DATA10 E19 L27 MB_ADD11 MB_DATA10 B20
DDRA_SMA12 L24 J19 DDRA_SDQ11 DDRB_SMA12 K27 A20 DDRB_SDQ11
DDRA_SMA13 MA_ADD12 MA_DATA11 DDRA_SDQ12 DDRB_SMA13 MB_ADD12 MB_DATA11 DDRB_SDQ12
AA25 MA_ADD13 MA_DATA12 G16 W26 MB_ADD13 MB_DATA12 E17
DDRA_SMA14 L21 H16 DDRA_SDQ13 DDRB_SMA14 K25 B17 DDRB_SDQ13
DDRA_SMA15 MA_ADD14 MA_DATA13 DDRA_SDQ14 DDRB_SMA15 MB_ADD14 MB_DATA13 DDRB_SDQ14
L20 MA_ADD15 MA_DATA14 H19 K24 MB_ADD15 MB_DATA14 B19
F19 DDRA_SDQ15 C19 DDRB_SDQ15
DDRA_SBS0# MA_DATA15 DDRB_SBS0# MB_DATA15
<10> DDRA_SBS0# U24 MA_BANK0 <11> DDRB_SBS0# U27 MB_BANK0
DDRA_SBS1# U21 H20 DDRA_SDQ16 DDRB_SBS1# T28 C21 DDRB_SDQ16
<10> DDRA_SBS1# MA_BANK1 MA_DATA16 <11> DDRB_SBS1# MB_BANK1 MB_DATA16
DDRA_SBS2# L23 F21 DDRA_SDQ17 DDRB_SBS2# K28 B22 DDRB_SDQ17
<10> DDRA_SBS2# MA_BANK2 MA_DATA17 <11> DDRB_SBS2# MB_BANK2 MB_DATA17
J23 DDRA_SDQ18 C23 DDRB_SDQ18
<10> DDRA_SDM[7..0] MA_DATA18 <11> DDRB_SDM[7..0] MB_DATA18
DDRA_SDM0 E14 H23 DDRA_SDQ19 DDRB_SDM0 D14 A24 DDRB_SDQ19
DDRA_SDM1 MA_DM0 MA_DATA19 DDRA_SDQ20 DDRB_SDM1 MB_DM0 MB_DATA19 DDRB_SDQ20
J17 MA_DM1 MA_DATA20 G20 A18 MB_DM1 MB_DATA20 D20
DDRA_SDM2 E21 E20 DDRA_SDQ21 DDRB_SDM2 A22 B21 DDRB_SDQ21
DDRA_SDM3 MA_DM2 MA_DATA21 DDRA_SDQ22 DDRB_SDM3 MB_DM2 MB_DATA21 DDRB_SDQ22
F25 MA_DM3 MA_DATA22 G22 C25 MB_DM3 MB_DATA22 E23
DDRA_SDM4 AD27 H22 DDRA_SDQ23 DDRB_SDM4 AF25 B23 DDRB_SDQ23
DDRA_SDM5 MA_DM4 MA_DATA23 DDRB_SDM5 MB_DM4 MB_DATA23
AC23 MA_DM5 AG22 MB_DM5
2 DDRA_SDM6 DDRA_SDQ24 DDRB_SDM6 DDRB_SDQ24 2
AD19 MA_DM6 MA_DATA24 G24 AH18 MB_DM6 MB_DATA24 E24
DDRA_SDM7 AC15 E25 DDRA_SDQ25 DDRB_SDM7 AD14 B25 DDRB_SDQ25
MA_DM7 MA_DATA25 DDRA_SDQ26 MB_DM7 MB_DATA25 DDRB_SDQ26
MA_DATA26 G27 MB_DATA26 B27
DDRA_SDQS0 G14 G26 DDRA_SDQ27 DDRB_SDQS0 C15 D28 DDRB_SDQ27
<10> DDRA_SDQS0 MA_DQS_H0 MA_DATA27 <11> DDRB_SDQS0 MB_DQS_H0 MB_DATA27
DDRA_SDQS0# H14 F23 DDRA_SDQ28 DDRB_SDQS0# B15 B24 DDRB_SDQ28
<10> DDRA_SDQS0# MA_DQS_L0 MA_DATA28 <11> DDRB_SDQS0# MB_DQS_L0 MB_DATA28
DDRA_SDQS1 G18 H24 DDRA_SDQ29 DDRB_SDQS1 E18 D24 DDRB_SDQ29
<10> DDRA_SDQS1 MA_DQS_H1 MA_DATA29 <11> DDRB_SDQS1 MB_DQS_H1 MB_DATA29
DDRA_SDQS1# H18 E28 DDRA_SDQ30 DDRB_SDQS1# D18 D26 DDRB_SDQ30
<10> DDRA_SDQS1# MA_DQS_L1 MA_DATA30 <11> DDRB_SDQS1# MB_DQS_L1 MB_DATA30
DDRA_SDQS2 J21 F27 DDRA_SDQ31 DDRB_SDQS2 E22 C27 DDRB_SDQ31
<10> DDRA_SDQS2 MA_DQS_H2 MA_DATA31 <11> DDRB_SDQS2 MB_DQS_H2 MB_DATA31
DDRA_SDQS2# H21 DDRB_SDQS2# D22
<10> DDRA_SDQS2# MA_DQS_L2 <11> DDRB_SDQS2# MB_DQS_L2
DDRA_SDQS3 E27 AB28 DDRA_SDQ32 DDRB_SDQS3 B26 AG26 DDRB_SDQ32
<10> DDRA_SDQS3 MA_DQS_H3 MA_DATA32 <11> DDRB_SDQS3 MB_DQS_H3 MB_DATA32
DDRA_SDQS3# E26 AC27 DDRA_SDQ33 DDRB_SDQS3# A26 AH26 DDRB_SDQ33
<10> DDRA_SDQS3# MA_DQS_L3 MA_DATA33 <11> DDRB_SDQS3# MB_DQS_L3 MB_DATA33
DDRA_SDQS4 AE26 AD25 DDRA_SDQ34 DDRB_SDQS4 AG24 AF23 DDRB_SDQ34
<10> DDRA_SDQS4 MA_DQS_H4 MA_DATA34 <11> DDRB_SDQS4 MB_DQS_H4 MB_DATA34
DDRA_SDQS4# AD26 AA24 DDRA_SDQ35 DDRB_SDQS4# AG25 AG23 DDRB_SDQ35
<10> DDRA_SDQS4# MA_DQS_L4 MA_DATA35 <11> DDRB_SDQS4# MB_DQS_L4 MB_DATA35
DDRA_SDQS5 AB22 AE28 DDRA_SDQ36 DDRB_SDQS5 AG21 AG27 DDRB_SDQ36
<10> DDRA_SDQS5 MA_DQS_H5 MA_DATA36 <11> DDRB_SDQS5 MB_DQS_H5 MB_DATA36
DDRA_SDQS5# AA22 AD28 DDRA_SDQ37 DDRB_SDQS5# AF21 AF27 DDRB_SDQ37
<10> DDRA_SDQS5# MA_DQS_L5 MA_DATA37 <11> DDRB_SDQS5# MB_DQS_L5 MB_DATA37
DDRA_SDQS6 AB18 AB26 DDRA_SDQ38 DDRB_SDQS6 AG17 AH24 DDRB_SDQ38
<10> DDRA_SDQS6 MA_DQS_H6 MA_DATA38 <11> DDRB_SDQS6 MB_DQS_H6 MB_DATA38
DDRA_SDQS6# AA18 AC25 DDRA_SDQ39 DDRB_SDQS6# AG18 AE24 DDRB_SDQ39
<10> DDRA_SDQS6# MA_DQS_L6 MA_DATA39 <11> DDRB_SDQS6# MB_DQS_L6 MB_DATA39
DDRA_SDQS7 AA14 DDRB_SDQS7 AH14
<10> DDRA_SDQS7 MA_DQS_H7 <11> DDRB_SDQS7 MB_DQS_H7
DDRA_SDQS7# AA15 Y23 DDRA_SDQ40 DDRB_SDQS7# AG14 AE22 DDRB_SDQ40
<10> DDRA_SDQS7# MA_DQS_L7 MA_DATA40 <11> DDRB_SDQS7# MB_DQS_L7 MB_DATA40
MA_DATA41 AA23 DDRA_SDQ41 MB_DATA41 AH22 DDRB_SDQ41
DDRA_CLK0 T21 Y21 DDRA_SDQ42 DDRB_CLK0 R26 AE20 DDRB_SDQ42
<10> DDRA_CLK0 MA_CLK_H0 MA_DATA42 <11> DDRB_CLK0 MB_CLK_H0 MB_DATA42
DDRA_CLK0# T22 AA20 DDRA_SDQ43 DDRB_CLK0# R27 AH20 DDRB_SDQ43
<10> DDRA_CLK0# MA_CLK_L0 MA_DATA43 <11> DDRB_CLK0# MB_CLK_L0 MB_DATA43
DDRA_CLK1 R23 AB24 DDRA_SDQ44 DDRB_CLK1 P27 AD23 DDRB_SDQ44
<10> DDRA_CLK1 MA_CLK_H1 MA_DATA44 <11> DDRB_CLK1 MB_CLK_H1 MB_DATA44
DDRA_CLK1# R24 AD24 DDRA_SDQ45 DDRB_CLK1# P28 AD22 DDRB_SDQ45
<10> DDRA_CLK1# MA_CLK_L1 MA_DATA45 <11> DDRB_CLK1# MB_CLK_L1 MB_DATA45
MA_DATA46 AA21 DDRA_SDQ46 MB_DATA46 AD21 DDRB_SDQ46
DDRA_CKE0 H28 AC21 DDRA_SDQ47 DDRB_CKE0 J26 AD20 DDRB_SDQ47
<10> DDRA_CKE0 MA_CKE0 MA_DATA47 <11> DDRB_CKE0 MB_CKE0 MB_DATA47
DDRA_CKE1 H27 DDRB_CKE1 J27
<10> DDRA_CKE1 MA_CKE1 <11> DDRB_CKE1 MB_CKE1
MA_DATA48 AA19 DDRA_SDQ48 MB_DATA48 AF19 DDRB_SDQ48
DDRA_ODT0 Y25 AC19 DDRA_SDQ49 DDRB_ODT0 W27 AE18 DDRB_SDQ49
<10> DDRA_ODT0 MA_ODT0 MA_DATA49 <11> DDRB_ODT0 MB_ODT0 MB_DATA49
DDRA_ODT1 AA27 AC17 DDRA_SDQ50 DDRB_ODT1 Y28 AE16 DDRB_SDQ50
<10> DDRA_ODT1 MA_ODT1 MA_DATA50 <11> DDRB_ODT1 MB_ODT1 MB_DATA50
MA_DATA51 AA17 DDRA_SDQ51 MB_DATA51 AH16 DDRB_SDQ51
DDRA_SCS0# V22 AB20 DDRA_SDQ52 DDRB_SCS0# V25 AG20 DDRB_SDQ52
3 <10> DDRA_SCS0# MA_CS_L0 MA_DATA52 <11> DDRB_SCS0# MB_CS_L0 MB_DATA52 3
DDRA_SCS1# AA26 Y19 DDRA_SDQ53 DDRB_SCS1# Y27 AG19 DDRB_SDQ53
<10> DDRA_SCS1# MA_CS_L1 MA_DATA53 <11> DDRB_SCS1# MB_CS_L1 MB_DATA53
MA_DATA54 AD18 DDRA_SDQ54 MB_DATA54 AF17 DDRB_SDQ54
DDRA_SRAS# V21 AD17 DDRA_SDQ55 DDRB_SRAS# V24 AD16 DDRB_SDQ55
<10> DDRA_SRAS# MA_RAS_L MA_DATA55 <11> DDRB_SRAS# MB_RAS_L MB_DATA55
DDRA_SCAS# W24 DDRB_SCAS# V27
<10> DDRA_SCAS# MA_CAS_L <11> DDRB_SCAS# MB_CAS_L
DDRA_SWE# W23 AA16 DDRA_SDQ56 DDRB_SWE# V28 AG15 DDRB_SDQ56
<10> DDRA_SWE# MA_WE_L MA_DATA56 <11> DDRB_SWE# MB_WE_L MB_DATA56
MA_DATA57 Y15 DDRA_SDQ57 MB_DATA57 AD15 DDRB_SDQ57
MEM_MA_RST# H25 AA13 DDRA_SDQ58 MEM_MB_RST# J25 AG13 DDRB_SDQ58
<10> MEM_MA_RST# MA_RESET_L MA_DATA58 <11> MEM_MB_RST# MB_RESET_L MB_DATA58
MEM_MA_EVENT# T24 AC13 DDRA_SDQ59 MEM_MB_EVENT# T25 AD13 DDRB_SDQ59
<10> MEM_MA_EVENT# MA_EVENT_L MA_DATA59 <11> MEM_MB_EVENT# MB_EVENT_L MB_DATA59
MA_DATA60 Y17 DDRA_SDQ60 MB_DATA60 AG16 DDRB_SDQ60
+MEM_VREF W20 M_VREF MA_DATA61 AB16 DDRA_SDQ61 MB_DATA61 AF15 DDRB_SDQ61
MA_DATA62 AB14 DDRA_SDQ62 MB_DATA62 AE14 DDRB_SDQ62
+1.5V 1 2 M_ZVDDIO W21 M_ZVDDIO MA_DATA63 Y13 DDRA_SDQ63 MB_DATA63 AF13 DDRB_SDQ63
R3 39.2_0402_1%
Place them close to APU within 1"
15mil
ME@ LOTES_ACA-ZIF-109-P12-A_FS1R2
ME@ LOTES_ACA-ZIF-109-P12-A_FS1R2
EVENT# pull high 0.75V reference voltage +1.5V
+1.5V
2
4 R4 4
1K_0402_1%
R5 1 2 1K_0402_5% MEM_MA_EVENT# 15mil
1
R6 1 2 1K_0402_5% MEM_MB_EVENT# +MEM_VREF
2
1 2
R7
1K_0402_1% C45 C46 Security Classification Compal Secret Data Compal Electronics, Inc.
1000P_0402_50V7K 0.1U_0402_16V7K 2011/10/12 2013/10/12 Title
2 1 Issued Date Deciphered Date
FS1r2 DDRIII Memory I/F
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 6 of 51
A B C D E
A B C D E
JCPU1D
Place near APU
ANALOG/DISPLAY/MISC
<24> DP0_TXP0_C
C56 1 2 0.1U_0402_16V7K DP0_TXP0 L3 DP0_TXP0 DP0_AUXP D1 DP0_AUXP C47 1 2 0.1U_0402_16V7K DP0_AUXP_C <24> To LVDS DP0_AUXP R57 2 1 1.8K_0402_5%
C48 1 2 0.1U_0402_16V7K DP0_TXN0 L2 D2 DP0_AUXN C49 1 2 0.1U_0402_16V7K
<24> DP0_TXN0_C DP0_TXN0 DP0_AUXN DP0_AUXN_C <24> Translater DP0_AUXN R25 2 1 1.8K_0402_5%
K5 DP0_TXP1 LVDS DP1_AUXP E1 ML_VGA_AUXP C57 1 2 0.1U_0402_16V7K ML_VGA_AUXP_C <13>
K4 DP0_TXN1 DP1_AUXN E2 ML_VGA_AUXN C52 1 2 0.1U_0402_16V7K ML_VGA_AUXN_C <13> To FCH ML_VGA_AUXP R10 2 1 1.8K_0402_5%
K2 D5 ML_VGA_AUXN R11 2 1 1.8K_0402_5%
DP0_TXP2 DP2_AUXP HDMI_CLK <26>
K1 DP0_TXN2 DP2_AUXN D6 HDMI_DATA <26> To HDMI
DISPLAY PORT 0
J3 DP0_TXP3 DP3_AUXP E5
Place near APU J2 DP0_TXN3 DP3_AUXN E6
C63 1 2 0.1U_0402_16V7K DP1_TXP0 H5 F5
1 <13> ML_VGA_TXP0 DP1_TXP0 DP4_AUXP 1
<13> ML_VGA_TXN0
C64 1 2 0.1U_0402_16V7K DP1_TXN0 H4 DP1_TXN0 DP4_AUXN F6
DISPLAY PORT MISC.
<13> ML_VGA_TXP1
C65 1 2 0.1U_0402_16V7K DP1_TXP1 H2 DP1_TXP1 DP5_AUXP G5
C66 1 2 0.1U_0402_16V7K DP1_TXN1 H1 G6
<13> ML_VGA_TXN1 DP1_TXN1 DP5_AUXN
To FCH
C67 1 2 0.1U_0402_16V7K DP1_TXP2 G3 D3 +1.5V +3VS Asserted as an input to force the
<13> ML_VGA_TXP2 DP1_TXP2 DP0_HPD LVDS_HPD <24>
C68 1 2 0.1U_0402_16V7K DP1_TXN2 G2 E3 processor into the HTC-active state
<13> ML_VGA_TXN2 DP1_TXN2 DP1_HPD FCH_CRT_HPD <13>
DISPLAY PORT 1
DP2_HPD D7 HDMI_DET <26>
C69 1 2 0.1U_0402_16V7K DP1_TXP3 F2 E7
<13> ML_VGA_TXP3 DP1_TXP3 DP3_HPD
1
C70 1 2 0.1U_0402_16V7K DP1_TXN3 F1 F7
<13> ML_VGA_TXN3 DP1_TXN3 DP4_HPD
G7 R13 R14 R12
C58 HDMI@ 1 DP5_HPD
<26> HDMI_TX2P 2 0.1U_0402_16V7K DP2_TXP0 L9 DP2_TXP0
1K_0402_5% 10K_0402_5% 10K_0402_5%
<26> HDMI_TX2N
C53 HDMI@ 1 2 0.1U_0402_16V7K DP2_TXN0 L8 DP2_TXN0 DP_BLON C6
B6
2 2
2
C59 HDMI@ 1 DP_DIGON
<26> HDMI_TX1P 2 0.1U_0402_16V7K DP2_TXP1 L5 DP2_TXP1 HDMI DP_VARY_BL A6 DP_INT_PWM <9>
C54 HDMI@ 1 2 0.1U_0402_16V7K DP2_TXN1 L6
B
<26> HDMI_TX1N DP2_TXN1
DP_AUX_ZVSS C1 DP_AUX_ZVSS R16 1 2 150_0402_1% Q1
C55 HDMI@ 1 2 0.1U_0402_16V7K DP2_TXP2 K8 APU_PROCHOT#
E
<26> HDMI_TX0P DP2_TXP2 1 3 H_PROCHOT# <33,40,47>
C60 HDMI@ 1 2 0.1U_0402_16V7K DP2_TXN2 K7
C
<26> HDMI_TX0N DP2_TXN2 TEST6 AD12
MMBT3904_NL_SOT23-3
DISPLAY PORT 2
TEST9 M18 T5
<26> HDMI_CLKP
C61 HDMI@ 1 2 0.1U_0402_16V7K DP2_TXP3 J6 DP2_TXP3 TEST10 N18 T6
C62 HDMI@ 1 2 0.1U_0402_16V7K DP2_TXN3 J5 F11 T66
<26> HDMI_CLKN DP2_TXN3 TEST14
TEST15 G11 T67
AE11 H11 T3 1 @ 2
<12> APU_CLK CLKIN_H TEST16
AD11 J11 T4 R868 0_0402_5%
<12> APU_CLK# CLKIN_L TEST17
Place near Connector F12 APU_TEST18 R18 1 2 1K_0402_5%
CLK
TEST18
<12> APU_DISP_CLK AB11 DISP_CLKIN_H TEST19 G12 APU_TEST19 R19 1 2 1K_0402_5%
<12> APU_DISP_CLK# AA11 DISP_CLKIN_L TEST20 J12 APU_TEST20 R21 1 2 1K_0402_5%
TEST
TEST24 H12 APU_TEST24 R22 1 2 1K_0402_5%
<47> APU_SVC B3 SVC TEST25_H AE10 TEST25_H R23 1 2 510_0402_1%
<47> APU_SVD A3 SVD TEST25_L AD10 TEST25_L R24 1 2 510_0402_1% +1.2VS
TEST28_H L10 T7
2 2
C3 M10
SER.
<47> APU_SVT SVT TEST28_L T8
TEST30_H P19
APU_SIC AG12 R19
APU_SID SIC TEST30_L
AH12 SID TEST31 K22 APU_TEST31 R27 1 2 39.2_0402_1%
TEST32_H T19
<12> APU_RST# AF10 RESET_L TEST32_L N19
<12,47> APU_PWRGD AB12 PWROK TEST35 AA12 APU_TEST35 R28 1 HDMI@ 2 300_0402_5% +1.5V
R29 1 nonHDMI@
2 300_0402_5%
CTRL
<12> APU_PROCHOT# AC10 PROCHOT_L FS1R2 W10 FS1R2 R30 1 2 10K_0402_5% +3VALW
APU_THERMTRIP# AE12 AC12
THERMTRIP_L DMAACTIVE_L ALLOW_STOP <12> +1.5V
ALERT_L AF12 ALERT_L THERMTRIP shutdown
TEST4 P18 T11
APU_TDI H10 R18 T12 temperature: 115 degree
APU_TDO TDI TEST5
J10 TDO
1
APU_TCK F10
APU_TMS TCK JTAG
R20 R17 Indicates to the FCH that a thermal trip
G10 TMS
APU_TRST# F9 Y10 1K_0402_5% 10K_0402_5% has occurred. Its assertion will cause the FCH to
APU_DBRDY TRST_L RSVD1
G9 AA10 transition the system to S5 immediately
DBRDY RSVD2
RSVD
APU_DBREQ# H9 Y12
2 2
DBREQ_L RSVD3
RSVD4 K21
B
<47> APU_VDD_SEN_L B4 VSS_SENSE
C5 Q2
VDDP_SENSE
E
A4 APU_THERMTRIP# 3 1 1 2
<47> APU_VDDNB_SEN_H VDDNB_SENSE H_THERMTRIP# <14>
SENSE
C
Route as differential A5 R55 0_0402_5%
VDDIO_SENSE MMBT3904_NL_SOT23-3
with VSS_SENSE <47> APU_VDD_SEN_H C4 VDD_SENSE
B5 VDDR_SENSE
1 2 MAINPWON <33,40,42>
R56 0_0402_5%
ME@ LOTES_ACA-ZIF-109-P12-A_FS1R2 @
3 3
ESD request
@
CPU TSI interface level shift
APU_PWRGD C1033
1 2 100P_0402_50V8J BSH111, the Vgs is: +1.5V HDT Debug conn +1.5V
@
C71
min = 0.4V +1.5V
1 2 0.1U_0402_16V4Z
Max = 1.3V JHDT1
1 2 APU_TCK R35 1 2 1K_0402_5%
1 2
2
+3VS 1 R31 2 1 R32 2
R37 3 4 APU_TMS R38 1 2 1K_0402_5%
31.6K_0402_1% 30K_0402_1% 3 4
1K_0402_5%
+1.5V 5 6 APU_TDI R40 1 2 1K_0402_5%
5 6
1
7 8 APU_TDO
7 8
2
G
R42 1 2 1K_0402_5% APU_SIC Q3
APU_TRST# 9 10 APU_PWRGD
R44 APU_SID APU_SID 9 10
1 2 1K_0402_5% 3 1 EC_SMB_DA2_SUS <33> To EC
R45 2 10K_0402_5% APU_RST#
S
1 11 11 12 12
R46 1 2 1K_0402_5% ALERT_L
BSH111 1N_SOT23-3 R47 1 2 10K_0402_5% 13 14 APU_DBRDY
R48 13 14
1 2 1K_0402_5% ALLOW_STOP
R49 1 2 10K_0402_5% 15 16 APU_DBREQ# R50 1 2 1K_0402_5%
+1.5VS 15 16
2
G
Q4 17 17 18 18 R51 1 2 0_0402_5% APU_TEST19
R52 1 2 300_0402_5% APU_RST#
APU_SIC 3 1 To EC 19 20 R53 1 2 0_0402_5% APU_TEST18
EC_SMB_CK2_SUS <33> 19 20
R54 2 300_0402_5% APU_PWRGD
S
1
4 4
R36 1 @ 2 1K_0402_5% APU_SVT BSH111 1N_SOT23-3
SAMTE_ASP-136446-07-B
R39 1 @ 2 1K_0402_5% APU_SVC ME@
R41 1 @ 2 1K_0402_5% APU_SVD
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FS1r2 Display/MISC/HDT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Monday, November 07, 2011 Sheet 7 of 51
A B C D E
A B C D E
Power Name Consumption
VDD
+APU_CORE 60A JCPU1F
VDDNB J20 VSS_1 VSS_73 A19
+APU_CORE
+APU_CORE_NB 29A L4
R7
VSS_2 VSS_74 A21
A23
VSS_3 VSS_75
VDDIO W18 VSS_4 VSS_76 A25
+1.5V 3.2A A15 VSS_5 VSS_77 A7
C75
0.22U_0402_6.3V6K
C72
0.22U_0402_6.3V6K
C73
0.01U_0402_16V7K
C76
0.01U_0402_16V7K
C77
0.01U_0402_16V7K
C78
180P_0402_50V8J
C74
180P_0402_50V8J
AB17 VSS_6 VSS_78 AA4
VDDP / VDDR 1 1 1 1 1 1 1 AC22 VSS_7 VSS_79 AA7
+APU_CORE JCPU1E +APU_CORE AE21 AB13
+1.2VS 5A / 3.5A AF24
VSS_8 VSS_80
AB15
VSS_9 VSS_81
VDDA F8 VDD_1 VDD_32 R11
2 2 2 2 2 2 2
AH23 VSS_10 VSS_82 AB19
1 1
H6 T10 AH25 AB21
+2.5VS 0.5A J1
VDD_2 VDD_33
H8 B7
VSS_11 VSS_83
AB23
VDD_3 VDD_34 VSS_12 VSS_84
J14 VDD_4 VDD_35 G1 C14 VSS_13 VSS_85 AB25
P6 VDD_5 VDD_36 U11 C16 VSS_14 VSS_86 AB27
P10 VDD_6 VDD_37 W11 C2 VSS_15 VSS_87 AB9
J16 VDD_7 VDD_38 W13 C20 VSS_16 VSS_88 AC14
J18 W15 +APU_CORE_NB C22 AC16
VDD_8 VDD_39 VSS_17 VSS_89
J9 VDD_9 VDD_40 W17 C24 VSS_18 VSS_90 AC18
K19 VDD_10 VDD_41 W19 C26 VSS_19 VSS_91 AC20
K3 VDD_11 VDD_42 AB3 C28 VSS_20 VSS_92 AC24
C79
0.22U_0402_6.3V6K
C80
0.22U_0402_6.3V6K
C81
180P_0402_50V8J
C82
180P_0402_50V8J
C83
180P_0402_50V8J
K17 VDD_12 VDD_43 AD3 D13 VSS_21 VSS_93 AC26
M3 VDD_13 VDD_44 AD6 1 1 1 1 1 D15 VSS_22 VSS_94 AC28
K6 VDD_14 VDD_45 AE1 D17 VSS_23 VSS_95 AC4
V10 VDD_15 VDD_46 L1 D19 VSS_24 VSS_96 AC7
V18 VDD_16 VDD_47 Y6 D23 VSS_25 VSS_97 AD9
2 2 2 2 2
V3 VDD_17 VDD_48 M6 D25 VSS_26 VSS_98 AE13
F3 VDD_18 VDD_49 N11 D27 VSS_27 VSS_99 AE15
L18 VDD_19 VDD_50 N1 E4 VSS_28 VSS_100 AE17
V6 VDD_20 VDD_51 T3 E9 VSS_29 VSS_101 M9
W1 VDD_21 VDD_52 T6 (330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00) F14 VSS_30 VSS_102 N10
T18 VDD_22 VDD_53 U19 F16 VSS_31 VSS_103 N4
Y14 U1 +1.5V F18 N7
VDD_23 VDD_54 VSS_32 VSS_104
AA1 VDD_24 VDD_55 Y16 F20 VSS_33 VSS_105 R10
AB6 VDD_25 VDD_56 Y18 F22 VSS_34 VSS_106 R4
AC1 VDD_26 VDD_57 Y3 F26 VSS_35 VSS_107 T11
C84
22U_0603_6.3V6M
C85
22U_0603_6.3V6M
C86
22U_0603_6.3V6M
C87
22U_0603_6.3V6M
C88
22U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C93
0.22U_0402_6.3V6K
C94
0.22U_0402_6.3V6K
C95
0.22U_0402_6.3V6K
C96
0.22U_0402_6.3V6K
C97
0.22U_0402_6.3V6K
C98
0.22U_0402_6.3V6K
C99
180P_0402_50V8J
C100
330U_2.5V_M
R1 VDD_27 VDD_58 D4 1 F28 VSS_36 VSS_108 T9
C89
C90
C91
C92
P3 VDD_28 VDD_59 F4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G13 VSS_37 VSS_109 U10
K10 AF6 + G15 U18
VDD_29 VDD_60 @ VSS_38 VSS_110
H3 VDD_30 VDD_61 AF3 G17 VSS_39 VSS_111 U4
M19 VDD_31 VDD_62 L11 G19 VSS_40 VSS_112 U7
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
G21 VSS_41 VSS_113 V11
G23 VSS_42 VSS_114 AE19
2 2
+APU_CORE_NB C8 VDDNB_1 VDDNB_13 C11 +APU_CORE_NB G25 VSS_43 VSS_115 AE23
D10 VDDNB_2 VDDNB_14 C12 G4 VSS_44 VSS_116 AE25
B8 VDDNB_3 VDDNB_15 D9 J22 VSS_45 VSS_117 AE27
B12 VDDNB_4 VDDNB_16 D8 J24 VSS_46 VSS_118 AE4
C9 VDDNB_5 VDDNB_17 D12 J4 VSS_47 VSS_119 AE7
A9 VDDNB_6 VDDNB_18 D11 J7 VSS_48 VSS_120 AF14
A10 VDDNB_7 VDDNB_19 B11 K11 VSS_49 VSS_121 AF16
A8 VDDNB_8 VDDNB_20 A12 K14 VSS_50 VSS_122 AF18
A11 B10 Module design without +APU_CORE_NB +1.5V Across VDDIO and VSS K9 AF20
VDDNB_9 VDDNB_21 VSS_51 VSS_123
E10 VDDNB_10 VDDNB_22 E12 power plane only Decoupling cap split AC11 VSS_52 VSS_124 AF22
E11 VDDNB_11 VDDNB_23 B9 L19 VSS_53 VSS_125 AF26
C10 VDDNB_12 L7 VSS_54 VSS_126 AF28
C101
0.22U_0402_6.3V6K
C102
0.22U_0402_6.3V6K
C103
180P_0402_50V8J
C104
180P_0402_50V8J
K13 +VDDNB_CAP M11 AF9
VDDNB_CAP_1 VSS_55 VSS_127
VDDNB_CAP_2 K12 1 1 1 1 AF11 VSS_56 VSS_128 AG4
C168
C169
C145
V19 VSS_57 VSS_129 AG7
1 1 1 V9 VSS_58 VSS_130 AH13
W16 VSS_59 VSS_131 AH15
2 2 2 2
+1.5V H26 VDDIO_1 VDDIO_19 T23 +1.5V W4 VSS_60 VSS_132 AH17
22U_0603_6.3V6M
22U_0603_6.3V6M
180P_0402_50V8J
K20 VDDIO_2 VDDIO_20 T26 W7 VSS_61 VSS_133 AH19
2 2 2
J28 VDDIO_3 VDDIO_21 U22 Y11 VSS_62 VSS_134 AH21
K23 VDDIO_4 VDDIO_22 U25 Y20 VSS_63 VSS_135 P9
K26 VDDIO_5 VDDIO_23 U28 Y22 VSS_64 VSS_136 C18
L22 VDDIO_6 VDDIO_24 Y26 Y9 VSS_65 VSS_137 D21
L25 VDDIO_7 VDDIO_25 T20 A17 VSS_66 VSS_138 W14
L28 VDDIO_8 VDDIO_26 R28 A13 VSS_67 VSS_139 P11
M20 VDDIO_9 VDDIO_27 R25 K16 VSS_68 VSS_140 C7
M23 VDDIO_10 VDDIO_28 R22 F24 VSS_69 VSS_141 E8
M26 VDDIO_11 VDDIO_29 V20 G8 VSS_70 VSS_142 K18
N22 VDDIO_12 VDDIO_30 V23 H7 VSS_71 VSS_143 W12
N25 V26 Northbridge Power Pins J8
VDDIO_13 VDDIO_31 for Remote Decoupling VSS_72
N28 VDDIO_14 VDDIO_32 W22
P20 VDDIO_15 VDDIO_33 W25
3 LOTES_ACA-ZIF-109-P12-A_FS1R2 3
P23 VDDIO_16 VDDIO_34 W28
P26 VDDIO_17 VDDIO_35 Y24
AA28 VDDIO_18 VDDIO_36 G28 ME@
VDDP decoupling +1.2VS
AH6 VDDP_1 VDDR_1 AG10
AH5 VDDP_2 VDDR_2 AH8 VDDR decoupling
180P_0402_50V8J
180P_0402_50V8J
AH4 VDDP_3 VDDR_3 AH9
C105
C106
C107
0.22U_0402_6.3V6K
C108
0.22U_0402_6.3V6K
AH3 VDDP_4 VDDR_4 AH10 +1.2VS
1 1 1 1 AH7 VDDP_5
C109
180P_0402_50V8J
C110
180P_0402_50V8J
C111
1000P_0402_50V7K
C115
0.22U_0402_6.3V6K
C116
0.22U_0402_6.3V6K
AB10 VDDA 1 1 1 1 1
2 2 2 2
2 2 2 2 2
LOTES_ACA-ZIF-109-P12-A_FS1R2
ME@ Demo Board Capacitor
APU_CORE CORE_NB CORE_NB_CAP VDDIO_SUS
22uF x 10 22uF x 2 22uF x 2 (CPU side)
0.22uF x 2 10uF x 1 180pF x 1 22uF x 4
0.01uF x 3 0.22uF x 2 4.7uF x 4
180pF x 2 180pF x 3 0.22uF x 6 +2(split)
180pF x 1 + 2(split)
4
VDDP VDDR VDDA VDDIO_SUS 4
+2.5VS L1 40mil 0.22uF x 2 0.22uF x 2 4.7uF x 1 (DIMM x2)
FBMA-L11-201209-221LMA30T_0805
+VDDA
180pF x 2 1nF x 1 0.22uF x 1 100uF x 2
2 1
180pF x 2 3.3nF x 1 0.1uF x 12
C117
3300P_0402_50V7K
C118
0.22U_0402_6.3V6K
C119
4.7U_0402_6.3V6M
1 1
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
2
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FS1r2 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Monday, November 07, 2011 Sheet 8 of 51
A B C D E
5 4 3 2 1
P
a
n
e
l
P
W
M
+3VS
1
D R76 R77 D
47K_0402_5% 4.7K_0402_5%
2
APU_INVT_PWM <24>
1
2
G Q11 @
MMBT3904_NL_SOT23-3
S 2N7002K_SOT23-3 R884
3
1
Q12 C 0_0402_5%
<7> DP_INT_PWM 1 2 2
2
R78 2.2K_0402_5% B
E
3
1
R79
4.7K_0402_5%
1
R885
0_0402_5%
2
C C
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
FS1r2 Signal Level Shifter
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 9 of 51
5 4 3 2 1
A B C D E
+1.5V +1.5V
+VREF_DQ
JDIMM1 ME@
1 VREF_DQ VSS 2
3 4 DDRA_SDQ4 DDRA_SDQ[0..63]
DDRA_SDQ0 VSS DQ4 DDRA_SDQ5 DDRA_SDQ[0..63] <6>
5 DQ0 DQ5 6
DDRA_SDQ1 7 8 DDRA_SDM[0..7]
DQ1 VSS DDRA_SDM[0..7] <6>
9 10 DDRA_SDQS0#
VSS DQS0# DDRA_SDQS0# <6> DDRA_SMA[0..15]
DDRA_SDM0 11 12 DDRA_SDQS0 DDRA_SMA[0..15] <6>
DM0 DQS0 DDRA_SDQS0 <6>
13 VSS VSS 14
DDRA_SDQ2 15 16 DDRA_SDQ6
DDRA_SDQ3 DQ2 DQ6 DDRA_SDQ7
17 DQ3 DQ7 18
19 VSS VSS 20
1 DDRA_SDQ8 DDRA_SDQ12 1
21 DQ8 DQ12 22
DDRA_SDQ9 23 24 DDRA_SDQ13
DQ9 DQ13
25 VSS VSS 26
DDRA_SDQS1# 27 28 DDRA_SDM1
<6> DDRA_SDQS1# DQS1# DM1
DDRA_SDQS1 29 30 MEM_MA_RST#
<6> DDRA_SDQS1 DQS1 RESET# MEM_MA_RST# <6>
31 VSS VSS 32
DDRA_SDQ10 33 34 DDRA_SDQ14 Place near DIMM1
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15 +1.5V
35 DQ11 DQ15 36
37 VSS VSS 38
DDRA_SDQ16 39 40 DDRA_SDQ20 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21
41 DQ17 DQ21 42 2 2 2 2 2 2
43 VSS VSS 44
DDRA_SDQS2# 45 46 DDRA_SDM2 C120 C121 C122 C123 C124 C125
<6> DDRA_SDQS2# DQS2# DM2
DDRA_SDQS2 47 48
<6> DDRA_SDQS2 DQS2 VSS 1 1 1 1 1 1
49 50 DDRA_SDQ22
DDRA_SDQ18 VSS DQ22 DDRA_SDQ23 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
51 DQ18 DQ23 52
DDRA_SDQ19 53 54
DQ19 VSS DDRA_SDQ28
55 VSS DQ28 56
DDRA_SDQ24 57 58 DDRA_SDQ29
DDRA_SDQ25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDRA_SDQS3#
VSS DQS3# DDRA_SDQS3# <6>
DDRA_SDM3 63 64 DDRA_SDQS3
DM3 DQS3 DDRA_SDQS3 <6>
65 VSS VSS 66
DDRA_SDQ26 67 68 DDRA_SDQ30
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31
69 DQ27 DQ31 70
71 VSS VSS 72
DDRA_CKE0 73 74 DDRA_CKE1
<6> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <6>
75 VDD VDD 76
77 78 DDRA_SMA15
DDRA_SBS2# NC A15 DDRA_SMA14
<6> DDRA_SBS2# 79 BA2 A14 80
2 2
81 VDD VDD 82
DDRA_SMA12 83 84 DDRA_SMA11
DDRA_SMA9 A12/BC# A11 DDRA_SMA7
85 A9 A7 86
87 VDD VDD 88
DDRA_SMA8 89 90 DDRA_SMA6
DDRA_SMA5 A8 A6 DDRA_SMA4
91 A5 A4 92
93 VDD VDD 94
DDRA_SMA3 95 96 DDRA_SMA2
DDRA_SMA1 A3 A2 DDRA_SMA0
97 A1 A0 98
99 100 +1.5V +1.5V
DDRA_CLK0 VDD VDD DDRA_CLK1
<6> DDRA_CLK0 101 CK0 CK1 102 DDRA_CLK1 <6>
DDRA_CLK0# 103 104 DDRA_CLK1#
<6> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <6>
2
105 VDD VDD 106
DDRA_SMA10 107 108 DDRA_SBS1# R80 R81
A10/AP BA1 DDRA_SBS1# <6> +VREF_DQ +VREF_CA
DDRA_SBS0# 109 110 DDRA_SRAS# 1K_0402_1% 1K_0402_1%
<6> DDRA_SBS0# BA0 RAS# DDRA_SRAS# <6>
111 VDD VDD 112
DDRA_SWE# 113 114 DDRA_SCS0# 15mil 15mil
DDRA_SCS0# <6>
1
<6> DDRA_SWE# DDRA_SCAS# WE# S0# DDRA_ODT0 +VREF_DQ +VREF_CA
<6> DDRA_SCAS# 115 CAS# ODT0 116 DDRA_ODT0 <6>
117 VDD VDD 118
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDRA_SMA13 119 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 <6>
DDRA_SCS1# 121 122
<6> DDRA_SCS1# S1# NC
2
123 VDD VDD 124 1 1 1 1
125 126 +VREF_CA C126 C129 R82 C127 C128 R83
TEST VREF_CA 1K_0402_1% 1K_0402_1%
127 VSS VSS 128
DDRA_SDQ32 129 130 DDRA_SDQ36
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37 2 2 2 2
131 132
1
DQ33 DQ37
133 VSS VSS 134
DDRA_SDQS4# 135 136 DDRA_SDM4
<6> DDRA_SDQS4# DQS4# DM4
DDRA_SDQS4 137 138
<6> DDRA_SDQS4 DQS4 VSS
139 140 DDRA_SDQ38
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39
141 DQ34 DQ39 142
DDRA_SDQ35 143 144
3 DQ35 VSS DDRA_SDQ44 3
145 VSS DQ44 146
DDRA_SDQ40 147 148 DDRA_SDQ45
DDRA_SDQ41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDRA_SDQS5#
VSS DQS5# DDRA_SDQS5# <6>
DDRA_SDM5 153 154 DDRA_SDQS5
DM5 DQS5 DDRA_SDQS5 <6>
155 VSS VSS 156
DDRA_SDQ42 157 158 DDRA_SDQ46
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
159 DQ43 DQ47 160
161 VSS VSS 162
DDRA_SDQ48 163 164 DDRA_SDQ52
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53
165 DQ49 DQ53 166
167 VSS VSS 168
DDRA_SDQS6# 169 170 DDRA_SDM6
<6> DDRA_SDQS6# DQS6# DM6
DDRA_SDQS6 171 172
<6> DDRA_SDQS6 DQS6 VSS
173 174 DDRA_SDQ54
DDRA_SDQ50 VSS DQ54 DDRA_SDQ55
175 DQ50 DQ55 176
DDRA_SDQ51 177 178
DQ51 VSS DDRA_SDQ60
179 VSS DQ60 180
DDRA_SDQ56 181 182 DDRA_SDQ61
DDRA_SDQ57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDRA_SDQS7#
VSS DQS7# DDRA_SDQS7# <6>
DDRA_SDM7 187 188 DDRA_SDQS7
DM7 DQS7 DDRA_SDQS7 <6>
189 VSS VSS 190
DDRA_SDQ58 191 192 DDRA_SDQ62
DDRA_SDQ59 DQ58 DQ62 DDRA_SDQ63
193 DQ59 DQ63 194
R84 10K_0402_5% 195 196
VSS VSS MEM_MA_EVENT#
1 2 197 SA0 EVENT# 198 MEM_MA_EVENT# <6>
+3VS 199 VDDSPD SDA 200 FCH_SDATA0 <11,14,32>
201 SA1 SCL 202 FCH_SCLK0 <11,14,32>
203 VTT VTT 204 +0.75VS
1
1 1
205 GND1 GND2 206
4 C130 C131 R85 4
207 BOSS1 BOSS2 208
2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 10K_0402_5%
2 2
2
LCN_DAN06-K4406-0103
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/10/12 2013/10/12 Title
Reverse H:4mm Issued Date Deciphered Date
DDRIII SO-DIMM 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 10 of 51
A B C D E
A B C D E
+1.5V +1.5V
+VREF_DQ JDIMM2 ME@
1 VREF_DQ VSS1 2
3 4 DDRB_SDQ4 DDRB_SDQ[0..63]
DDRB_SDQ0 VSS2 DQ4 DDRB_SDQ5 DDRB_SDQ[0..63] <6>
5 DQ0 DQ5 6
DDRB_SDQ1 7 8 DDRB_SDM[0..7]
DQ1 VSS3 DDRB_SDM[0..7] <6>
9 10 DDRB_SDQS0#
VSS4 DQS#0 DDRB_SDQS0# <6> DDRB_SMA[0..15]
DDRB_SDM0 11 12 DDRB_SDQS0 DDRB_SMA[0..15] <6>
DM0 DQS0 DDRB_SDQS0 <6>
13 VSS5 VSS6 14
DDRB_SDQ2 15 16 DDRB_SDQ6
DDRB_SDQ3 DQ2 DQ6 DDRB_SDQ7
17 DQ3 DQ7 18
19 VSS7 VSS8 20
1 DDRB_SDQ8 21 22 DDRB_SDQ12 +VREF_DQ 1
DDRB_SDQ9 DQ8 DQ12 DDRB_SDQ13 +VREF_CA
23 DQ9 DQ13 24
DDRB_SDQS1#
25 VSS9 VSS10 26
DDRB_SDM1
15mil 15mil
<6> DDRB_SDQS1# 27 DQS#1 DM1 28
DDRB_SDQS1 29 30 MEM_MB_RST# +VREF_DQ +VREF_CA
<6> DDRB_SDQS1 DQS1 RESET# MEM_MB_RST# <6>
31 VSS11 VSS12 32
1000P_0402_50V7K
1000P_0402_50V7K
DDRB_SDQ10 33 34 DDRB_SDQ14
DQ10 DQ14
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDRB_SDQ11 35 36 DDRB_SDQ15
DQ11 DQ15
37 VSS13 VSS14 38 1 1 1 1
C132
C133
C134
DDRB_SDQ16 39 40 DDRB_SDQ20 C135
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDRB_SDQS2# DDRB_SDM2 2 2 2 2
<6> DDRB_SDQS2# 45 DQS#2 DM2 46
DDRB_SDQS2 47 48
<6> DDRB_SDQS2 DQS2 VSS17
49 50 DDRB_SDQ22
DDRB_SDQ18 VSS18 DQ22 DDRB_SDQ23
51 DQ18 DQ23 52
DDRB_SDQ19 53 54
DQ19 VSS19 DDRB_SDQ28
55 VSS20 DQ28 56
DDRB_SDQ24 57 58 DDRB_SDQ29
DDRB_SDQ25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDRB_SDQS3#
VSS22 DQS#3 DDRB_SDQS3# <6>
DDRB_SDM3 63 64 DDRB_SDQS3
DM3 DQS3 DDRB_SDQS3 <6>
65 VSS23 VSS24 66
DDRB_SDQ26 67 68 DDRB_SDQ30
DDRB_SDQ27 DQ26 DQ30 DDRB_SDQ31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
DDRB_CKE0 DDRB_CKE1
Place near DIMM2
<6> DDRB_CKE0 73 CKE0 CKE1 74 DDRB_CKE1 <6>
75 76 +1.5V
VDD1 VDD2 DDRB_SMA15
77 NC1 A15 78
2 DDRB_SBS2# DDRB_SMA14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
<6> DDRB_SBS2# 79 BA2 A14 80
81 VDD3 VDD4 82 2 2 2 2 2 2
DDRB_SMA12 83 84 DDRB_SMA11
DDRB_SMA9 A12/BC# A11 DDRB_SMA7 C136 C137 C138 C139 C140 C141
85 A9 A7 86
87 VDD5 VDD6 88
DDRB_SMA8 DDRB_SMA6 1 1 1 1 1 1
89 A8 A6 90
DDRB_SMA5 91 92 DDRB_SMA4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A5 A4
93 VDD7 VDD8 94
DDRB_SMA3 95 96 DDRB_SMA2
DDRB_SMA1 A3 A2 DDRB_SMA0
97 A1 A0 98
99 VDD9 VDD10 100
DDRB_CLK0 101 102 DDRB_CLK1
<6> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <6>
DDRB_CLK0# 103 104 DDRB_CLK1#
<6> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <6>
105 VDD11 VDD12 106
DDRB_SMA10 107 108 DDRB_SBS1#
A10/AP BA1 DDRB_SBS1# <6>
DDRB_SBS0# 109 110 DDRB_SRAS#
<6> DDRB_SBS0# BA0 RAS# DDRB_SRAS# <6>
111 112 +0.75VS
DDRB_SWE# VDD13 VDD14 DDRB_SCS0# +1.5V
<6> DDRB_SWE# 113 WE# S0# 114 DDRB_SCS0# <6>
DDRB_SCAS# 115 116 DDRB_ODT0
<6> DDRB_SCAS# CAS# ODT0 DDRB_ODT0 <6>
117 VDD15 VDD16 118
DDRB_SMA13 119 120 DDRB_ODT1 2 1
A13 ODT1 DDRB_ODT1 <6>
DDRB_SCS1# 121 122
<6> DDRB_SCS1# S1# NC2 C142 C143
123 VDD17 VDD18 124 1
125 126 +VREF_CA 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
NCTEST VREF_CA 1 2 + C144
127 VSS27 VSS28 128
DDRB_SDQ32 129 130 DDRB_SDQ36 220U_6.3V_M
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37
131 DQ33 DQ37 132
2 @
133 VSS29 VSS30 134
DDRB_SDQS4# 135 136 DDRB_SDM4
<6> DDRB_SDQS4# DQS#4 DM4
DDRB_SDQS4 137 138
<6> DDRB_SDQS4 DQS4 VSS31
139 140 DDRB_SDQ38
DDRB_SDQ34 VSS32 DQ38 DDRB_SDQ39
141 DQ34 DQ39 142
3 DDRB_SDQ35 3
143 DQ35 VSS33 144
145 146 DDRB_SDQ44
DDRB_SDQ40 VSS34 DQ44 DDRB_SDQ45
147 DQ40 DQ45 148 SF000002Y00
DDRB_SDQ41 149 150
DQ41 VSS35 DDRB_SDQS5#
151 VSS36 DQS#5 152 DDRB_SDQS5# <6>
DDRB_SDM5 153 154 DDRB_SDQS5
DM5 DQS5 DDRB_SDQS5 <6>
155 VSS37 VSS38 156
DDRB_SDQ42 157 158 DDRB_SDQ46
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDRB_SDQ48 163 164 DDRB_SDQ52
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDRB_SDQS6# 169 170 DDRB_SDM6
<6> DDRB_SDQS6# DQS#6 DM6
DDRB_SDQS6 171 172
<6> DDRB_SDQS6 DQS6 VSS43
173 174 DDRB_SDQ54
DDRB_SDQ50 VSS44 DQ54 DDRB_SDQ55
175 DQ50 DQ55 176
DDRB_SDQ51 177 178
DQ51 VSS45 DDRB_SDQ60
179 VSS46 DQ60 180
DDRB_SDQ56 181 182 DDRB_SDQ61
DDRB_SDQ57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDRB_SDQS7#
VSS48 DQS#7 DDRB_SDQS7# <6>
DDRB_SDM7 187 188 DDRB_SDQS7
DM7 DQS7 DDRB_SDQS7 <6>
189 VSS49 VSS50 190
DDRB_SDQ58 191 192 DDRB_SDQ62
DDRB_SDQ59 DQ58 DQ62 DDRB_SDQ63
193 DQ59 DQ63 194
R86 10K_0402_5% 195 196
VSS51 VSS52 MEM_MB_EVENT#
1 2 197 SA0 EVENT# 198 MEM_MB_EVENT# <6>
+3VS 199 VDDSPD SDA 200 FCH_SDATA0 <10,14,32>
201 SA1 SCL 202 FCH_SCLK0 <10,14,32>
203 VTT1 VTT2 204 +0.75VS
1
4 R87 4
205 G1 G2 206
10K_0402_5% LCN_DAN06-K4806-0103
2
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/10/12 2013/10/12 Title
Reserve H:8mm Issued Date Deciphered Date
DDRIII SO-DIMM 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 01> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 11 of 51
A B C D E
A B C D E
C146 1 U2A
C146 place close to FCH 2 150P_0402_50V8J
HUDSON-2
APU_PCIE_RST#_C AE2 AF3
PLT_RST# PCIE_RST# PCICLK0
1 R89 2 33_0402_5% A_RST# AD5 AF1
PCI CLKS
A_RST# PCICLK1/GPO36 PCI_CLK1 <16>
PCICLK2/GPO37 AF5
C147 1 2 0.1U_0402_16V7K UMI_RXP0_C AE30 AG2
<5> UMI_RXP0 UMI_TX0P PCICLK3/GPO38 PCI_CLK3 <16>
C148 1 2 0.1U_0402_16V7K UMI_RXN0_C AE32 AF6
<5> UMI_RXN0 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 <16>
C149 1 2 0.1U_0402_16V7K UMI_RXP1_C AD33
<5> UMI_RXP1 UMI_TX1P
C150 1 2 0.1U_0402_16V7K UMI_RXN1_C AD31 AB5
<5> UMI_RXN1 UMI_TX1N PCIRST#
C151 1 2 0.1U_0402_16V7K UMI_RXP2_C AD28
<5> UMI_RXP2 UMI_TX2P +3VALW
C152 1 2 0.1U_0402_16V7K UMI_RXN2_C AD29
<5> UMI_RXN2 UMI_TX2N
C153 1 2 0.1U_0402_16V7K UMI_RXP3_C AC30 AJ3 C789 @
<5> UMI_RXP3 UMI_TX3P AD0/GPIO0
C154 1 2 0.1U_0402_16V7K UMI_RXN3_C AC32 AL5 APU_PCIE_RST #: Reset PCIE device on APU 1 2
1 <5> UMI_RXN3 UMI_TX3N AD1/GPIO1 1
AD2/GPIO2 AG4
AB33 AL6 0.1U_0402_16V4Z
<5> UMI_TXP0 UMI_RX0P AD3/GPIO3
5
AB31 AH3 MC74VHC1G08DFT2G SC70 5P
PCI EXPRESS INTERFACES
<5> UMI_TXN0 UMI_RX0N AD4/GPIO4
AB28 AJ5 @ R692 2 B
P
<5> UMI_TXP1 UMI_RX1P AD5/GPIO5
AB29 AL1 APU_PCIE_RST#_C 1 2 4
<5> UMI_TXN1 UMI_RX1N AD6/GPIO6 Y APU_PCIE_RST# <17,28,32>
Y33 AN5 33_0402_5% 1 A
<5> UMI_TXP2 UMI_RX2P AD7/GPIO7
G
Y31 AN6 U43
<5> UMI_TXN2 UMI_RX2N AD8/GPIO8
2
<5> UMI_TXP3 Y28 AJ1 1
3
UMI_RX3P AD9/GPIO9 @ @ @ R866
<5> UMI_TXN3 Y29 UMI_RX3N AD10/GPIO10 AL8
AL3 C790 R693 0_0402_5%
R94 PCIE_CALRP AD11/GPIO11 8.2K_0402_5%
1 2 590_0402_1% AF29 PCIE_CALRP AD12/GPIO12 AM7 150P_0402_50V8J
R88 2
+VDDAN_11_PCIE 1 2 2K_0402_1% PCIE_CALRN AF31 AJ6
1
PCIE_CALRN AD13/GPIO13
AD14/GPIO14 AK7
V33 AN8 @ R695
GPP_TX0P AD15/GPIO15 PLT_RST# <33>
V31 GPP_TX0N AD16/GPIO16 AG9 1 2
W30 AM11 0_0402_5%
GPP_TX1P AD17/GPIO17
W32 GPP_TX1N AD18/GPIO18 AJ10
AB26 GPP_TX2P AD19/GPIO19 AL12 R692/ C790 close to FCH
AB27 GPP_TX2N AD20/GPIO20 AK11
AA24 GPP_TX3P AD21/GPIO21 AN12
AA23 GPP_TX3N AD22/GPIO22 AG12
AD23/GPIO23 AE12 PCI_AD23 <16>
AA27 GPP_RX0P AD24/GPIO24 AC12 PCI_AD24 <16>
AA26 GPP_RX0N AD25/GPIO25 AE13 PCI_AD25 <16>
W27 GPP_RX1P AD26/GPIO26 AF13 PCI_AD26 <16>
V27 AH13
PCI INTERFACE
GPP_RX1N AD27/GPIO27 PCI_AD27 <16>
V26 GPP_RX2P AD28/GPIO28 AH14
W26 GPP_RX2N AD29/GPIO29 AD15
W24 GPP_RX3P AD30/GPIO30 AC15
W23 GPP_RX3N AD31/GPIO31 AE16
CBE0# AN3
CBE1# AJ8
2 2
CBE2# AN10
+1.1VS_CKVDD R95 1 2 2K_0402_1% CLK_CALRN F27 AD12
CLK_CALRN CBE3#
FRAME# AG10
DEVSEL# AK9
IRDY# AL10
G30 PCIE_RCLKP TRDY# AF10
G28 PCIE_RCLKN PAR AE10
STOP# AH1
<7> APU_DISP_CLK R26 DISP_CLKP PERR# AM9 Module design have reserve GPIO44,45 for
<7> APU_DISP_CLK# T26 DISP_CLKN SERR# AH8 VGA power enable and reset
REQ0# AG15
H33 DISP2_CLKP REQ1#/GPIO40 AG13
H31 DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 AF15
REQ3#/CLK_REQ5#/GPIO42 AM17 T14
<7> APU_CLK T24 APU_CLKP GNT0# AD16
<7> APU_CLK# T23 APU_CLKN GNT1#/GPO44 AD13
GNT2#/SD_LED/GPO45 AD21
R98 1 PX@ 2 0_0402_5% CLK_PCIE_VGA_R J30 AK17 T69
<17> CLK_PCIE_VGA SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46
R99 1 PX@ 2 0_0402_5% CLK_PCIE_VGA#_R K29 AD19
<17> CLK_PCIE_VGA# SLT_GFX_CLKN CLKRUN#
LOCK# AH9
H27 GPP_CLK0P
H28 GPP_CLK0N INTE#/GPIO32 AF18
INTF#/GPIO33 AE18
J27 GPP_CLK1P INTG#/GPIO34 AC16
K26 GPP_CLK1N INTH#/GPIO35 AD18
R102 1 2 0_0402_5% CLK_PCIE_WLAN_R
WLAN <32> CLK_PCIE_WLAN
R103 1 2 0_0402_5% CLK_PCIE_WLAN#_R
F33
F31
GPP_CLK2P
CLOCK GENERATOR
<32> CLK_PCIE_WLAN# GPP_CLK2N
B25 R891 1 2 0_0402_5%
LPCCLK0 CLK_PCI_EC <16,33>
R100 1 2 0_0402_5% CLK_PCIE_LAN_R E33 1 @ 2
<28> CLK_PCIE_LAN GPP_CLK3P CLK_PCI_DB <32>
R101 1 2 0_0402_5% CLK_PCIE_LAN#_R E31 D25 R670
LAN <28> CLK_PCIE_LAN# GPP_CLK3N LPCCLK1
D27
LPC_CLK1 <16>
0_0402_5%
3 LAD0 LPC_AD0 <32,33> 3
M23 GPP_CLK4P LAD1 C28 LPC_AD1 <32,33>
M24 GPP_CLK4N LAD2 A26 LPC_AD2 <32,33>
LAD3 A29 LPC_AD3 <32,33>
LPC
M27 GPP_CLK5P LFRAME# A31 LPC_FRAME# <32,33>
M26 GPP_CLK5N LDRQ0# B27
LDRQ1#/CLK_REQ6#/GPIO49 AE27
N25 GPP_CLK6P SERIRQ/GPIO48 AE19 SERIRQ <33>
N26 GPP_CLK6N
R23 GPP_CLK7P
R24 GPP_CLK7N DMA_ACTIVE# G25 ALLOW_STOP <7>
PROCHOT# E28 APU_PROCHOT#_R R15 1 @ 2 0_0402_5% APU_PROCHOT# <7>
N27 GPP_CLK8P APU_PG E26 APU_PWRGD <7,47>
R27 GPP_CLK8N LDT_STP# G26
APU
APU_RST# F26 APU_RST# <7>
R680 1 @ 2 22_0402_5% CLK_LAN_25M_R J26
<28> CLK_LAN_48M 14M_25M_48M_OSC
S5_CORE_EN H7
RTCCLK F1 RTC_CLK <16,33>
F3 +RTCBATT
INTRUDER_ALERT#
25M_X1 C31 E6 W=20mils 1 2
25M_X1 VDDBT_RTC_G R105 510_0402_5%
1U_0402_6.3V6K
32K_X1
S5 PLUS
32K_X1 G2 1
1
25M_X2 C33 C156 CLRP1 @
25M_X2 SHORT PADS
2
32K_X2 2
32K_X2 G4
25M_X1
21807-A13-HUDSON-M3_FCBGA656
25M_X2 1 2 C158 1 2 32K_X1
4 R106 1M_0402_5% for Clear CMOS 4
22P_0402_50V8J
1
3 OSC NC 4
2
2 1 R107 Y1
NC OSC 20M_0402_5% 32.768KHZ_12.5PF_CM31532768DZFT
Y4
2
1 25MHZ_20PF_FSX3M-25.M20FDO 1
C157 C155
C159 1 2 32K_X2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
22P_0402_50V8J
2
22P_0402_50V8J
2
22P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH PCIE/CLK/PCI/LPC/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA8611P 0.1
Date: Monday, November 07, 2011 Sheet 12 of 51
A B C D E
A B C D E
4MB SPI ROM
& Non-share ROM. SPI_CLK_FCH
1
+3VALW
R111
33_0402_5%
@
R112 1 2 SPI_WP#
2
3.3K_0402_5%
U2B
R108 1 2SPI_HOLD# +3VALW C160
1 HUDSON-2 3.3K_0402_5% 0.1U_0402_16V4Z 22P_0402_50V8J 1
AK19 AL14 C165 @
SATA_TX0P SD_CLK/SCLK_2/GPIO73
AM19 SATA_TX0N SD_CMD/SLOAD_2/GPIO74 AN14 1 2
AJ12 R115
SD_CD/GPIO75 0_0402_5% U4
AL20 SATA_RX0N SD_WP/GPIO76 AH12
AN20 AK13 SPI_SB_CS0#_R 1 2 SPI_SB_CS0# 1 8 R110
SATA_RX0P SD_DATA0/SDATI_2/GPIO77 CS# VCC
SD CARD
AM13 SPI_SO_R 1 2 SPI_SO_L 2 7 SPI_HOLD# 0_0402_5%
C161 1 SATA_FTX_C_DRX_P1 AN22 SD_DATA1/SDATO_2/GPIO78 SPI_WP# SO/SIO1 HOLD# SPI_CLK_FCH 1 SPI_CLK_FCH_R
<31> SATA_FTX_DRX_P1 2 0.01U_0402_16V7K SATA_TX1P SD_DATA2/GPIO79 AH15 3 WP# SCLK 6 2
C162 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_N1 AL22 AJ14 0_0402_5% 4 5 SPI_SI 1 2 SPI_SI_R
<31> SATA_FTX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80 GND SI/SIO0
HDD R117 0_0402_5%
AH20 AC4 MX25L3206EM2I-12G_SO8 R119
<31> SATA_FRX_C_DTX_N1 SATA_RX1N GBE_COL
<31> SATA_FRX_C_DTX_P1 AJ20 SATA_RX1P GBE_CRS AD3
GBE_MDCK AD9 SA00003K800 R110 place close to FCH
<31> SATA_FTX_C_DRX_P2 AJ22 SATA_TX2P GBE_MDIO W10
<31> SATA_FTX_C_DRX_N2 AH22 SATA_TX2N GBE_RXCLK AB8
+3VALW
ODD GBE_RXD3 AH7
<31> SATA_FRX_C_DTX_N2 AM23 SATA_RX2N GBE_RXD2 AF7
AK23 AE7 GBE_PHY_INTR R121 1 2 10K_0402_5%
<31> SATA_FRX_C_DTX_P2 SATA_RX2P GBE_RXD1
GBE_RXD0 AD7
AH24 SATA_TX3P GBE_RXCTL/RXDV AG8
AJ24 SATA_TX3N GBE_RXERR AD1
GBE_TXCLK AB7
AN24 AF9
GBE LAN
SATA_RX3N GBE_TXD3
AL24 SATA_RX3P GBE_TXD2 AG6
GBE_TXD1 AE8
AL26 SATA_TX4P GBE_TXD0 AD8
AN26 SATA_TX4N GBE_TXCTL/TXEN AB9
SERIAL ATA
GBE_PHY_PD AC2
AJ26 SATA_RX4N GBE_PHY_RST# AA7
AH26 W9 GBE_PHY_INTR
SATA_RX4P GBE_PHY_INTR
AN29 SATA_TX5P
2 SPI_SO_R 2
AL28 SATA_TX5N SPI_DI/GPIO164 V6
V5 SPI_SI_R
SPI_DO/GPIO163 SPI_CLK_FCH_R
AK27 SATA_RX5N SPI_CLK/GPIO162 V3
SPI ROM
AM27 T6 SPI_SB_CS0#_R
SATA_RX5P SPI_CS1#/GPIO165 SPI_WP#
ROM_RST#/SPI_WP#/GPIO161 V1
AL29 NC6
AN31 NC7
VGA_RED L30 DAC_RED <27>
AL31 R125 1 2 150_0402_1%
NC8
AL33 NC9
VGA_GREEN L32 DAC_GRN <27>
AH33 R126 1 2 150_0402_1%
NC10
AH31 NC11
VGA_BLUE M29 DAC_BLU <27>
AJ33 R127 1 2 150_0402_1%
NC12
AJ31
VGA DAC
NC13
VGA_HSYNC/GPO68 M28 CRT_HSYNC <27>
VGA_VSYNC/GPO69 N30 CRT_VSYNC <27>
VGA_DDC_SDA/GPO70 M33 CRT_DDC_DATA <27>
1K_0402_1% 2 1 R128 SATA_CALRP AF28 N32
SATA_CALRP VGA_DDC_SCL/GPO71 CRT_DDC_CLK <27>
+AVDD_SATA 931_0402_1% 2 1 R130 SATA_CALRN AF27 SATA_CALRN R131 1
VGA_DAC_RSET K31 2 715_0402_1%
+3VS 10K_0402_5% 1 2 R133 AD22 SATA_ACT#/GPIO67
AUX_VGA_CH_P V28 ML_VGA_AUXP_C <7>
VGA MAINLINK
AUX_VGA_CH_N V29 ML_VGA_AUXN_C <7>
AF21 SATA_X1
AUXCAL U28 AUXCAL R134 1 2 100_0402_1% +VDDAN_11_ML
ML_VGA_L0P T31 ML_VGA_TXP0 <7>
3 3
ML_VGA_L0N T33 ML_VGA_TXN0 <7>
AG21 SATA_X2 ML_VGA_L1P T29 ML_VGA_TXP1 <7>
ML_VGA_L1N T28 ML_VGA_TXN1 <7>
ML_VGA_L2P R32 ML_VGA_TXP2 <7>
ML_VGA_L2N R30 ML_VGA_TXN2 <7>
ML_VGA_L3P P29 ML_VGA_TXP3 <7>
P28 +FCH_VDDAN_33_DAC
ML_VGA_L3N ML_VGA_TXN3 <7>
2 1
10K_0402_5% R614
ML_VGA_HPD/GPIO229 C29 FCH_CRT_HPD <7>
T48 AH16 FANOUT0/GPIO52 VIN0/GPIO175 N2 1 2
AM15 R137 10K_0402_5%
FANOUT1/GPIO53 HW MONITOR
<31> BT_ON# AJ16 FANOUT2/GPIO54 VIN1/GPIO176 M3 1 2
R138 10K_0402_5%
AK15 L2 1 @ 2
<32> BT_DISABLE# FANIN0/GPIO56 VIN2/SDATI_1/GPIO177
AN16 R139 10K_0402_5%
<32> WL_OFF# FANIN1/GPIO57
AL16 N4 1 @ 2
FANIN2/GPIO58 VIN3/SDATO_1/GPIO178 R142 10K_0402_5%
P1 1 @ 2
VIN4/SLOAD_1/GPIO179 R143 10K_0402_5%
<31> ODD_EN K6 TEMPIN0/GPIO171
P3 1 @ 2
ODD_EN VIN5/SCLK_1/GPIO180 R145 10K_0402_5%
1 2
R888 10K_0402_5% 1 2 K5 M1 1 @ 2
R146 10K_0402_5% TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 R147 10K_0402_5%
no Zero Power ODD function, VIN7/GBE_LED3/GPIO182 M5 1 2
Thus, pull-down needs to be poped 1 2 K3 TEMPIN2/GPIO173
R148 10K_0402_5%
R149 10K_0402_5%
NC1 AG16
1 2 M6 TEMPIN3/TALERT#/GPIO174 NC2 AH10
R151 10K_0402_5% A28
NC3
4
G27 Need to enable internal 4
NC4
NC5 L4 pull down to leave
unconnected
21807-A13-HUDSON-M3_FCBGA656
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH SATA/SPI/VGA/HWM/SD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 13 of 51
A B C D E
A B C D E
U2D
PCIE_RST2 : Reset PCIE device on Hudson 3
HUDSON-2
T17
USB MISC
AB6 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC G8
<33> EC_LID_OUT# R2 RI#/GEVENT22#
W7 B9 USB_RCOMP R154 1 2 11.8K_0402_1%
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
<33> PM_SLP_S3# T3 SLP_S3#
<33> PM_SLP_S5# W2 SLP_S5# USB_FSD1P/GPIO186 H1
<33> PBTN_OUT# J4 PWR_BTN# USB_FSD1N H3
FCH_PWRGD N7
<33,47> FCH_PWRGD PWR_GOOD
H6
USB 1.1
TEST0 USB_FSD0P/GPIO185
ACPI / WAKE UP EVENTS
T9 TEST0 USB_FSD0N H5
TEST1 T10
1 TEST2 TEST1/TMS 1
V9 TEST2 USB_HSD13P H10
USB_HSD13N G10
<33> GATEA20 AE22 GA20IN/GEVENT0#
USB_HSD12P K10
<33> KBRST# AG19 KBRST#/GEVENT1# USB_HSD12N J12
<33> EC_SCI# R9 LPC_PME#/GEVENT3#
<33> EC_SMI#
CPPE#_R
C26
T5
LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
USB_HSD11P
USB_HSD11N
G12
F12
USB30_P11 <37>
USB30_N11 <37> LP2 Root
+3VALW R155 1 @ 2 10K_0402_5% SYS_RESET# U4 SYS_RESET#/GEVENT19#
<28,32> FCH_PCIE_WAKE# K1 WAKE#/GEVENT8# USB_HSD10P K12 USB30_P10 <37>
<7> H_THERMTRIP#
V7
R10
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
USB_HSD10N K13 USB30_N10 <37> LP1
WD_PWRGD AF19 B11
WD_PWRGD USB_HSD9P
USB_HSD9N D11
<33> EC_RSMRST# U2 RSMRST#
USB_HSD8P E10
AG24 CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N F10
<28> LAN_CLKREQ# AE24 CLK_REQ3#/SATA_IS1#/GPIO63
AE26 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P C10
AF22 CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N A10
Root
USB 2.0
AH17 SATA_IS4#/FANOUT3/GPIO55
AG18 H9 T74
SATA_IS5#/FANIN3/GPIO59 USB_HSD6P T75
<30> FCH_SPKR AF24 SPKR/GPIO66 USB_HSD6N G9
FCH_SCLK0
GPIO
<10,11,32> FCH_SCLK0 AD26 SCL0/GPIO43
CR
+3VALW For FCH internal debug use FCH_SDATA0 AD25 A8
<10,11,32> FCH_SDATA0 SDA0/GPIO47 USB_HSD5P USB20_P5 <35>
FCH_SCLK1 T7 C8
SCL1/GPIO227 USB_HSD5N USB20_N5 <35>
R179 1 @ 2 2.2K_0402_5% TEST0 FCH_SDATA1 R7 SDA1/GPIO228
R181 1 @ 2 2.2K_0402_5% TEST1
<32> WLAN_CLKREQ# AG25
AG22
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
USB_HSD4P
USB_HSD4N
F8
E8
USB20_P4 <31>
USB20_N4 <31>
BT
J2 IR_LED#/LLB#/GPIO184
2
R183 1 @ 2 2.2K_0402_5% TEST2
<17,19,46> VGA_PWRGD AG26
V8
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#/VGA_PD
USB_HSD3P
USB_HSD3N
C6
A6
USB20_P3 <25>
USB20_N3 <25>
CMOS 2
W8 GBE_LED0/GPIO183
Y6
V10
SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
USB_HSD2P
USB_HSD2N
C5
A5
USB20_P2 <32>
USB20_N2 <32>
WLAN Root
AA8 GBE_STAT0/GEVENT11#
<18> PEG_CLKREQ#
R156 2 @ 1 0_0402_5% PEG_CLKREQ#_R AF25 CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P
USB_HSD1N
C1
C3
USB20_P1 <35>
USB20_N1 <35>
RP2
+3VALW <31> ODD_DA#_FCH
USB_OC7# M7
R8
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_HSD0P
USB_HSD0N
E1
E3
USB20_P0 <36>
USB20_N0 <36>
RP1
USB_OC5#
USB OC
T1 USB_OC5#/IR_TX0/GEVENT17#
P6 C16 USBSS_CALRP R864 1 2 1K_0402_1%
<31> ODD_DETECT# USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP
USB_OC3# F5 A16 USBSS_CALRN R865 1 2 1K_0402_1% +FCH_VDD_11_SSUSB_S
R883 @ USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN
1 2 10K_0402_5% USB_OC7#
<35> USB_OC2#
USB_OC2# P5 USB_OC2#/TCK/GEVENT14#
USB_OC1# J7 A14
<36> USB_OC1# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P
R624 1 2 10K_0402_5% USB_OC2# USB_OC0# T8 C14
<37> USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
R625 1 2 10K_0402_5% USB_OC1# C12
USB_SS_RX3P
USB_SS_RX3N A12
R174 1 2 10K_0402_5% USB_OC0#
R159 1 2 33_0402_5% HDA_BITCLK AB3 D15
<30> HDA_BITCLK_AUDIO AZ_BITCLK USB_SS_TX2P
R618 1 @ 2 10K_0402_5% ODD_DA#_FCH R160 1 2 33_0402_5% HDA_SDOUT AB1 B15
<30> HDA_SDOUT_AUDIO AZ_SDOUT USB_SS_TX2N
HDA_SDIN0
HD AUDIO
<30> HDA_SDIN0 AA2 AZ_SDIN0/GPIO167
R649 1 @ 2 10K_0402_5% ODD_DETECT# Y5 E14
AZ_SDIN1/GPIO168 USB_SS_RX2P
USB 3.0
Y3 AZ_SDIN2/GPIO169 USB_SS_RX2N F14
Y1 AZ_SDIN3/GPIO170
R620 1 @ 2 10K_0402_5% USB_OC5# R161 1 2 33_0402_5% HDA_SYNC AD6 F15 USB30_FTX_DRX_P1
<30> HDA_SYNC_AUDIO AZ_SYNC USB_SS_TX1P USB30_FTX_DRX_P1 <37>
R162 1 2 33_0402_5% HDA_RST# AE4 G15 USB30_FTX_DRX_N1
<30> HDA_RST_AUDIO# AZ_RST# USB_SS_TX1N USB30_FTX_DRX_N1 <37>
R163 1 @ 2 10K_0402_5% USB_OC3#
USB_SS_RX1P H13 USB30_FRX_DTX_P1
USB30_FRX_DTX_P1 <37>
LP2
R164 1 @ 2 10K_0402_5% H_THERMTRIP# G13 USB30_FRX_DTX_N1
USB_SS_RX1N USB30_FRX_DTX_N1 <37>
R169 1 @ 2 100K_0402_5% EC_LID_OUT# T61 K19 J16 USB30_FTX_DRX_P0
3 PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB30_FTX_DRX_P0 <37> 3
T19 J19 H16 USB30_FTX_DRX_N0
PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB30_FTX_DRX_N0 <37>
R170 1 @ 2 10K_0402_5% FCH_PCIE_WAKE# J21 SPI_CS2#/GBE_STAT2/GPIO166
USB_SS_RX0P J15 USB30_FRX_DTX_P0
USB30_FRX_DTX_P0 <37>
LP1
K15 USB30_FRX_DTX_N0
USB_SS_RX0N USB30_FRX_DTX_N0 <37>
GPIO189 D21
GPIO190 PS2KB_DAT/GPIO189 R165 10K_0402_5%
C20 PS2KB_CLK/GPIO190 SCL2/GPIO193 H19 1 2
+3VS 0_0402_5% 2 PX@ 1 R96 D23 G19 R167 1 2 10K_0402_5%
<17> PXS_RST# PS2M_DAT/GPIO191 EMBEDDED CTRL SDA2/GPIO194
0_0402_5% 2 PX@ 1 R97 C22 G22 R227 1 2 10K_0402_5%
<19,43,46> PXS_PWREN PS2M_CLK/GPIO192 SCL3_LV/GPIO195
R896 1 2 10K_0402_5% CPPE#_R G21 R228 1 2 10K_0402_5%
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197 E22
R171 1 2 2.2K_0402_5% FCH_SCLK0 H22
EC_PWM1/EC_TIMER1/GPIO198
D F21 KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 J22 EC_PWM2
EC_PWM2 <16> strap pin
1
R172 1 2 2.2K_0402_5% FCH_SDATA0 E20 H21
PX@ KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
<33> VGA_GATE# 2 F20 KSO_2/GPIO211
R175 1 2 10K_0402_5% WD_PWRGD G Q112 A22 K21
KSO_3/GPIO212 KSI_0/GPIO201
S 2N7002K_SOT23-3 E18 K22
3
R173 KSO_4/GPIO213 KSI_1/GPIO202
1 2 8.2K_0402_5% WLAN_CLKREQ# A20 KSO_5/GPIO214 KSI_2/GPIO203 F22
J18 KSO_6/GPIO215 KSI_3/GPIO204 F24
R176 1 2 8.2K_0402_5% LAN_CLKREQ# H18 E24
KSO_7/GPIO216 KSI_4/GPIO205
G18 KSO_8/GPIO217 KSI_5/GPIO206 B23
B21 KSO_9/GPIO218 KSI_6/GPIO207 C24
K18 KSO_10/GPIO219 KSI_7/GPIO208 F18
+3VALW +3VALW D19 KSO_11/GPIO220
A18 KSO_12/GPIO221
C18 KSO_13/GPIO222
B19 KSO_14/GPIO223
2 UMA@ 1
2 UMA@ 1
10K_0402_5%
10K_0402_5%
B17 KSO_15/GPIO224
A24 KSO_16/GPIO225
R685
R684
D17 KSO_17/GPIO226
4 4
21807-A13-HUDSON-M3_FCBGA656
R166 1 2 10K_0402_5% FCH_SCLK1 GPIO189
GPIO190
R168 1 2 10K_0402_5% FCH_SDATA1 BOARD
Config. GPIO189 GPIO190 Function
R177 1 2 2.2K_0402_5% EC_RSMRST#
PX@ 1
PX@ 1
10K_0402_5%
10K_0402_5%
0 0 PX4 Security Classification Compal Secret Data Compal Electronics, Inc.
R178 1 @ 2 10K_0402_5% HDA_BITCLK
R682
R683
0 1 Reserved Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
R180 1 @ 2 10K_0402_5% HDA_SDIN0
1 0 DIS FCH-ACPI/USB/HDA/GPIO
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R182 1 PX@ 2 10K_0402_5% PEG_CLKREQ#_R AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 1 UMA Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 14 of 51
A B C D E
A B C D E
+3VS +1.1VS
L4 U2C
1007mA
1 2 +VDDPL_33_SYS +VCC_VDDCR_11 1 2
MBK1608221YZF_2P 102mA HUDSON-2 R184 0_0805_5%
C181
2.2U_0402_6.3V6M
C182
0.1U_0402_16V7K
C183
0.1U_0402_16V7K
C184
0.1U_0402_16V7K
C185
1U_0402_6.3V6K
C186
1U_0402_6.3V6K
C177
10U_0603_6.3V6M
220 ohm +3VS 1 2 +VDDIO_33_PCIGP AB17 T14
VDDIO_33_PCIGP_1 VDDCR_11_1
22U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 R185 0_0603_5% AB18 T17 1 1 1 1 1
VDDIO_33_PCIGP_2 VDDCR_11_2
C176
C178
C187
C179
PCI/GPIO I/O
AE9 VDDIO_33_PCIGP_3 VDDCR_11_3 T20
1 1 1 1 AD10 VDDIO_33_PCIGP_4 VDDCR_11_4 U16
AG7 VDDIO_33_PCIGP_5 VDDCR_11_5 U18
2 2 2 2 2 2 2
AC13 VDDIO_33_PCIGP_6 VDDCR_11_6 V14
CORE S0
AB12 VDDIO_33_PCIGP_7 VDDCR_11_7 V17
2 2 2 2
AB13 VDDIO_33_PCIGP_8 VDDCR_11_8 V20
+FCH_VDDAN_33_DAC AB14 Y17
1 VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS 1
AB16 VDDIO_33_PCIGP_10
47mA 340mA 42ohm @ 100MHz
1 2 +VDDPL_33_MLDAC +VDDPL_33_SYS H24 H26 +1.1VS_CKVDD 1 2
R186 0_0402_5% VDDPL_33_SYS VDDAN_11_CLK_1 R187 0_0603_5%
20mA VDDAN_11_CLK_2 J25
C189
0.1U_0402_16V7K
C190
0.1U_0402_16V7K
C191
1U_0402_6.3V6K
C192
1U_0402_6.3V6K
C193
22U_0603_6.3V6M
R1881 2 0_0402_5% +VDDPL_33_DAC
0.1U_0402_16V7K
0.1U_0402_16V7K
CLKGEN I/O
+VDDPL_33_MLDAC V22 VDDPL_33_DAC VDDAN_11_CLK_3 K24
C180
C188
12mA VDDAN_11_CLK_4 L22 1 1 1 1 1
1 1 R1891 2 0_0402_5% +VDDPL_33_ML U22 M22
VDDPL_33_ML VDDAN_11_CLK_5
30mA VDDAN_11_CLK_6 N21
+FCH_VDDAN_33_DAC T22 N22
VDDAN_33_DAC VDDAN_11_CLK_7 2 2 2 2 2
2 2
VDDPL_33_SSUSB_S 11mA VDDAN_11_CLK_8 P22
+VDDPL_33_SSUSB_S L18
For Hudson3 USB3.0 only VDDPL_33_SSUSB_S
14mA
For Hudson2, connect to GND +VDDPL_33_USB_S D7 1088mA +1.1VS
VDDPL_33_USB_S +VDDAN_11_PCIE 42ohm @ 100MHz
11mA VDDAN_11_PCIE_1 AB24
+VDDPL_33_PCIE AH29 Y21 +VDDAN_11_PCIE 1 2
VDDPL_33_PCIE VDDAN_11_PCIE_2 R191 0_0805_5%
12mA AE25
PCI EXPRESS
VDDAN_11_PCIE_3
C195
0.1U_0402_16V7K
C196
1U_0402_6.3V6K
C197
22U_0603_6.3V6M
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA AG28 AD24
VDDPL_33_SATA VDDAN_11_PCIE_4
supply for the RGB outputs VDDAN_11_PCIE_5 AB23 1 1 1
@ AA22
VDDAN_11_PCIE_6
1 2 M31 LDO_CAP VDDAN_11_PCIE_7 AF26
C194 2.2U_0603_6.3V4Z AG27
+1.1VS L5 VDDAN_11_PCIE_8 2 2 2
7mA
1 2 R192 1 2 0_0402_5% +VDDPL_11_DAC V21
MBK1608221YZF_2P VDDPL_11_DAC +1.1VS
1337mA
220 ohm/2A +VDDAN_11_ML AA21 +AVDD_SATA 42ohm @ 100MHz
R193 1 VDDAN_11_SATA_1
2 0_0603_5% 226mA VDDAN_11_SATA_4 Y20 1 2
+3VS +FCH_VDDAN_33_DAC Y22 AB21 R194 0_0805_5%
VDDAN_11_ML_1 VDDAN_11_SATA_2
C199
4.7U_0402_6.3V6M
C201
0.1U_0402_16V7K
C202
0.1U_0402_16V7K
C203
0.1U_0402_16V7K
C204
1U_0402_6.3V6K
C205
1U_0402_6.3V6K
C206
22U_0603_6.3V6M
L2 30mil
SERIAL ATA
V23 AB22
MAIN LINK
VDDAN_11_ML_2 VDDAN_11_SATA_3
1 2 1 1 1 V24 VDDAN_11_ML_3 VDDAN_11_SATA_5 AC22 1 1 1 1
FBMA-L11-201209-221LMA30T_0805 V25 AC21
VDDAN_11_ML_4 VDDAN_11_SATA_6
C166
2.2U_0603_6.3V4Z
C167
0.1U_0402_16V4Z
220 ohm VDDAN_11_SATA_7 AA20
1 1 VDDAN_11_SATA_8 AA18
2 2 2 2 2 2 2 2 2
VDDAN_11_SATA_9 AB20
VDDAN_11_SATA_10 AC19
AB10 +3VALW
2 2 VDDIO_33_GBE_S
59mA
AB11 N18 +VDDIO_33_S 1 2
VDDCR_11_GBE_S_1 VDDIO_33_S_1 R195 0_0402_5%
AA11 L19
GBE LAN
VDDCR_11_GBE_S_2 VDDIO_33_S_2
C207
1U_0402_6.3V6K
C208
1U_0402_6.3V6K
C209
2.2U_0402_6.3V6M
VDDIO_33_S_3 M18
1 2 AA9 V12 1 1 1
3.3V_S5 I/O
R196 0_0402_5% VDDIO_GBE_S_1 VDDIO_33_S_4
AA10 VDDIO_GBE_S_2 VDDIO_33_S_5 V13
+3VALW Y12
L8 VDDIO_33_S_6
470mA VDDIO_33_S_7 Y13
2 2 2
1 2 +VDDAN_33_USB G7 W11
VDDAN_33_USB_S_1 VDDIO_33_S_8
10U_0603_6.3V6M
10U_0603_6.3V6M
FBMA-L11-201209-221LMA30T_0805 H8 VDDAN_33_USB_S_2
+3VALW +3VALW +VDDXL_3.3V
C212
C213
C214
1U_0402_6.3V6K
C215
1U_0402_6.3V6K
C216
0.1U_0402_16V7K
220 ohm/2A J8 VDDAN_33_USB_S_3
L6 1 1 1 1 1 K8 VDDAN_33_USB_S_4 5mA L9 Tie to +3.3V_S5 rail if USB3 Wake
1 2+VDDPL_33_SSUSB_S K9 VDDAN_33_USB_S_5 VDDXL_33_S G24 +VDDXL_3.3V 1 2 is supported; otherwise, tie to
MBK1608221YZF_2P M9 MBK1608221YZF_2P
VDDAN_33_USB_S_6 +3.3V_S0 rail.
C198
2.2U_0402_6.3V6M
C200
0.1U_0402_16V7K
C217
2.2U_0402_6.3V6M
2 2 2 2 2
M10 VDDAN_33_USB_S_7 220 ohm Hudson-2 designs: Tie to +3.3V_S0
220 ohm 1 1 N9 VDDAN_33_USB_S_8 1
N10 rail.
VDDAN_33_USB_S_9
M12 VDDAN_33_USB_S_10
N12 VDDAN_33_USB_S_11
2 2 2
M11 VDDAN_33_USB_S_12
+1.1VALW
L11 140mA +1.1VALW
1 2 +VDDAN_11_USB_S U12 187mA
USB
MBK1608221YZF_2P VDDAN_11_USB_S_1 +VDDCR_1.1V
U13 VDDAN_11_USB_S_2 VDDCR_11_S_1 N20 1 2
C219
2.2U_0402_6.3V6M
C220
0.1U_0402_16V7K
220 ohm M20 R197 0_0603_5%
+VDDAN_33_USB VDDCR_11_S_2
C221
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
1 1
L7 1 1
1 2 +VDDPL_33_USB_S
MBK1608221YZF_2P
2 2
C210
2.2U_0402_6.3V6M
C211
0.1U_0402_16V7K
3 3
220 ohm 2 2
1 1
+1.1VALW
L13 42mA +1.1VALW
2 2 +VDDCR_11V_USB L14
1 2 T12 VDDCR_11_USB_S_1 70mA
MBK1608221YZF_2P T13 J24 +VDDPL_11_SYS_S 1 2
VDDCR_11_USB_S_2 VDDPL_11_SYS_S
C223
10U_0603_6.3V6M
C224
0.1U_0402_16V7K
C225
0.1U_0402_16V7K
220 ohm MBK1608221YZF_2P
0.1U_0402_16V7K
C226
2.2U_0402_6.3V6M
C228
1 1 1 220 ohm
1 1
+3VS
L10 2 2 2
+VDDPL_33_PCIE 2 2
1 2
MBK1608221YZF_2P
220 ohm +3VALW
+FCH_VDD_11_SSUSB_S
C218
2.2U_0402_6.3V6M
282mA 12mA
1 P16 M8 +VDDAN_33_HWM 1 2
+VDDAN_11_SSUSB VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S
40mils 1 R199 2 M14 VDDAN_11_SSUSB_S_2
R198 0_0402_5% AMD reply:
C232
2.2U_0402_6.3V6M
C233
0.1U_0402_16V7K
0_0603_5% N14 VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3
C229
1U_0402_6.3V6K
C230
0.1U_0402_16V7K
C231
0.1U_0402_16V7K
P13 1 1 it to +3.3V_S5 directly if HWM is not used.
2 VDDAN_11_SSUSB_S_4
1 1 1 P14 VDDAN_11_SSUSB_S_5
USB SS
@ @
2 2
2 2 2
424mA
N16 VDDCR_11_SSUSB_S_1
+3VS N17 +3VS
L12 VDDCR_11_SSUSB_S_2
P17 VDDCR_11_SSUSB_S_3 26mA
1 2 +VDDPL_33_SATA M17 AA4 +VDDIO_AZ 1 2 VDDIO_AZ_S should be tied to
MBK1608221YZF_2P VDDCR_11_SSUSB_S_4 VDDIO_AZ_S R200 0_0402_5% +3.3/1.5V_S5 rail if Wake on Ring
POWER
C227
2.2U_0402_6.3V6M
220 ohm C236 1 2 2.2U_0402_6.3V6M is supported
1
4 L15 4
+1.1VALW 2 1 1 R201 2 +VDDCR_11_SSUSB 21807-A13-HUDSON-M3_FCBGA656
0_0603_5%
C237
10U_0603_6.3V6M
C238
1U_0402_6.3V6K
C239
0.1U_0402_16V7K
C240
0.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_0805
2
42 ohm/4A 1 1 1 1
2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 15 of 51
A B C D E
5 4 3 2 1
DEBUG STRAPS
U2E
HUDSON-2
STRAP PINS FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
A3 VSS VSS T25
A33 VSS VSS T27
B7 VSS VSS U6 PCI_CLK1 PCI_CLK3 PCI_CLK4 CLK_PCI_EC LPC_CLK1 EC_PWM2 RTC_CLK PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
B13 VSS VSS U14
D9 VSS VSS U17
D D
D13 VSS VSS U20 PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI
E5 VSS VSS U21
HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE PULL PLL ILA PLL PCIE STRAPS MEM BOOT
E12 U30
E16
VSS VSS
U32 STRAPS DISABLED HIGH AUTORUN
VSS VSS DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
E29 VSS VSS V11
F7 VSS VSS V16
F9 VSS VSS V18
F11 VSS VSS W4 PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI
F13 W6 PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
F16
VSS VSS
W25
LOW LOW
VSS VSS STRAP MODE ENABLED AUTORUN
F17 VSS VSS W28
F19 Y14 DEFAULT DEFAULT DEFAULT DEFAULT
VSS VSS
F23 VSS VSS Y16
F25 VSS VSS Y18
F29 VSS VSS AA6
G6 VSS VSS AA12
G16 AA13 +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW
VSS VSS
G32 VSS VSS AA14
R202 10K_0402_5%
R203 10K_0402_5%
R204 10K_0402_5%
R205 10K_0402_5%
R206 10K_0402_5%
R207 10K_0402_5%
R208 10K_0402_5%
H12 VSS VSS AA16
H15 VSS VSS AA17
1
GROUND
H29 VSS VSS AA25
J6 VSS VSS AA28
J9 AA30 @ @ @ @
VSS VSS <12> PCI_AD27
C J10 VSS VSS AA32 C
J13 AB25 <12> PCI_AD26
2
VSS VSS
J28 VSS VSS AC6
J32 VSS VSS AC18 <12> PCI_AD25
K7 VSS VSS AC28 <12> PCI_CLK1
K16 VSS VSS AD27 <12> PCI_AD24
K27 VSS VSS AE6 <12> PCI_CLK3
K28 VSS VSS AE15 <12> PCI_AD23
L6 VSS VSS AE21 <12> PCI_CLK4
L12 VSS VSS AE28
L13 VSS VSS AF8 <12,33> CLK_PCI_EC
R209 2.2K_0402_5%
R210 2.2K_0402_5%
R211 2.2K_0402_5%
R212 2.2K_0402_5%
R213 2.2K_0402_5%
L15 VSS VSS AF12
1
L16 VSS VSS AF16 <12> LPC_CLK1
L21 VSS VSS AF33
M13 AG30 @ @ @ @ @
VSS VSS <14> EC_PWM2
M16 VSS VSS AG32
M21 AH5 <12,33> RTC_CLK
2
VSS VSS
M25 VSS VSS AH11 R214 10K_0402_5%
R215 10K_0402_5%
R216 10K_0402_5%
R217 10K_0402_5%
R218 10K_0402_5%
R219 2.2K_0402_5%
R220 2.2K_0402_5%
N6 VSS VSS AH18
N11 VSS VSS AH19
1
1
N13 VSS VSS AH21
N23 VSS VSS AH23
N24 AH25 @ @ @
VSS VSS
P12 VSS VSS AH27
B P18 AJ18 B
2
2
VSS VSS
P20 VSS VSS AJ28
P21 VSS VSS AJ29
P31 VSS VSS AK21
P33 VSS VSS AK25
R4 VSS VSS AL18
R11 VSS VSS AM21
R25 VSS VSS AM25
R28 VSS VSS AN1
T11 VSS VSS AN18
T16 VSS VSS AN28
T18 VSS VSS AN33
N8 VSSAN_HWM VSSPL_DAC T21
VSSAN_DAC L28
K25 VSSXL VSSANQ_DAC K33
VSSIO_DAC N28
H25 VSSPL_SYS
EFUSE R6
21807-A13-HUDSON-M3_FCBGA656
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH-VSS/Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 16 of 51
5 4 3 2 1
5 4 3 2 1
PCIE_CTX_GRX_P[15..0] U6A PX@ PCIE_CRX_GTX_P[15..0]
<5> PCIE_CTX_GRX_P[15..0] PCIE_CRX_GTX_P[15..0] <5>
PCIE_CTX_GRX_N[15..0] PCIE_CRX_GTX_N[15..0]
<5> PCIE_CTX_GRX_N[15..0] PCIE_CRX_GTX_N[15..0] <5>
LVDS Interface
PCIE_CTX_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 0.1U_0402_16V7K 2 1 C241 PX@ PCIE_CRX_GTX_P0
PCIE_CTX_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_CRX_C_GTX_N0 0.1U_0402_16V7K
Y37 PCIE_RX0N PCIE_TX0N Y32 2 1 C242 PX@ PCIE_CRX_GTX_N0 U6G PX@
D D
PCIE_CTX_GRX_P1 Y35 PCIE_RX1P PCIE_TX1P W33 PCIE_CRX_C_GTX_P1 0.1U_0402_16V7K 2 1 C243 PX@ PCIE_CRX_GTX_P1
PCIE_CTX_GRX_N1 W36 W32 PCIE_CRX_C_GTX_N1 0.1U_0402_16V7K 2 1 C244 PX@ PCIE_CRX_GTX_N1 LVDS CONTROL AK27
PCIE_RX1N PCIE_TX1N VARY_BL
DIGON AJ27
PCIE_CTX_GRX_P2 W38 PCIE_RX2P PCIE_TX2P U33 PCIE_CRX_C_GTX_P2 0.1U_0402_16V7K 2 1 C245 PX@ PCIE_CRX_GTX_P2
PCIE_CTX_GRX_N2 V37 U32 PCIE_CRX_C_GTX_N2 0.1U_0402_16V7K 2 1 C246 PX@ PCIE_CRX_GTX_N2
PCIE_RX2N PCIE_TX2N
TXCLK_UP_DPF3P AK35
PCIE_CTX_GRX_P3 V35 PCIE_RX3P PCIE_TX3P U30 PCIE_CRX_C_GTX_P3 0.1U_0402_16V7K 2 1 C247 PX@ PCIE_CRX_GTX_P3
TXCLK_UN_DPF3N AL36
PCIE_CTX_GRX_N3 U36 U29 PCIE_CRX_C_GTX_N3 0.1U_0402_16V7K 2 1 C248 PX@ PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N
TXOUT_U0P_DPF2P AJ38
TXOUT_U0N_DPF2N AK37
PCIE_CTX_GRX_P4 U38 PCIE_RX4P PCIE_TX4P T33 PCIE_CRX_C_GTX_P4 0.1U_0402_16V7K 2 1 C250 PX@ PCIE_CRX_GTX_P4
PCIE_CTX_GRX_N4 T37 T32 PCIE_CRX_C_GTX_N4 0.1U_0402_16V7K 2 1 C251 PX@ PCIE_CRX_GTX_N4 AH35
PCIE_RX4N PCIE_TX4N TXOUT_U1P_DPF1P
PCI EXPRESS INTERFACE
TXOUT_U1N_DPF1N AJ36
PCIE_CTX_GRX_P5 T35 PCIE_RX5P PCIE_TX5P T30 PCIE_CRX_C_GTX_P5 0.1U_0402_16V7K 2 1 C249 PX@ PCIE_CRX_GTX_P5
TXOUT_U2P_DPF0P AG38
PCIE_CTX_GRX_N5 R36 T29 PCIE_CRX_C_GTX_N5 0.1U_0402_16V7K 2 1 C252 PX@ PCIE_CRX_GTX_N5 AH37
PCIE_RX5N PCIE_TX5N TXOUT_U2N_DPF0N
TXOUT_U3P AF35
PCIE_CTX_GRX_P6 R38 PCIE_RX6P PCIE_TX6P P33 PCIE_CRX_C_GTX_P6 0.1U_0402_16V7K 2 1 C253 PX@ PCIE_CRX_GTX_P6
TXOUT_U3N AG36
PCIE_CTX_GRX_N6 P37 P32 PCIE_CRX_C_GTX_N6 0.1U_0402_16V7K 2 1 C254 PX@ PCIE_CRX_GTX_N6
PCIE_RX6N PCIE_TX6N
C C
LVTMDP
PCIE_CTX_GRX_P7 P35 PCIE_RX7P PCIE_TX7P P30 PCIE_CRX_C_GTX_P7 0.1U_0402_16V7K 2 1 C255 PX@ PCIE_CRX_GTX_P7
PCIE_CTX_GRX_N7 N36 P29 PCIE_CRX_C_GTX_N7 0.1U_0402_16V7K 2 1 C256 PX@ PCIE_CRX_GTX_N7 AP34
PCIE_RX7N PCIE_TX7N TXCLK_LP_DPE3P
TXCLK_LN_DPE3N AR34
PCIE_CTX_GRX_P8 N38 PCIE_RX8P PCIE_TX8P N33 PCIE_CRX_C_GTX_P8 0.1U_0402_16V7K 2 1 C257 PX@ PCIE_CRX_GTX_P8
TXOUT_L0P_DPE2P AW37
PCIE_CTX_GRX_N8 M37 N32 PCIE_CRX_C_GTX_N8 0.1U_0402_16V7K 2 1 C258 PX@ PCIE_CRX_GTX_N8 AU35
PCIE_RX8N PCIE_TX8N TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P AR37
PCIE_CTX_GRX_P9 M35 PCIE_RX9P PCIE_TX9P N30 PCIE_CRX_C_GTX_P9 0.1U_0402_16V7K 2 1 C259 PX@ PCIE_CRX_GTX_P9
TXOUT_L1N_DPE1N AU39
PCIE_CTX_GRX_N9 L36 N29 PCIE_CRX_C_GTX_N9 0.1U_0402_16V7K 2 1 C260 PX@ PCIE_CRX_GTX_N9
PCIE_RX9N PCIE_TX9N
TXOUT_L2P_DPE0P AP35
TXOUT_L2N_DPE0N AR35
PCIE_CTX_GRX_P10 L38 PCIE_RX10P PCIE_TX10P L33 PCIE_CRX_C_GTX_P10 0.1U_0402_16V7K 2 1 C261 PX@ PCIE_CRX_GTX_P10
PCIE_CTX_GRX_N10 K37 L32 PCIE_CRX_C_GTX_N10 0.1U_0402_16V7K 2 1 C262 PX@ PCIE_CRX_GTX_N10 AN36
PCIE_RX10N PCIE_TX10N TXOUT_L3P
TXOUT_L3N AP37
PCIE_CTX_GRX_P11 K35 PCIE_RX11P PCIE_TX11P L30 PCIE_CRX_C_GTX_P11 0.1U_0402_16V7K 2 1 C263 PX@ PCIE_CRX_GTX_P11
PCIE_CTX_GRX_N11 J36 L29 PCIE_CRX_C_GTX_N11 0.1U_0402_16V7K 2 1 C264 PX@ PCIE_CRX_GTX_N11
PCIE_RX11N PCIE_TX11N
PCIE_CTX_GRX_P12 J38 PCIE_RX12P PCIE_TX12P K33 PCIE_CRX_C_GTX_P12 0.1U_0402_16V7K 2 1 C265 PX@ PCIE_CRX_GTX_P12 Seymour M2
PCIE_CTX_GRX_N12 H37 K32 PCIE_CRX_C_GTX_N12 0.1U_0402_16V7K 2 1 C266 PX@ PCIE_CRX_GTX_N12
PCIE_RX12N PCIE_TX12N
B B
PCIE_CTX_GRX_P13 H35 PCIE_RX13P PCIE_TX13P J33 PCIE_CRX_C_GTX_P13 0.1U_0402_16V7K 2 1 C267 PX@ PCIE_CRX_GTX_P13
PCIE_CTX_GRX_N13 G36 J32 PCIE_CRX_C_GTX_N13 0.1U_0402_16V7K 2 1 C268 PX@ PCIE_CRX_GTX_N13
PCIE_RX13N PCIE_TX13N
PCIE_CTX_GRX_P14 G38 PCIE_RX14P PCIE_TX14P K30 PCIE_CRX_C_GTX_P14 0.1U_0402_16V7K 2 1 C269 PX@ PCIE_CRX_GTX_P14
PCIE_CTX_GRX_N14 F37 K29 PCIE_CRX_C_GTX_N14 0.1U_0402_16V7K 2 1 C270 PX@ PCIE_CRX_GTX_N14
PCIE_RX14N PCIE_TX14N R221 2 @ 1 0_0402_5%
PCIE_CTX_GRX_P15 F35 PCIE_RX15P PCIE_TX15P H33 PCIE_CRX_C_GTX_P15 0.1U_0402_16V7K 2 1 C271 PX@ PCIE_CRX_GTX_P15
PCIE_CTX_GRX_N15 E37 H32 PCIE_CRX_C_GTX_N15 0.1U_0402_16V7K 2 1 C272 PX@ PCIE_CRX_GTX_N15 +3VGS
PCIE_RX15N PCIE_TX15N
5
CLOCK U7
CLK_PCIE_VGA AB35 2
P
<12> CLK_PCIE_VGA PCIE_REFCLKP <14> PXS_RST# B
CLK_PCIE_VGA# AA36 4 GPU_RST#
<12> CLK_PCIE_VGA# PCIE_REFCLKN Y
<12,28,32> APU_PCIE_RST# 1 A
G
R222 0_0402_5%
2 @ 1 CALIBRATION PX@
<14,19,46> VGA_PWRGD
3
Y30 1.27K_0402_1% 1 PX@ 2 R223 MC74VHC1G08DFT2G SC70 5P
PCIE_CALRP
R224 2 PX@ 1 AH16 Y29 2K_0402_1% 1 PX@ 2 R225 +1.0VGS
A 10K_0402_5% PWRGOOD PCIE_CALRN A
GPU_RST# AA30 PERSTB
Security Classification Compal Secret Data Compal Electronics, Inc.
1
PX@ 2011/10/12 2013/10/12 Title
R226 Seymour M2
Issued Date Deciphered Date
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_SeymourXT_M2_PCIE/LVDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 17 of 51
5 4 3 2 1
5 4 3 2 1
U6B CONFIGURATION STRAPS RECOMMENDED SETTINGS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
TXCAP_DPA3P AU24 NA = NOT APPLICABLE
TXCAM_DPA3N AV23
AT25 RECOMMENDED
MUTI GFX TX0P_DPA2P STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
AR24 SETTINGS
DPA TX0M_DPA2N
AU26 0: 50% swing
TX1P_DPA1P TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 1: Full swing X
TX1M_DPA1N AV25
AR8 AT27 0: disable
DVPCNTL_MVP_0 TX2P_DPA0P TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS 1: enable X
AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26
AP8 DVPCNTL_0
AW8 AR30 Advertises PCIE speed 0: 2.5GT/s
D DVPCNTL_1 TXCBP_DPB3P RSVD GPIO2 when compliance test 1: 5GT/s 0 D
AR3 DVPCNTL_2 TXCBM_DPB3N AT29
AR1 DVPCLK
<22> VRAM_ID0 AU1 DVPDATA_0 TX3P_DPB2P AV31
AU3 AU30 RSVD GPIO8 RESERVED 0
<22> VRAM_ID1 DVPDATA_1 DPB TX3M_DPB2N
<22> VRAM_ID2 AW3 DVPDATA_2
AP6 DVPDATA_3 TX4P_DPB1P AR32
AW5 AT31 BIF_VGA DIS GPIO9 VGA ENABLED 0
DVPDATA_4 TX4M_DPB1N
AU5 DVPDATA_5
AR6 DVPDATA_6 TX5P_DPB0P AT33
AW6 AU32 RSVD GPIO21 RESERVED 0
DVPDATA_7 TX5M_DPB0N
AU6 DVPDATA_8
AT7 AU14 0: disable
DVPDATA_9 TXCCP_DPC3P BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 1: enable X
AV7 DVPDATA_10 TXCCM_DPC3N AV13
AN7 DVPDATA_11
AV9 DVPDATA_12 TX0P_DPC2P AT15
AT9 AR14 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XXX
DVPDATA_13 TX0M_DPC2N
AR10 DVPDATA_14
AW10 DPC AU16
DVPDATA_15 TX1P_DPC1P VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
AU10 DVPDATA_16 TX1M_DPC1N AV15
AP10 DVPDATA_17
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 AR16 RSVD H2SYNC 0
DVPDATA_19 TX2M_DPC0N
AR12 DVPDATA_20
AW12 DVPDATA_21 TXCDP_DPD3P AU20
AU12 AT19 RSVD GENERICC 0
DVPDATA_22 TXCDM_DPD3N
AP12 DVPDATA_23
AT21 AUD[1] AUD[0]
TX3P_DPD2P AUD[1] HSYNC 0 0 No audio function 11
AJ21 SWAPLOCKA TX3M_DPD2N AR20
AK21 0 1 Audio for DisplayPort and HDMI if dongle is detected
SWAPLOCKB DPD AUD[0] VSYNC
AU22 1 0 Audio for DisplayPort only
TX4P_DPD1P
TX4M_DPD1N AV21 1 1 Audio for both DisplayPort and HDMI
I2C
TX5P_DPD0P
TX5M_DPD0N
AT23
AR22 AMD RESERVED CONFIGURATION STRAPS
STRAPS AK26 SCL ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
AJ26 SDA
+3VGS Reserve as AMD request RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
C
R AD39 NOT CONFLICT DURING RESET C
GENERAL PURPOSE I/O AD37
10K_0402_5% @ R229 GPU_GPIO0 GPU_GPIO0 RB +3VGS
1 2 AH20 GPIO_0
10K_0402_5% 1 PX@ 2 R230 GPU_GPIO1 GPU_GPIO1 AH18 AE36 GPIO21 H2SYNC GENERICC GPIO2 GPIO8
10K_0402_5% R231 GPU_GPIO2 GPU_GPIO2 GPIO_1 G VGA_HSYNC
1 PX@ 2 AN16 GPIO_2 GB AD35 10K_0402_5% 1 @ 2 R892
VGA_SMB_DA2 AH23
RB751V_SOD323 VGA_SMB_CK2 GPIO_3_SMBDATA VGA_VSYNC 10K_0402_5% @
AJ23 GPIO_4_SMBCLK B AF37 1 2 R893
10K_0402_5% 1 @ 2 R232 GPU_GPIO5 D2 @ 1 2 GPU_GPIO5 AH17 AE38 Transmitter Power Saving Enable
<33,41> ACIN GPIO_5_AC_BATT DAC1 BB
GPU_GPIO_6 AJ17 TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode
T49 R02 GPIO_6 VGA_HSYNC
AK17 GPIO_7_BLON HSYNC AC36 1: full Tx output swing (Default setting for Desktop)
10K_0402_5% 1 @ 2 R234 GPU_GPIO8 GPU_GPIO8 AJ13 AC38 VGA_VSYNC
10K_0402_5% @ R236 GPU_GPIO9 GPU_GPIO9 GPIO_8_ROMSO VSYNC
1 2 AH15 GPIO_9_ROMSI PCI Express Transmitter De-emphasis Enable
AJ16 +1.8VGS TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode
10K_0402_5% R237 GPU_GPIO11 GPU_GPIO11 GPIO_10_ROMSCK
1 PX@ 2 AK16 GPIO_11 RSET AB34 R238 1 PX@ 2 499_0402_1% 1: Tx de-emphasis enabled (Defailt setting for desktop)
10K_0402_5% 1 @ 2 R239 GPU_GPIO12 GPU_GPIO12 AL16
10K_0402_5% @ R240 GPU_GPIO13 GPU_GPIO13 GPIO_12 +AVDD
1 2 AM16 GPIO_13 AVDD AD34 (1.8V@65mA AVDD) 1 2
AM14 AE34 L16 PX@
GPIO_14_HPD2 AVSSQ
C274
C275
C273
GPU_VID0 BLM15BD121SN1D_0402
10U_0603_6.3V6M
0.1U_0402_16V7K
1U_0402_6.3V6K
<46> GPU_VID0 AM13 GPIO_15_PWRCNTL_0
GPIO_16 AK14 AC33 +VDD1DI (1.8V@100mA VDD1DI) 1 2 +1.8VGS 1 1 1
T50 GPIO_16 VDD1DI L17 PX@
AG30 GPIO_17_THERMAL_INT VSS1DI AC34
C276
C277
C278
10U_0603_6.3V6M
BLM15BD121SN1D_0402
1U_0402_6.3V6K
0.1U_0402_16V7K
AN14 GPIO_18_HPD3
R241 1 @ 2 10K_0402_5% AM17 1 1 1
GPIO_19_CTF 2 2 2
PX@
PX@
PX@
GPU_VID1 AL13 AC30
<46> GPU_VID1 GPIO_20_PWRCNTL_1 R2/NC
GPIO21_BBEN AJ14 AC31
+3VGS T51 AK13
GPIO_21_BB_EN
GPIO_22_ROMCSB
R2B/NC
2 2 2
+3VGS
Internal VGA Thermal Sensor
PX@
PX@
PX@
PEG_CLKREQ# AN13 AD30
<14> PEG_CLKREQ# GPIO_23_CLKREQB G2/NC
10K_0402_5% 1 @ 2 R242 GPIO24_TRSTB GPIO24_TRSTB AM23 AD31
10K_0402_5% @ GPIO25_TDI GPIO25_TDI JTAG_TRSTB G2B/NC
1 2 R243 AN23 JTAG_TDI
10K_0402_5% 1 @ 2 R244 GPIO27_TMS GPIO26_TCK AK23 AF30 +3VGS
JTAG_TCK B2/NC
1
GPIO27_TMS AL24 AF31 PX@ PX@
10K_0402_5% @ GPIO26_TCK GPIO28_TDO JTAG_TMS B2B/NC
1 2 R245 T52 AM24 JTAG_TDO
R246 R247
AJ19 10K_0402_5% 10K_0402_5%
GENERICA
AK19 GENERICB C/NC AC32
2
AJ20 AD32
2
GENERICC Y/NC
AK20 GENERICD COMP/NC AF32
AJ24 VGA_SMB_CK2 1 6
GENERICE_HPD4 DAC2 EC_SMB_CK2 <24,32,33>
AH26 GENERICF_HPD5
5
AH24 AD29 GENLK_CLK T53 PX@ Q17A
B GENERICG_HPD6 H2SYNC/GENLK_CLK GENLK_VSYNC T54 DMN66D0LDW-7_SOT363-6 B
V2SYNC/GENLK_VSYNC AC29
VGA_SMB_DA2 4 3 EC_SMB_DA2 <24,32,33>
AK24 HPD1
AG31 PX@ Q17B
VDD2DI/NC DMN66D0LDW-7_SOT363-6
VSS2DI/NC AG32
0.60 V level, Please
VREFG Divider ans A2VDD/NC AG33
+1.8VGS
PX@ cap close to ASIC AD33
+1.8VGS +VREFG_GPU A2VDDQ/NC
2 R248 1 499_0402_1% AH13 VREFG
PX@ AF33
L18 PX@ A2VSSQ/TSVSSQ
75mA 2 R249 1 249_0402_1%
2 1 +DPLL_PVDD
BLM15BD121SN1D_0402 2 1 AA29
R2SET/NC
C280
C281
C282
C279 0.1U_0402_16V7K +DPLL_PVDD AM32
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
PX@ DPLL_PVDD
1 1 1 AN32 DPLL_PVSS
DDC/AUX AM26
+DPLL_VDDC AN31 PLL/CLOCK DDC1CLK
DPLL_VDDC DDC1DATA AN26
2 2 2
PX@
PX@
PX@
AUX1P AM27
XTALIN AV33 AL27
XTALOUT AU34 XTALIN AUX1N
XTALOUT
DDC2CLK AM19
+1.0VGS AL19
L19 PX@ DDC2DATA
125mA +DPLL_VDDC
AW34 XO_IN
2 1 XTALIN AUX2P AN20
BLM15BD121SN1D_0402 AW35 AM20
Voltage Swing: 1.8 V XO_IN2 AUX2N
C284
C285
C287
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
1 1 1 DDCCLK_AUX3P AL30
DDCDATA_AUX3N AM30
DDCCLK_AUX4P AL29
2 2 2
PX@
PX@
PX@
AF29 DPLUS DDCDATA_AUX4N AM29
AG29 THERMAL
DMINUS
DDCCLK_AUX5P AN21
A
DDCDATA_AUX5N AM21 A
AK32 TS_FDO
R254 DDC6CLK AJ30
AL31 TS_A/NC DDC6DATA AJ31
XTALOUT PX@ XTALIN PX@ (1.8V@20mA TSVDD)
L20 AK30
1M_0402_5% +TSVDD DDCCLK_AUX7P
+1.8VGS 1 2 AJ32 TSVDD DDCDATA_AUX7N AK29
Y2 PX@ BLM15BD121SN1D_0402
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V4Z
AJ33 TSVSS
C288
C289
C290
2 1 1 1 1
27MHZ_16PF_X5H027000FG1H
Seymour M2 PX@
Security Classification Compal Secret Data Compal Electronics, Inc.
PX@ C291 C292 PX@ 2 2 2
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
PX@
PX@
PX@
18P_0402_50V8J 18P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_SeymourXT_M2_Main_MSIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 18 of 51
5 4 3 2 1
5 4 3 2 1
+3VGS +5VS +5VS
1
Q18 Q19 [email protected], in BACO mode
R256 PX4@ PX4@
0.1U_0402_16V7K
1
+1.0VGS
@ C293
1 10K_0402_5% AO3414_SOT23-3 AO3414_SOT23-3
R257 PX4@ +BIF_VDDC +VGA_CORE
D
10K_0402_5%
S
<14,17,46> VGA_PWRGD 3 1 1 3
2
PX4@ VDDC_ON#
2
2
1.0V_ON# PX5@
G
2
2
PX4@ 1.0V_ON# 1 2
5
+3VGS 1 R259 2 U9 R250 0_0805_5%
6
10K_0402_5% 2 PX4@ Q22 Q23 1
P
B PX4@ PX4@ PX4@ PX4@ C294
Y 4
1 +VGA_CORE AO3414_SOT23-3 AO3414_SOT23-3
A
G
D D
5 Q68B 2 Q68A PX@ 22U_0805_6.3V6M
2
D
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
S
3 1 1 3
3
MC74VHC1G08DFT2G SC70 5P
G
D
2
1
2 Q24 C296 @ VDDC_ON#
<20> PX_EN
G 2N7002K_SOT23-3 0.1U_0402_16V7K
S PX4@ +3VGS 1 2
3
U10
5
2
P
B PX_MODE
Y 4 PX_MODE <46>
+3VGS 1 A
G
PX4@
3
MC74VHC1G08DFT2G SC70 5P
1
@
R261
20K_0402_5%
2
PXS_PWREN 1 PX@ 2 RUNPWROK 1 2
R880 R262
0_0402_5% 0_0402_5%
PX5@
@
C297
1 +3.3VS TO +3.3VGS +3VS +3VGS
1U_0402_6.3V6K
J2 @
2 10U_0603_6.3V6M 1U_0603_10V6K
2 1
1
+3VALW 2MM @
1 1
C302 C303 R268
PX@ PX@ 470_0603_5%
1
C C
@ 2 2
3 1
2
R263 +5VALW
100K_0402_5%
D
1
Q27
2
AP2301GN-HF_SOT23-3 2
2
PXS_PWREN# PX@ G
@ R270 R271 S Q29
3
Q26 2N7002K_SOT23-3
1
DTC124EKAT146_SC59-3 20K_0402_5% 20K_0402_5% @
OUT
PX@ PX@
D 1 PX@
1
C304 PXS_PWREN# 1 @ 2
PXS_PWREN 2 PXS_PWREN 2 0.1U_0603_25V7K R272
<14,43,46> PXS_PWREN IN G Q30 0_0402_5%
GND
S 2N7002K_SOT23-3 2
3
PX@
3
+1.5V +1.5VGS
J9 @
+1.5VS TO +1.5VGS 2 1
B B
2MM
U12 PX@
10U_0603_6.3V6M AO4430L_SO8
8 1
1 7 2 1 1
1
C305 6 3 PX@ PX@ @
PX@ 5 C306 C307 R274
10U_0603_6.3V6M 1U_0603_10V6K 470_0603_5%
2 2 2
1 2
+VSB D
2
PX@ G
R275 S Q31 @
3
+3VALW 20K_0402_5% 2N7002K_SOT23-3
R278
1
1 PX@ 2
2
PX@ 150K_0402_5% 1
6
R273 R280 PX@
100K_0402_5% 0_0402_5% C308 @
PX@ @ 0.1U_0603_25V7K PX_MODE# 1 R282 2 0_0402_5%
2
PX_MODE# Q69A 2
2
1
DMN66D0LDW-7_SOT363-6
1
3
PX@
PX_MODE 5 Q69B
DMN66D0LDW-7_SOT363-6
1
4
PX@ R276
100K_0402_5%
A A
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_SeymourXT_M2_BACO POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 19 of 51
5 4 3 2 1
5 4 3 2 1
U6F
AB39 PCIE_VSS#1 GND#1 A3
E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
D
H34 PCIE_VSS#8 GND#8 AA26 D
H39 PCIE_VSS#9 GND#9 AA28
J31 PCIE_VSS#10 GND#10 AA6
J34 PCIE_VSS#11 GND#11 AB12
K31 PCIE_VSS#12 GND#12 AB15
K34 PCIE_VSS#13 GND#13 AB17
K39 PCIE_VSS#14 GND#14 AB20
1.8V@300mA DPAB_VDD18) +DPAB_VDD18 +1.8VGS L31 AB22
PCIE_VSS#15 GND#15
L34 PCIE_VSS#16 GND#16 AB24
M34 PCIE_VSS#17 GND#17 AB27
+DPAB_VDD18 1 R283 2 M39 AC11
PCIE_VSS#18 GND#18
1 1 1 N31 PCIE_VSS#19 GND#19 AC13
C311
C312
C309
10U_0603_6.3V6M
0_0402_5%
0.1U_0402_16V7K
1U_0402_6.3V6K
N34 PCIE_VSS#20 GND#20 AC16
U6H PX@ P31 AC18
+1.8VGS +DPCD_VDD18 PCIE_VSS#21 GND#21
P34 PCIE_VSS#22 GND#22 AC2
DP C/D POWER DP A/B POWER @ 2 @ 2 @ 2
P39 PCIE_VSS#23 GND#23 AC21
130mA R34 PCIE_VSS#24 GND#24 AC23
1 R284 2 +DPCD_VDD18 AP20 AN24 T31 AC26
DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1 +DPAB_VDD10 PCIE_VSS#25 GND#25
AP21 DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2 AP24 T34 PCIE_VSS#26 GND#26 AC28
+1.0VGS
C313
C314
C310
10U_0603_6.3V6M
0_0402_5% 1U_0402_6.3V6K
0.1U_0402_16V7K
T39 PCIE_VSS#27 GND#27 AC6
PX@ 1 1 1 +DPCD_VDD10 (1.0V@220mA DPAB_VDD10) U31 AD15
PCIE_VSS#28 GND#28
110mA U34 PCIE_VSS#29 GND#29 AD17
@ @ @ AP13 AP31 +DPAB_VDD10 1 R285 2 V34 AD20
DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 PCIE_VSS#30 GND#30
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
AT13 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 AP32 V39 PCIE_VSS#31 GND#31 AD22
2 2 2
C315
C316
C317
0_0402_5% W31 AD24
PCIE_VSS#32 GND#32
1 1 1 PX@ W34 PCIE_VSS#33 GND#33 AD27
AN17 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AN27 Y34 PCIE_VSS#34 GND#34 AD9
AP16 AP27 @ @ @ Y39 AE2
DP/DPC_VSSR#2 DP/DPA_VSSR#2 PCIE_VSS#35 GND#35
AP17 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AP28 GND#36 AE6
2 2 2
AW14 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW24 GND#37 AF10
AW16 DP/DPC_VSSR#5 DP/DPA_VSSR#5 AW26 GND#38 AF16
GND#39 AF18
+1.0VGS +DPCD_VDD10
+DPCD_VDD18
AP22 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1
+DPAB_VDD18
AP25 130mA F15 GND#100
GND GND#40
GND#41
GND#42
AF21
AG17
AG2
AP23 DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 AP26 F17 GND#101 GND#43 AG20
1 R286 2 +DPCD_VDD10 F19 AG22
+DPCD_VDD10 +DPAB_VDD10 GND#102 GND#44
F21 GND#103 GND#45 AG6
@ C318
@ C319
@ C320
10U_0603_6.3V6M
0_0402_5%
1U_0402_6.3V6K
0.1U_0402_16V7K
C F23 GND#104 GND#46 AG9 C
PX@ 1 1 1 AP14 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 AN33110mA F25 GND#105 GND#47 AH21
AP15 DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 AP33 F27 GND#106 GND#48 AJ10
F29 GND#107 GND#49 AJ11
F31 GND#108 GND#50 AJ2
2 2 2
F33 GND#109 GND#51 AJ28
AN19 DP/DPD_VSSR#1 DP/DPB_VSSR#1 AN29 F7 GND#110 GND#52 AJ6
AP18 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP29 F9 GND#111 GND#53 AK11
AP19 DP/DPD_VSSR#3 DP/DPB_VSSR#3 AP30 G2 GND#112 GND#54 AK31
AW20 DP/DPD_VSSR#4 DP/DPB_VSSR#4 AW30 G6 GND#113 GND#55 AK7
AW22 DP/DPD_VSSR#5 DP/DPB_VSSR#5 AW32 H9 GND#114 GND#56 AL11
J2 GND#115 GND#57 AL14
J27 GND#116 GND#58 AL17
J6 GND#117 GND#59 AL2
150_0402_1% 2 PX@ 1 R287 AW18 AW28 R288 1 PX@ 2 150_0402_1% J8 AL20
+1.8VGS DPCD_CALR DPAB_CALR GND#118 GND#60
K14 GND#119 GND/PX_EN#61 AL21 PX_EN <19>
+DPEF_VDD18 +DPAB_VDD18 K7 AL23
GND#120 GND#62
150mA DP E/F POWER DP PLL POWER 20mA L11 GND#121 GND#63 AL26
1 R289 2 +DPEF_VDD18 AH34 AU28 L17 AL32
DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD GND#122 GND#64
1
AJ34 DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS AV27 L2 GND#123 GND#65 AL6
@ C321
@ C322
@ C323
10U_0603_6.3V6M
0_0402_5% R290
1U_0402_6.3V6K
0.1U_0402_16V7K
L22 GND#124 GND#66 AL8
PX@ 1 1 1 +DPEF_VDD10 +DPAB_VDD18 L24 AM11 4.7K_0402_5%
GND#125 GND#67 PX@
20mA L6 GND#126 GND#68 AM31
AL33 AV29 M17 AM9
2
DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD GND#127 GND#69
AM33 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS AR28 M22 GND#128 GND#70 AN11
2 2 2
M24 GND#129 GND#71 AN2
+DPCD_VDD18 N16 AN30
GND#130 GND#72
N18 GND#131 GND#73 AN6
AN34 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD AU18 N2 GND#132 GND#74 AN8
AP39 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS AV17 N21 GND#133 GND#75 AP11
AR39 DP/DPE_VSSR#3 N23 GND#134 GND#76 AP7
AU37 +DPCD_VDD18 N26 AP9
DP/DPE_VSSR#4 GND#135 GND#77
N6 GND#136 GND#78 AR5
DPCD_VDD18/DPD_PVDD AV19 R15 GND#137 GND#79 B11
+DPEF_VDD18 AR18 R17 B13
DP_VSSR/DPD_PVSS GND#138 GND#80
20mA R2 GND#139 GND#81 B15
AF34 +DPEF_VDD18 R20 B17
+1.0VGS +DPEF_VDD10 DPEF/DPF_VDD18#1 GND#140 GND#82
B
AG34 DPEF/DPF_VDD18#2 R22 GND#141 GND#83 B19 B
DPEF_VDD18/DPE_PVDD AM37 R24 GND#142 GND#84 B21
+DPEF_VDD10 AN38 R27 B23
DP_VSSR/DPE_PVSS GND#143 GND#85
20mA R6 GND#144 GND#86 B25
1 R291 2 +DPEF_VDD10 AK33 +DPEF_VDD18 T11 B27
DPEF/DPF_VDD10#1 GND#145 GND#87
AK34 DPEF/DPF_VDD10#2 T13 GND#146 GND#88 B29
@ C324
@ C325
@ C326
0_0402_5%
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
DPEF_VDD18/DPF_PVDD AL38 T16 GND#147 GND#89 B31
PX@ 1 1 1 DP_VSSR/DPF_PVSS AM35 T18 GND#148 GND#90 B33
T21 GND#149 GND#91 B7
AF39 DP/DPF_VSSR#1 T23 GND#150 GND#92 B9
AH39 DP/DPF_VSSR#2 T26 GND#151 GND#93 C1
2 2 2
AK39 DP/DPF_VSSR#3 U15 GND#153 GND#94 C39
AL34 DP/DPF_VSSR#4 U17 GND#154 GND#95 E35
AM34 DP/DPF_VSSR#5 U2 GND#155 GND#96 E5
U20 GND#156 GND#97 F11
U22 GND#157 GND#98 F13
U24 GND#158
150_0402_1% 2 PX@ 1 R292 AM39 U27
DPEF_CALR GND#159
U6 GND#160
V11 GND#161
Seymour M2 V16
PX@ GND#163
V18 GND#164
V21 GND#165
V23 GND#166
V26 GND#167
W2 GND#168
W6 GND#169
Y15 GND#170
Y17 GND#171
Y20 GND#172
Y22 GND#173 VSS_MECH#1 A39 MECH#1
Y24 AW1 MECH#2 T55 PAD
GND#174 VSS_MECH#2 T56 PAD
Y27 GND#175 VSS_MECH#3 AW39MECH#3
U13 T57 PAD
GND#152
V13 GND#162
Seymour M2
PX@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_SetmourXT_M2_PWR_GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 20 of 51
5 4 3 2 1
5 4 3 2 1
(1.8V@504mA PCIE_VDDR) +1.8VGS
+1.5VGS U6E PX@ L21
For DDR3/GDDR5, MVDDQ = 1.5V +PCIE_VDDR 2 1
MEM I/O MBK1608121YZF_0603
PCIE
C330
C331
C332
C333
C334
C335
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AC7
AD11
VDDR1#1 PCIE_VDDR#1 AA31
AA32
1 1 1 1 1 1 PCIE_VDDR CRB Design
VDDR1#2 PCIE_VDDR#2
0.1u 2 2
C336
C337
C338
C327
C339
C328
C340
C341
C329
C342
C343
C344
C345
C346
C347
C348
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
220U_B2_2.5VM_R35
D 1 AF7 VDDR1#3 PCIE_VDDR#3 AA33 D
AG10 AA34
+
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDR1#4 PCIE_VDDR#4 2 2 2 2 2 2 1u 3 3
PX@
PX@
PX@
PX@
PX@
PX@
AJ7 VDDR1#5 PCIE_VDDR#5 V28
@ AK8
AL9
VDDR1#6 PCIE_VDDR#6 W29
W30
10u 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDR1#7 PCIE_VDDR#7
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
G11 VDDR1#8 PCIE_VDDR#8 Y31
G14 AB37 +1.0VGS
VDDR1#9 PCIE_VDDR/PCIE_PVDD
G17 VDDR1#10 (1.0V@1920mA PCIE_VDDC)
G20 VDDR1#11 PCIE_VDDC#1 G30
G23 VDDR1#12 PCIE_VDDC#2 G31
C349
C350
C351
C352
C353
C354
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
G26 VDDR1#13 PCIE_VDDC#3 H29
G29 VDDR1#14 PCIE_VDDC#4 H30 1 1 1 1 1 1
H10
J7
VDDR1#15 PCIE_VDDC#5 J29
J30
PCIE_VDDC CRB Design
J9
VDDR1#16
VDDR1#17
PCIE_VDDC#6
PCIE_VDDC#7 L28
2 2 2 2 2 2
1u 7 5 (1@)
PX@
PX@
PX@
PX@
PX@
@
K11 M28
K13
VDDR1#18
VDDR1#19
PCIE_VDDC#8
PCIE_VDDC#9 N28 10u 1 1
VDDR1 CRB Design K8
L12
VDDR1#20 PCIE_VDDC#10 R28
T28
0.1u 6 6 L16
VDDR1#21
VDDR1#22
PCIE_VDDC#11
PCIE_VDDC#12 U28
+VGA_CORE
1u 10 5 L21
L23
VDDR1#23
VDDR1#24
10u 6 5 L26
L7
VDDR1#25 CORE VDDC#1 AA15
AA17
VDDC CRB Design
VDDR1#26 VDDC#2
1u 30 25
C355
C356
C359
C360
C361
C362
C363
C364
C365
C366
C367
C368
C369
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
M11 VDDR1#27 VDDC#3 AA20
N11 AA22
VDD_CT CRB Design P7
VDDR1#28
VDDR1#29
VDDC#4
VDDC#5 AA24
1 1 1 1 1 1 1 1 1 1 1 1 1
10u 10 1
0.1u 1 1
R11
U11
VDDR1#30 VDDC#6 AA27
AB16
22u 0 1
VDDR1#31 VDDC#7 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
+1.8VGS +VDDC_CT
1u 3 3 U7
Y11
VDDR1#32
VDDR1#33
VDDC#8
VDDC#9
AB18
AB21
10u 1 1 1
PX@ L22
2
(1.8V@110mA VDD_CT) Y7 VDDR1#34 VDDC#10 AB23
AB26
BLM15BD121SN1D_0402 VDDC#11
VDDC#12 AB28
+VGA_CORE
C370
C371
C372
C373
C374
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDC#13 AC17
1 1 1 1 1 VDDC#14 AC20
VDDR3 CRB Design +3VGS
LEVEL
TRANSLATION VDDC#15 AC22
AC24
1u 3 3 VDDC#16
POWER
C377
C378
C379
C381
C382
C383
C384
C385
C386
C387
C388
C389
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C AF26 VDD_CT#1 VDDC#17 AC27 C
PX@ 2 2 2 2 2
PX@
PX@
PX@
PX@
10u 1 1 AF27
AG26
VDD_CT#2
VDD_CT#3
VDDC#18
VDDC#19
AD18
AD21
1 1 1 1 1 1 1 1 1 1 1 1
C390
C391
C392
C393
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AG27 VDD_CT#4 VDDC#20 AD23
1 1 1 1 VDDC#21 AD26
2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
VDDC#22 AF17
VDDR4 CRB Design AF23
I/O
VDDC#23 AF20
AF22
0.1u 1 1 2 2 2 2 VDDR3#1 VDDC#24
PX@
PX@
PX@
PX@
AF24 VDDR3#2 VDDC#25 AG16
1u 1 1 +1.8VGS
AG23
AG24
VDDR3#3
VDDR3#4
VDDC#26
VDDC#27
AG18
AG21 +VGA_CORE
VDDC#28 AH22
PX@ L23 AH27
VDDC#29
MPV18 CRB Design 1 2 +VDDR4 AF13 VDDR4#4 VDDC#30 AH28
C400
C394
10U_0603_6.3V6M
22U_0603_6.3V6M
BLM15BD121SN1D_0402 AF15 M26
0.1u 2 1 VDDR4#5 VDDC#31
C396
C397
1U_0402_6.3V6K
0.1U_0402_16V7K
AG13 VDDR4#7 VDDC#32 N24 1 1
1u 2 1 1 1 AG15 VDDR4#8 VDDC/BIF_VDDC#33
VDDC#34
N27
R18
10u 1 1 VDDC#35 R21
2 2
PX@
PX@
AD12 VDDR4#1 VDDC#36 R23
2 2
PX@
PX@
AF11 VDDR4#2 VDDC#37 R26
AF12 VDDR4#3 VDDC#38 T17
SPV18 CRB Design AG11 VDDR4#6 VDDC#39 T20
T22
+BIF_VDDC
0.1u 1 1 +1.8VGS +1.8VGS VDDC#40
VDDC#41 T24
1u 1 1 (M97, Broadway and Madison: 1.8V@150mA MPV18)
VDDC/BIF_VDDC#42
VDDC#43
T27
U16 For non-BACO designs, connect BIF_VDDC to VDDC.
10u 1 1
C401
C402
L24 PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
M20 U18
1 2 +MPV18 M21
NC_VDDRHA VDDC#44
U21 1 1 For BACO designs - see BACO reference schematics
MCK1608471YZF 0603 NC_VSSRHA VDDC#45
VDDC#46 U23
L25 PX@
VDDC#47 U26 VDDCI CRB Design
SPV10 CRB Design
C403
C404
C405
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
1 2 V12 V17
NC_VDDRHB VDDC#48 2 2
1u 10 9
PX@
PX@
BLM15BD121SN1D_0402 1 1 1 U12 V20
0.1u 1 1 NC_VSSRHB VDDC#49
VDDC#50 V22
10u 3 2
C406
C407
C408
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
1u 1 1 1 1 1
VDDC#51
VDDC#52
V24
V27 22u 0 1
2 2 2
PX@
PX@
PX@
10u 1 1 PLL VDDC#53 Y16
Y18
B VDDC#54 B
VDDC#55 Y21
2 2 2
PX@
PX@
PX@
VDDC#56 Y23
H7 MPV18#1 VDDC#57 Y26
H8 MPV18#2 VDDC#58 Y28
(GDDR3/DDR3 1.12V@4A VDDCI) +VGA_CORE
+1.0VGS
(1.8V@75mA SPV18) +SPV18 AM10 (GDDR5 1.12V@16A VDDCI)
PX@ L26 SPV18
VDDCI#1 AA13
1 2 (120mA SPV10) +SPV10 AN9 AB13
SPV10 VDDCI#2
C409
C410
C411
C412
C413
C414
C415
C416
C417
C418
C422
C425
MCK1608471YZF 0603
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDCI#3 AC12
AN10 SPVSS VDDCI#4 AC15 1 1 1 1 1 1 1 1 1 1 1 1
C420
C424
C426
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDCI#5 AD13
1 1 1 VDDCI#6 AD16
VDDCI#7 M15
2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
VDDCI#8 M16
VOLTAGE M18
2 2 2 SENESE VDDCI#9
PX@
PX@
PX@
VDDCI#10 M23
VDDCI#11 N13
<46> VCCSENSE_VGA AF28 FB_VDDC VDDCI#12 N15
VDDCI#13 N17
AG28
VDDCI#14 N20
N22
VDDCI and VDDC should have seperate regulators with a merge option on PCB
FB_VDDCI ISOLATED VDDCI#15
CORE I/O VDDCI#16
R12
R13
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator
VDDCI#17
<46> VSSSENSE_VGA AH29 FB_GND VDDCI#18 R16
VDDCI#19 T12
VDDCI#20 T15
Route as differential VDDCI#21 V15
VDDCI#22 Y13
Seymour M2
PX@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_SeymourXT_M2_Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 21 of 51
5 4 3 2 1
5 4 3 2 1
U6C
DDR2 DDR2 U6D MDB[0..63]
GDDR3/GDDR5 GDDR5/GDDR3 DDR2 DDR2 <23> MDB[0..63]
DDR3 DDR3 GDDR3/GDDR5 GDDR5/GDDR3
C37 G24 DDR3 DDR3 MAB[12..0]
DQA0_0/DQA_0 MAA0_0/MAA_0 MAB[12..0] <23>
C35 J23 MDB0 C5 P8 MAB0
DQA0_1/DQA_1 MAA0_1/MAA_1 MDB1 DQB0_0/DQB_0 MAB0_0/MAB_0 MAB1 B_BA[2..0]
A35 DQA0_2/DQA_2 MAA0_2/MAA_2 H24 C3 DQB0_1/DQB_1 MAB0_1/MAB_1 T9 B_BA[2..0] <23>
E34 J24 MDB2 E3 P9 MAB2
MEMORY INTERFACE A
DQA0_3/DQA_3 MAA0_3/MAA_3 MDB3 DQB0_2/DQB_2 MAB0_2/MAB_2 MAB3
G32 DQA0_4/DQA_4 MAA0_4/MAA_4 H26 E1 DQB0_3/DQB_3 MAB0_3/MAB_3 N7
D33 J26 MDB4 F1 N8 MAB4
MEMORY INTERFACE B
DQA0_5/DQA_5 MAA0_5/MAA_5 MDB5 DQB0_4/DQB_4 MAB0_4/MAB_4 MAB5
F32 DQA0_6/DQA_6 MAA0_6/MAA_6 H21 F3 DQB0_5/DQB_5 MAB0_5/MAB_5 N9
E32 G21 MDB6 F5 U9 MAB6
DQA0_7/DQA_7 MAA0_7/MAA_7 MDB7 DQB0_6/DQB_6 MAB0_6/MAB_6 MAB7
D31 DQA0_8/DQA_8 MAA1_0/MAA_8 H19 G4 DQB0_7/DQB_7 MAB0_7/MAB_7 U8
F30 H20 MDB8 H5 Y9 MAB8
DQA0_9/DQA_9 MAA1_1/MAA_9 MDB9 DQB0_8/DQB_8 MAB1_0/MAB_8 MAB9
C30 DQA0_10/DQA_10 MAA1_2/MAA_10 L13 H6 DQB0_9/DQB_9 MAB1_1/MAB_9 W9
A30 G16 MDB10 J4 AC8 MAB10
DQA0_11/DQA_11 MAA1_3/MAA_11 +1.8VGS MDB11 DQB0_10/DQB_10 MAB1_2/MAB_10 MAB11
F28 DQA0_12/DQA_12 MAA1_4/MAA_12 J16 K6 DQB0_11/DQB_11 MAB1_3/MAB_11 AC9
C28 H16 MDB12 K5 AA7 MAB12
D DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 R293 X76@ 2 10K_0402_5% VRAM_ID0 MDB13 DQB0_12/DQB_12 MAB1_4/MAB_12 B_BA2 D
A28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 J17 1 VRAM_ID0 <18> L4 DQB0_13/DQB_13 MAB1_5/BA2 AA8
E28 H17 R294 1 X76@ 2 10K_0402_5% MDB14 M6 Y8 B_BA0
DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 R295 X76@ 2 10K_0402_5% VRAM_ID1 MDB15 DQB0_14/DQB_14 MAB1_6/BA0 B_BA1
D27 DQA0_16/DQA_16 1 VRAM_ID1 <18> M1 DQB0_15/DQB_15 MAB1_7/BA1 AA9
F26 A32 R296 1 X76@ 2 10K_0402_5% MDB16 M3
DQA0_17/DQA_17 WCKA0_0/DQMA_0 DQB0_16/DQB_16 DQMB#[7..0] <23>
C26 C32 R297 1 X76@ 2 10K_0402_5% VRAM_ID2 MDB17 M5 H3 DQMB#0
DQA0_18/DQA_18 WCKA0B_0/DQMA_1 VRAM_ID2 <18> DQB0_17/DQB_17 WCKB0_0/DQMB_0
A26 D23 R298 1 X76@ 2 10K_0402_5% MDB18 N4 H1 DQMB#1
DQA0_19/DQA_19 WCKA0_1/DQMA_2 MDB19 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 DQMB#2
F24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 E22 P6 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T3
C24 C14 MDB20 P5 T5 DQMB#3
DQA0_21/DQA_21 WCKA1_0/DQMA_4 MDB21 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 DQMB#4
A24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 A14 R4 DQB0_21/DQB_21 WCKB1_0/DQMB_4 AE4
E24 E10 MDB22 T6 AF5 DQMB#5
DQA0_23/DQA_23 WCKA1_1/DQMA_6 MDB23 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 DQMB#6
C22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 D9 T1 DQB0_23/DQB_23 WCKB1_1/DQMB_6 AK6
A22 MDB24 U4 AK5 DQMB#7
DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 MDB25 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
F22 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 C34 V6 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 QSB[7..0] <23>
D21 D29 MDB26 V1 F6 QSB0
DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 QSB1
A20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 D25 V3 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 K3
F20 E20 Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2 MDB28 Y6 P3 QSB2
DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 MDB29 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 QSB3
D19 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 E16 Y1 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 V5
E18 E12 MDB30 Y3 AB5 QSB4
DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 H5TQ1G63DFR-11C MDB31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 QSB5
C18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 J10 Y5 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AH1
A18 D7 R293 R296 R298 MDB32 AA4 AJ9 QSB6
DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6
F18 DQA1_2/DQA_34
64MX16 (512MB) SA000041S30 MDB33 AB6 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 AM5 QSB7
QSB#[7..0] <23>
D17 A34 1 0 0 MDB34 AB1
DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 K4W1G1646G-BC11 MDB35 DQB1_2/DQB_34 QSB#0
A16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E30 AB3 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 G7
F16 E26 R294 R295 R298 MDB36 AD6 K1 QSB#1
DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1
D15 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C20 64MX16 (512MB) SA00004GS40 MDB37 AD1 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 P1 QSB#2
E14 C16 0 1 0 MDB38 AD3 W4 QSB#3
DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 H5TQ2G63BFR-11C MDB39 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 QSB#4
F14 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 C12 AD5 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AC4
D13 J11 R293 R296 R297 MDB40 AF1 AH3 QSB#5
DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5
F12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 F8 128Mx16 (1GB) SA00003YO10 MDB41 AF3 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AJ8 QSB#6
A12 1 0 1 MDB42 AF6 AM3 QSB#7
DQA1_11/DQA_43 K4W2G1646C-HC11 MDB43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
D11 DQA1_12/DQA_44 ADBIA0/ODTA0 J21 AG4 DQB1_11/DQB_43
F10 G19 R294 R295 R297 MDB44 AH5 T7 ODTB0
DQA1_13/DQA_45 ADBIA1/ODTA1 DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB0 <23>
A10 DQA1_14/DQA_46
128Mx16 (1GB) SA000047Q10 MDB45 AH6 DQB1_13/DQB_45 ADBIB1/ODTB1 W7 ODTB1
ODTB1 <23>
C10 H27 0 1 1 MDB46 AJ4
DQA1_15/DQA_47 CLKA0 MDB47 DQB1_14/DQB_46 CLKB0
G13 DQA1_16/DQA_48 CLKA0B G27 AK3 DQB1_15/DQB_47 CLKB0 L9 CLKB0 <23>
H13 MDB48 AF8 L8 CLKB0#
DQA1_17/DQA_49 DQB1_16/DQB_48 CLKB0B CLKB0# <23>
J13 J14 MDB49 AF9
DQA1_18/DQA_50 CLKA1 MDB50 DQB1_17/DQB_49 CLKB1
C H11 DQA1_19/DQA_51 CLKA1B H14 AG8 DQB1_18/DQB_50 CLKB1 AD8 CLKB1 <23> C
G10 MDB51 AG7 AD7 CLKB1#
DQA1_20/DQA_52 DQB1_19/DQB_51 CLKB1B CLKB1# <23>
G8 K23 MDB52 AK9
DQA1_21/DQA_53 RASA0B MDB53 DQB1_20/DQB_52 RASB0#
K9 DQA1_22/DQA_54 RASA1B K19 AL7 DQB1_21/DQB_53 RASB0B T10 RASB0# <23>
K10 MDB54 AM8 Y10 RASB1#
DQA1_23/DQA_55 DQB1_22/DQB_54 RASB1B RASB1# <23>
G9 K20 ZZZ20 ZZZ21 ZZZ22 ZZZ23 MDB55 AM7
DQA1_24/DQA_56 CASA0B MDB56 DQB1_23/DQB_55 CASB0#
A8 DQA1_25/DQA_57 CASA1B K17 AK1 DQB1_24/DQB_56 CASB0B W10 CASB0# <23>
C8 MDB57 AL4 AA10 CASB1#
DQA1_26/DQA_58 DQB1_25/DQB_57 CASB1B CASB1# <23>
E8 K24 MDB58 AM6
DQA1_27/DQA_59 CSA0B_0 MDB59 DQB1_26/DQB_58 CSB0#_0
A6 DQA1_28/DQA_60 CSA0B_1 K27 AM1 DQB1_27/DQB_59 CSB0B_0 P10 CSB0#_0 <23>
C6 MDB60 AN4 L10
DQA1_29/DQA_61 MDB61 DQB1_28/DQB_60 CSB0B_1
E6 DQA1_30/DQA_62 CSA1B_0 M13 VRAM VRAM VRAM VRAM AP3 DQB1_29/DQB_61
A5 K16 H1G@ H512M@ S1G@ S512M@ MDB62 AP1 AD10 CSB1#_0
DQA1_31/DQA_63 CSA1B_1 DQB1_30/DQB_62 CSB1B_0 CSB1#_0 <23>
X7638538L01 X7638538L04 X7638538L02 X7638538L03 MDB63 AP5 AC10
DQB1_31/DQB_63 CSB1B_1
L18 MVREFDA CKEA0 K21
+1.5VGS L20 J20 U10 CKEB0
MVREFSA CKEA1 CKEB0 CKEB0 <23>
+VDD_MEM15_REFDB Y12 AA11 CKEB1
MVREFDB CKEB1 CKEB1 <23>
R299 1 @ 2 240_0402_1% L27 K26 +VDD_MEM15_REFSB AA12
R300 1 PX@ MEM_CALRN0 WEA0B MVREFSB WEB0#
2 240_0402_1% N12 MEM_CALRN1 WEA1B L15 WEB0B N10 WEB0# <23>
R301 1 @ 2 240_0402_1% AG12 AB11 WEB1#
MEM_CALRN2 WEB1B WEB1# <23>
R304 1 PX@ 2 240_0402_1% M12 H23 PX@
MEM_CALRP1 MAA0_8
GDDR5
R302 1 @ 2 240_0402_1% M27 J19 R303 1 2 TESTEN AD28 T8 MAB13
MEM_CALRP0 MAA1_8 TESTEN MAB0_8 MAB13 <23>
GDDR5
R305 1 @ 2 240_0402_1% AH12 5.11K_0402_1% W8 MAB14
MEM_CALRP2 MAB1_8 MAB14 <23>
AK10 CLKTESTA
AL10 AH11 DRAM_RST#_R
CLKTESTB DRAM_RST
Seymour M2
PX@ Seymour M2
PX@
1
Thames/Whislter M2 Seymour M2 @ @
C427 C428
R299 POP @ 0.1U_0402_16V7K 0.1U_0402_16V7K
2
B B
route 50ohms single-ended/100ohms diff
R300 @ POP This basic topology should be used for DRAM_RST for DDR3/GDDR5.These and keep short
Capacitors and Resistor values are an example only. The Series R and Debug only, for clock observation, if not needed, DNI
1
R301 POP @ || Cap values will depend on the DRAM load and will have to be
@ @ 5mil 5mil
calculated for different Memory ,DRAM Load and board to pass Reset
R302 POP @ Signal Spec.
R306 R307
51.1_0402_1% 51.1_0402_1%
R304 @ POP Place all these components very close to GPU (Within
2
25mm) and keep all component close to each Other (within
R305 POP @ 5mm) except Rser2
+1.5VGS
1
R308
4.7K_0402_5% +1.5VGS +1.5VGS
@
2
1
R311 R312
40.2_0402_1% 40.2_0402_1%
1 R313 2 1 R314 2 DRAM_RST#_R PX@ PX@
<23> DRAM_RST# 51.1_0402_1% 10_0402_5%
2
PX@ PX@
+VDD_MEM15_REFDB +VDD_MEM15_REFSB
2
1
PX@ PX@
1
C431 R317 C432 C433
120P_0402_50V9 4.99K_0402_1% R318 0.1U_0402_16V7K R319 0.1U_0402_16V7K
2
100_0402_1% PX@ 100_0402_1% PX@
1
2
PX@ PX@
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_SeymourXT_M2_MEM IF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Monday, November 07, 2011 Sheet 22 of 51
5 4 3 2 1
5 4 3 2 1
U17 U18 U19 U20
VREFC_A1_B M8 E3 MDB19 VREFC_A2_B M8 E3 MDB26 VREFC_A3_B M8 E3 MDB33 VREFC_A4_B M8 E3 MDB55
VREFD_Q1_B H1 VREFCA DQL0 MDB20 VREFD_Q2_B VREFCA DQL0 MDB30 VREFD_Q3_B VREFCA DQL0 MDB37 VREFD_Q4_B VREFCA DQL0 MDB50
VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDB22 F2 MDB24 F2 MDB35 F2 MDB54
MAB0 DQL2 MDB16 MAB0 DQL2 MDB29 MAB0 DQL2 MDB39 MAB0 DQL2 MDB51
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAB1 P7 H3 MDB23 MAB1 P7 H3 MDB27 MAB1 P7 H3 MDB32 MAB1 P7 H3 MDB53
MAB2 A1 DQL4 MDB17 MAB2 A1 DQL4 MDB28 MAB2 A1 DQL4 MDB36 MAB2 A1 DQL4 MDB49
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAB3 N2 G2 MDB21 MAB3 N2 G2 MDB25 MAB3 N2 G2 MDB34 MAB3 N2 G2 MDB52
MAB4 A3 DQL6 MDB18 MAB4 A3 DQL6 MDB31 MAB4 A3 DQL6 MDB38 MAB4 A3 DQL6 MDB48
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAB5 P2 MAB5 P2 MAB5 P2 MAB5 P2
MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAB7 R2 D7 MDB0 MAB7 R2 D7 MDB15 MAB7 R2 D7 MDB44 MAB7 R2 D7 MDB56
D MDB[0..63] MAB8 A7 DQU0 MDB4 MAB8 A7 DQU0 MDB10 MAB8 A7 DQU0 MDB41 MAB8 A7 DQU0 MDB59 D
<22> MDB[0..63] T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3
MAB9 R3 C8 MDB1 MAB9 R3 C8 MDB14 MAB9 R3 C8 MDB47 MAB9 R3 C8 MDB63
MAB10 A9 DQU2 MDB6 MAB10 A9 DQU2 MDB11 MAB10 A9 DQU2 MDB43 MAB10 A9 DQU2 MDB62
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
MAB11 R7 A7 MDB3 MAB11 R7 A7 MDB12 MAB11 R7 A7 MDB45 MAB11 R7 A7 MDB57
MAB12 A11 DQU4 MDB7 MAB12 A11 DQU4 MDB9 MAB12 A11 DQU4 MDB40 MAB12 A11 DQU4 MDB61
N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2
MAB13 T3 B8 MDB2 MAB13 T3 B8 MDB13 MAB13 T3 B8 MDB46 MAB13 T3 B8 MDB58
MAB[14..0] MAB14 A13 DQU6 MDB5 MAB14 A13 DQU6 MDB8 MAB14 A13 DQU6 MDB42 MAB14 A13 DQU6 MDB60
<22> MAB[14..0] T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3
M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+1.5VGS +1.5VGS +1.5VGS +1.5VGS
M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2
<22> B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
<22> B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
DQMB#[7..0] <22> B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
<22> DQMB#[7..0] VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKB0 J7 N9 J7 N9 CLKB1 J7 N9
<22> CLKB0 CK VDD CK VDD <22> CLKB1 CK VDD CK VDD
K7 R1 CLKB0# K7 R1 K7 R1 CLKB1# K7 R1
<22> CLKB0# CK VDD CK VDD <22> CLKB1# CK VDD CK VDD
K9 R9 CKEB0 K9 R9 K9 R9 CKEB1 K9 R9
QSB[7..0] <22> CKEB0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS <22> CKEB1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
<22> QSB[7..0]
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
<22> ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <22> ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
<22> CSB0#_0 CS/CS0 VDDQ CS/CS0 VDDQ <22> CSB1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
<22> RASB0# RAS VDDQ RAS VDDQ <22> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<22> CASB0# CAS VDDQ CAS VDDQ <22> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
QSB#[7..0] <22> WEB0# WE VDDQ WE VDDQ <22> WEB1# WE VDDQ WE VDDQ
<22> QSB#[7..0] VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB2 F3 H2 QSB3 F3 H2 QSB4 F3 H2 QSB6 F3 H2
QSB0 DQSL VDDQ QSB1 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
DQMB#2 E7 A9 DQMB#3 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
DQMB#0 DML VSS DQMB#1 DML VSS DQMB#5 DML VSS DQMB#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSB#2 G3 J2 QSB#3 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
PX@ QSB#0 DQSL VSS QSB#1 DQSL VSS QSB#5 DQSL VSS QSB#7 DQSL VSS
C B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 C
CLKB0 1 2 M1 M1 M1 M1
R344 56_0402_1% VSS VSS VSS VSS
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
PX@ T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
<22> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
CLKB0# 1 2 T1 T1 T1 T1
R345 56_0402_1% VSS VSS VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1
C481
1
1
0.01U_0402_16V7K J1 B1 J1 B1 J1 B1 J1 B1
PX@ R346 NC/ODT1 VSSQ R347 NC/ODT1 VSSQ R348 NC/ODT1 VSSQ R349 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
2
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1
PX@ L9 D8 PX@ L9 D8 PX@ L9 D8 PX@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
PX@ G9 G9 G9 G9
CLKB1 1 VSSQ VSSQ VSSQ VSSQ
2
R350 56_0402_1% 96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
PX@ K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
CLKB1# 1 2 X76@ X76@ X76@ X76@
R351 56_0402_1%
1
C482
0.01U_0402_16V7K
PX@
2
+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
B B
1
1
R352 R353 R354 R355 R356 R357 R358 R359
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
2
2
VREFD_Q1_B VREFC_A1_B VREFC_A2_B VREFD_Q2_B VREFC_A3_B VREFD_Q3_B VREFC_A4_B VREFD_Q4_B
C484
C485
C486
C487
C488
C489
C490
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
C483
0.1U_0402_16V7K
1 1 1 1 1 1 1
1
1 R361 R362 R364 R365 R366 R367 R363
R360 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% PX@ PX@ PX@ PX@ PX@ PX@ PX@
2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2
2
2
PX@
2
+1.5VGS
+1.5VGS
+1.5VGS +1.5VGS
C491
C492
C493
C494
C495
C496
C497
C498
C499
C500
C501
C502
C503
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C504
C505
C506
C507
C508
C509
C510
C511
C512
C513
C514
C515
C516
C517
C518
C519
C520
C521
C522
C523
C524
C525
C526
C527
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_SeymourXT_M2_VRAM_B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 23 of 51
5 4 3 2 1
5 4 3 2 1
E
E
R
O
M
+3VS +3VS_PS
30mil 30mil +SWR_VDD
R368 0_0603_5%
+3VS_PS
Close to Pin3 U22 U21
19 LVDS_ACLK <25> @ 8 1
+DP_V33 TXEC+ VCC A0
L27 2 1 +DP_V33 40mil 3 DP_V33 TXEC- 20 LVDS_ACLK# <25> 0_0402_5% 7 WP A1 2
FBMA-L11-201209-221LMA30T_0805 MIIC_SCL R621 1 2 MIIC_SCL_R 6 3
SCL A2
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z 60mil 13 21 LVDS_A2 <25> MIIC_SDA R622 1 2 MIIC_SDA_R 5 4
SWR_VDD TXE2+ SDA GND
Power
D D
1 1 1 L28 2 1 +SWR_VDD 18 22 0_0402_5%
LVDS
PVCC TXE2- LVDS_A2# <25>
FBMA-L11-201209-221LMA30T_0805 @ CAT24C64WI-GT3_SO8
C528
C529
C530
+SWR_V12 L29 1 2 +SWR_LX 60mil 12 23 LVDS_A1 <25>
4.7UH_PG031B-4R7MS_1.1A_20% SWR_LX TXE1+
2 2 2 60mil 11 SWR_VCCK TXE1- 24 LVDS_A1# <25>
27 VCCK
7 DP_V12 TXE0+ 25 LVDS_A0 <25>
TXE0- 26 LVDS_A0# <25>
+3VS_PS
Reserve for R01 as vender request
RTD2132S Pull high for EEPROM implementation
2
2 pull down for EEPROM free design @
<7> DP0_AUXP_C AUX_P
DP-IN
1 14 R372
GPIO
<7> DP0_AUXN_C AUX_N GPIO(PWM OUT) TL_INVT_PWM <25>
Close to L28 Close to Pin18 T70 GPIO(Panel_VCC) 15 TL_ENVDD <25> 4.7K_0402_5%
<7> DP0_TXP0_C 5 LANE0P GPIO(PWM IN) 16 APU_INVT_PWM <9>
+SWR_VDD 6 17 TL_BKOFF#_R
<7> DP0_TXN0_C
1
LANE0N GPIO(BL_EN) MIIC_SCL
T71
10U_0603_6.3V6M
0.1U_0402_16V4Z
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 For EC programming ROM CSCL 9 CIICSCL1 LVDS MIICSCL1 29 EDID_CLK <25>
2
CSDA 10 28
CIICSDA1 EDID MIICDA1 EDID_DATA <25>
C531
C532
C533
C534
C535
Other
R630
4.7K_0402_5%
2 2 2 2 2
<7> LVDS_HPD R882 1 2 LVDS_HPD_R 32 HPD ROM MIICSCL0 31 MIIC_SCL
1K_0402_5% 30 MIIC_SDA
1
MIICSDA0
8 DP_REXT
1
4 DP_GND GND 33
2
Close to Pin13 R377
100K_0402_5% R378 RTD2132S-GR_QFN32_5X5
12K_0402_1%
2
Version E
1
Close to L29 +1.2VS +3VS_PS
C @ L30 C
+SWR_V12 2 1 EDID_DATA R369 1 2 4.7K_0402_5%
0_0402_5% Change to 12Kohm 1% (DG ref.)
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
20101114 EDID_CLK R370 1 2 4.7K_0402_5%
1 1 1 1 20110124 Modify
C536
C537
C538
C539
MIIC_SDA R374 1 2 4.7K_0402_5%
2 2 2 2
CSCL R375 1 @ 2 4.7K_0402_5%
CSDA R376 1 @ 2 4.7K_0402_5%
Close to
Pin27
Close to Pin7
Vendor advise reserve it
R696 1 2 0_0402_5% ENBAKL <33>
TL_BKOFF#_R R623 1 @ 2 0_0402_5% TL_BKOFF# <25>
B C745 B
+3VS_PS 0.1U_0402_16V7K
1 2
5
2
P
B
Y 4
<25,33> BKOFF# 1 A
G
U38
3
MC74VHC1G08DFT2G SC70 5P
+3VS_PS
2
Q34A @
CSDA 1 6 EC_SMB_DA2
EC_SMB_DA2 <18,32,33>
DMN66D0LDW-7_SOT363-6
R878 1 2 0_0402_5%
5
Q34B @
CSCL 4 3 EC_SMB_CK2
A EC_SMB_CK2 <18,32,33> A
DMN66D0LDW-7_SOT363-6
R879 1 2 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator - RTD2132S
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Monday, November 07, 2011 Sheet 24 of 51
5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT +LCDVDD +5VALW
+3VS
1
R381 R382 W=60mils
150_0603_1% 100K_0402_5%
1 2
C546
D R383
3
4.7U_0603_6.3V6K
Q35 2 1 2 2
D 2N7002K_SOT23-3 G 2 D
S 220K_0402_5%
3
Q36
1 AP2301GN-HF_SOT23-3
1
1
C547
W=60mils
OUT
0.1U_0402_16V4Z
2 +LCDVDD +LCDVDD_CONN
L31
R389 1 2 0_0402_5% 2
<24> TL_ENVDD IN
1 2
GND
Q37 FBMA-L11-201209-221LMA30T_0805
1
DTC124EKAT146_SC59-3 1 1
3
C548 C549
R390 @ 4.7U_0603_6.3V6K
100K_0402_5% 0.1U_0402_16V4Z
2 2
2
@
R697 1 2 0_0402_5%
<33> EC_INVT_PWM
C C
R392 1 2 0_0402_5% INVTPWM
<24> TL_INVT_PWM
2
+LEDVDD B+
R395
100K_0402_5%
1 R822 2
1
1 1 0_0805_5%
@
C543 C542
680P_0402_50V7K 4.7U_0805_25V6-K
2 2
JLVDS1
1 1
2 2 G1 31
3 3 G2 32
4 4 G3 33
5 5 G4 34
6 6
DISPOFF# 7
INVTPWM 7
8 8
9 9
Reserve for R01 as vender request <24> LVDS_ACLK 10
R698 1 @ 10
<24,33> BKOFF# 2 0_0402_5% <24> LVDS_ACLK# 11 11
12 12
+3VS 13
T72 <24> LVDS_A2 13
@R399
@ R399 14
<24> LVDS_A2# 14
1 2 <24> LVDS_A1 15 15
B 10K_0402_5% B
<24> LVDS_A1# 16 16
R403 1 2 0_0402_5% 1 2 17
<24> TL_BKOFF# <24> LVDS_A0 17
R400 0_0402_5% T73 18
<24> LVDS_A0# 18
<24> EDID_DATA 19 19
1 2 DISPOFF# <24> EDID_CLK 20 20
+3VS 21 21
RB751V_SOD323 1 +LCDVDD_CONN 22
R402 1 22
2 10K_0402_5% D4 @ @ (60 MIL) 23 23
C544 +3VS 24
680P_0402_50V7K 24
25 25
2
+3VS_CMOS 26 26
<14> USB20_P3 USB20_P3 27
USB20_N3 27
<14> USB20_N3 28 28
29 29
30 30
ACES_88341-3001
CMOS Camera ME@
Q39
AP2301GN-HF_SOT23-3
+3VS 3 1 +CMOS_PW
CMOS@ 1
1
C554
0.1U_0402_16V4Z
2
R406 CMOS@
C780 C555 2
0_0603_5%
+3VALW 1 2 CMOS1 1 2 CMOS@
2
A A
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CMOS
@ CMOS@ 1
2
10U_0603_6.3V6M
R408 C556
10K_0402_5% CMOS@
CMOS@ 2
Security Classification Compal Secret Data Compal Electronics, Inc.
1
<33> CMOS_ON#
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 25 of 51
5 4 3 2 1
5 4 3 2 1
HDMIDAT_R
<7> HDMI_CLKP R410 HDMI@ 1 2 0_0402_5% HDMI_CLK+_CONN
<7> HDMI_CLKN R411 HDMI@ 1 2 0_0402_5% HDMI_CLK-_CONN
<7> HDMI_TX0P R412 HDMI@ 1 2 0_0402_5% HDMI_TX0+_CONN HDMICLK_R
<7> HDMI_TX0N R413 HDMI@ 1 2 0_0402_5% HDMI_TX0-_CONN
<7> HDMI_TX1P R414 HDMI@ 1 2 0_0402_5% HDMI_TX1+_CONN
<7> HDMI_TX1N R415 HDMI@ 1 2 0_0402_5% HDMI_TX1-_CONN
2
<7> HDMI_TX2P R416 HDMI@ 1 2 0_0402_5% HDMI_TX2+_CONN
<7> HDMI_TX2N R417 HDMI@ 1 2 0_0402_5% HDMI_TX2-_CONN D5 @
PJDLC05_SOT23-3
D D
1
+3VS ESD
EMI request
2
@L32
@ L32 R521
HDMI_CLKP 1 2 HDMI_CLK+_CONN @ C1025 1 2 10P_0402_50V8J 4.7K_0402_5%
1 2 HDMI@
2
1
HDMI_CLKN 4 3 HDMI_CLK-_CONN @ C1026 1 2 10P_0402_50V8J
4 3 HDMICLK_R
<7> HDMI_CLK 1 6
WCM-2012-900T_4P
DMN66D0LDW-7_SOT363-6
@L33
@ L33 Q41A
2
HDMI_TX0P 1 2 HDMI_TX0+_CONN @ C1027 1 2 10P_0402_50V8J HDMI@
1 2 R522
4.7K_0402_5%
5
HDMI_TX0N 4 3 HDMI_TX0-_CONN @ C1028 1 2 10P_0402_50V8J HDMI@
4 3
1
WCM-2012-900T_4P <7> HDMI_DATA 4 3 HDMIDAT_R
@L34
@ L34 DMN66D0LDW-7_SOT363-6
HDMI_TX1P 1 2 HDMI_TX1+_CONN @ C1029 1 2 10P_0402_50V8J Q41B
1 2 HDMI@
C HDMI_TX1N HDMI_TX1-_CONN @ C1030 C
4 4 3 3 1 2 10P_0402_50V8J
WCM-2012-900T_4P
@L35
@ L35
HDMI_TX2P 1 2 HDMI_TX2+_CONN @ C1031 1 2 10P_0402_50V8J
1 2
HDMI_TX2N 4 3 HDMI_TX2-_CONN @ C1032 1 2 10P_0402_50V8J
4 3
WCM-2012-900T_4P
@R429
@ R429
0_0805_5%
HDMI_CLK+_CONN 1 2 +5VS_HDMI_F 1 2 +5VS
R418 HDMI@ 604_0402_1%
HDMI_CLK-_CONN 1 2 RB491D_SC59-3
2
R419 HDMI@ 604_0402_1%
HDMI_TX0+_CONN 1 2 HDMI@ D7 HDMI@
R420 HDMI@ 604_0402_1% F1
HDMI_TX0-_CONN 1 2 1.1A_6V_SMD1812P110TF
R421 HDMI@ 604_0402_1%
1
HDMI_TX1+_CONN 1 2 +5VS +5VS_HDMI
R422 HDMI@ 604_0402_1% ESD
HDMI_TX1-_CONN 1 2 3 1 C557
R423 HDMI@ 604_0402_1% 0.1U_0402_16V4Z
2
HDMI_TX2+_CONN 1 2 1 HDMI_HPD HDMI@
B R424 HDMI@ 604_0402_1% HDMI@ HDMI@ B
HDMI_TX2-_CONN @ R430 R431 2
1 2 2
R425 HDMI@ 604_0402_1% D8 2K_0402_5% 2K_0402_5%
BAT54S-7-F_SOT23-3
D
1
1
+5VS 2 Q42
G 2N7002K_SOT23-3
1
S HDMI@
3
@ JHDMI1
R427 HDMI_HPD 19
100K_0402_5% HP_DET
18
NEAR CONNECTOR +3VS 17
+5V
2
HDMIDAT_R DDC/CEC_GND
16 SDA
HDMICLK_R 15 SCL
14 Reserved
13 CEC
HDMI_CLK-_CONN 12 20
CK- GND
2
11 CK_shield GND 21
R867 HDMI_CLK+_CONN 10 22
1K_0402_5% HDMI@ HDMI_TX0-_CONN CK+ GND
9 D0- GND 23
1
@ HDMI@ C R432 8
Q43 HDMI_HPD HDMI_TX0+_CONN D0_shield
2 1 2 7
1
MMBT3904_NL_SOT23-3 B 150K_0402_5% HDMI_TX1-_CONN D0+
6 D1-
E 5
3
D1_shield
2
<7> HDMI_DET HDMI_TX1+_CONN 4
@ HDMI_TX2-_CONN D1+
3 D2-
1
R433 2
HDMI@ 200K_0402_5% HDMI_TX2+_CONN D2_shield
1 D2+
R434
1
100K_0402_5% SUYIN_100042GR019M23DZL
ME@
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 26 of 51
5 4 3 2 1
A B C D E
FCM1608CF-121T03 0603
1 DAC_RED 1 2 RED 1
<13> DAC_RED
L36
FCM1608CF-121T03 0603
DAC_GRN 1 2 GREEN
<13> DAC_GRN
L37
FCM1608CF-121T03 0603 D2107 @
DAC_BLU 1 2 BLUE BLUE 6 3 RED
<13> DAC_BLU I/O4 I/O2
L38
1
+5VS
1 1 1 1 1 1
R435 R436 R437 C558 C559 C560 C561 C562 C563 5 2
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J VDD GND
2 2 2 2 2 2
2
2
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 4 1 GREEN
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
D2108 @
CRT_DDC_DATA 6 3 JVGA_HS
I/O4 I/O2
+CRT_VCC +5VS
R438
1 2 5 VDD GND 2
1
C564 1K_0402_5%
0.1U_0402_16V4Z CRT_DDC_CLK 4 1 JVGA_VS
2 2 I/O3 I/O1 2
5
AZC099-04S.R7G_SOT23-6
P
OE#
2 4 CRT_HSYNC_1 1 2 JVGA_HS
<13> CRT_HSYNC A Y L39
G
U23 FCM1608CF-121T03 0603
SN74AHCT1G125DCKR_SC70-5 1
3
@
C565
10P_0402_50V8J
+CRT_VCC 2
1
@
C566
0.1U_0402_16V4Z
2
5
1
P
OE#
2 4 CRT_VSYNC_1 1 2 JVGA_VS
<13> CRT_VSYNC A Y L40
G
U24 FCM1608CF-121T03 0603 1
SN74AHCT1G125DCKR_SC70-5 @
3
C567 +CRT_VCC
10P_0402_50V8J +5VS
2 D14
F2
2 1 1 2
3
1 3
RB491D_SC59-3
+CRT_VCC 1.1A_6V_SMD1812P110TF C568
0.1U_0402_16V4Z
2
1
R440 R441
4.7K_0402_5% 4.7K_0402_5%
JCRT1
2
6
11
RED 1
7
<13> CRT_DDC_DATA CRT_DDC_DATA CRT_DDC_DATA 12
GREEN 2
8 G 16
JVGA_HS 13 17
BLUE G
3
9
JVGA_VS 14
4
<13> CRT_DDC_CLK CRT_DDC_CLK 10
CRT_DDC_CLK 15
1 1 5
@ @ 1
C569 C570 C571 CONTE_80431-5K1-152
100P_0402_50V8J 68P_0402_50V8K ME@
2 2 100P_0402_50V8J
4 2 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 27 of 51
A B C D E
5 4 3 2 1
Switching Mode only
+3VALW +3V_LAN +LX
Close together
Layout Notice : Place as close L61 L62
R772 0_0402_5% L60
J11 chip as possible. +1.1_DVDDL 1 +LX_R
2 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
1000P_0402_50V7K
10U_0603_6.3V6M
4.7UH_SIA4012-4R7M_20% +1.1_AVDDL_L +1.1_AVDDL +1.1_DVDDL
0.1U_0402_16V4Z
1 1 2 2 1 2 1 2
@ C854
C855
C859
1U_0402_6.3V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
D 1 1 D
JUMP_43X79
Note: Place Close to LAN chip
C856
C857
C858
1 1 1
@
2 2 L39 DCR< 0.15 ohm
Atheros request can't disable LAN power Rate current > 1A
2 2 2
Place close to Pin34
Close to
Pin40
Vendor recommand reseve the
PU resistor close LAN chip
R773 1 2 4.7K_0402_5% U41 8162@ +3V_LAN
+3V_LAN
@ SA000050E00_S IC AR8161-AL3A-R QFN 40P E-LAN CTRL
<12,17,32> APU_PCIE_RST#
APU_PCIE_RST#
SA000052J10_S IC AR8162-AL3A-R QFN 40P E-LAN CTRL +AVDDH_AVDD3.3 R774 1 2 0_0402_5%
AR8162-AL3A-R
0.1U_0402_16V4Z
1U_0402_6.3V4Z
H --> Overclocking mode
L --> Not overclocking mode
C860
C862
1 1
C Overclocking mode stick C
2 1
Place Close to Chip U41 GIGA@ R881 @ 10K_0402_5%
2 2
<5> PCIE_CRX_DTX_N0 C861 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_N0 29 38 ACTIVITY
TX_N LED_0 ACTIVITY <29>
C863 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P0 30
Atheros LED_1 39
23
LAN_LINK#
LAN_CLK_SEL 2 1
LAN_LINK# <29>
<5> PCIE_CRX_DTX_P0 TX_P LED_2
AR8151/AR8161 R775 @ 10K_0402_5% Place close to Pin16
<5> PCIE_CTX_DRX_N0 36 RX_N For 48MHz CLK need to pull down,
12 MDI0-
TRXN0 MDI0+
MDI0- <29> keep floating for cystal
<5> PCIE_CTX_DRX_P0 35 RX_P TRXP0 11 MDI0+ <29>
15 MDI1-
TRXN1 MDI1- <29>
32 14 MDI1+
<12> CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ <29>
33 18 MDI2-
<12> CLK_PCIE_LAN REFCLK_P TRXN2 MDI2- <29>
17 MDI2+
TRXP2 MDI2+ <29>
APU_PCIE_RST# 2 21 MDI3-
PERST# TRXN3 MDI3- <29>
R777 1
@
2 0_0402_5% PCIE_WAKE#_R 3
TRXP3 20 MDI3+
MDI3+ <29> Place Close to PIN1
<14,32> FCH_PCIE_WAKE# WAKE#
<33> LAN_WAKE# R778 1 2 0_0402_5%
25 10 LAN_RBIAS 1 2 +3V_LAN
R780 1 SMCLK RBIAS
+3V_LAN 2 4.7K_0402_5% 26 SMDATA
R779 2.37K_0402_1%
Place Close to PIN1
@ 28 1 +3V_LAN
NC VDD33
1000P_0402_50V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V4Z
1U_0402_6.3V4Z
Vendor recommand reseve the 27 TESTMODE 1 1 1 1
1
C864
C865
C866
C867
C868
PU resistor close LAN chip +LX
LX 40 +LX
LAN_XTALO 7
2
@ LAN_XTALI XTLO R782 30K_0402_1% @ 2 2 2 @2
8 XTLI
+3V_LAN R781 1 2 4.7K_0402_5% 5 +1.7_VDDCT 1 2
VDDCT/ISOLAN +3VS
B B
<14> LAN_CLKREQ# 4 CLKREQ#
DVDDL/PPS 24
37 +1.1_DVDDL
+1.1_AVDDL DVDDL_REG/DVDDL
13 AVDDL
+1.1_AVDDL 19 +2.7_AVDDH
+1.1_AVDDL AVDDL +AVDDH_AVDD3.3
31 AVDDL AVDDH/AVDD33 16
+1.1_AVDDL_L 34 22 +2.7_AVDDH
+1.1_AVDDL AVDDL AVDDH +2.7_AVDDH
6 AVDDL_REG/AVDDL AVDDH_REG 9
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
C869
C870
C871
C872
C873
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 C874
C875
C876
C877
C878
41 GND 1 1 1 1 1
2 2 2 2 2 AR8161-AL3A-R_QFN40_5X5
2 2 2 2 2
Near
Near Near Near Near Pin9 Near Near
Pin13 Pin19 Pin31 Pin6 Pin22 Pin37
C879 @ 5P_0402_50V8
1 2 LAN_XTALI
<12> CLK_LAN_48M
Y3 LAN_XTALO
A
Place Close to C881 4 NC OSC 3 A
1 OSC NC 2
27P_0402_50V8J
27P_0402_50V8J
1 25MHZ_20PF_FSX3M-25.M20FDO 1
C881
C882
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-AR8151/8161
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Tuesday, November 08, 2011 Sheet 28 of 51
5 4 3 2 1
5 4 3 2 1
MDI3+
MDI3- Reserve for EMI go rural solution
T2
2 8162@
@ C883 MDI3+ 1 16 MDO3+ 1 R869 2 0_0603_5%
<28> MDI3+ TD+ TX+
0.1U_0402_16V4Z MDI3- MDO3- 1 R870 2 0_0603_5%
10
<28> MDI3- 2 TD- TX- 15
6
7
8
9
3 14 MCT3 8162@
D 1 CT CT D
4 13
6
7
8
9
10
NC NC
11 GND 5 NC NC 12
1 6 11 MCT2 8162@
RCLAMP3304N.TCT_SLP2626P10-10 MDI2+ CT CT MDO2+
<28> MDI2+ 7 RD+ RX+ 10 1 R871 2 0_0603_5%
D31 @
5
4
3
2
1
C884 MDI2- 8 9 MDO2- 1 R872 2 0_0603_5%
<28> MDI2- RD- RX-
@ 0.1U_0402_16V4Z 8162@ C885
5
4
3
2
1
2
1 2 1 2
BOTHHAND_NS0013LF R784 75_0603_5%
GIGA@ 1000P_1206_2KV7K
MDI2-
MDI2+
T1 2 1
Place Close to T2 2 DL1 LSE-200NX3216TRLF_1206-2
C886 MDI0+ 1 16 MDO0+ @
<28> MDI0+ TD+ TX+
MDI1- @ 0.1U_0402_16V4Z MDI0- 2 15 MDO0-
<28> MDI0- TD- TX-
3 CT CT 14 MCT0 Reserve gas tube for EMI go rural solution
1
4 NC NC 13 Place Close to T1,T2
MDI1+ 5 12
NC NC MCT1
1 6 CT CT 11
MDI1+ 7 10 MDO1+
<28> MDI1+ RD+ RX+
@ C887 MDI1- 8 9 MDO1-
<28> MDI1- RD- RX-
0.1U_0402_16V4Z
10
6
7
8
9
2
C C
BOTHHAND_NS0013LF
6
7
8
9
10
11 GND
RCLAMP3304N.TCT_SLP2626P10-10
D32 @
5
4
3
2
1
5
4
3
2
1
JRJ1
MDI0- 9
<28> LAN_LINK# Green LED-
MDI0+ +3V_LAN 2 R790 1 510_0402_5% 10 Green LED+
Place Close to T1 1
@ MDO0+ 1
C888 PR1+
470P_0402_50V7K MDO0- 2
2 PR1- @
MDO1+ 3 CHASSIS_GND C1034 1 2 470P_0603_50V8J
PR2+
MDO2+ 4 C1035 1 2 0.1U_0603_50V4Z
PR3+
MDO2- 5 C1036 1 2 1U_0603_25V6
PR3-
B MDO1- 6 B
PR2-
MDO3+ 7 14 CHASSIS_GND
PR4+ G2
MDO3- 8 13
PR4- G1
ACTIVITY 11
<28> ACTIVITY Yellow LED-
+3V_LAN 2 R793 1 510_0402_5% 12 Yellow LED+
CHASSIS_GND
1 SANTA_130452-D ME@
@
C889
470P_0402_50V7K
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_Transformer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Tuesday, November 08, 2011 Sheet 29 of 51
5 4 3 2 1
5 4 3 2 1
+3VS
CX20671
High Definition Audio Codec SoC
1
HDA_RST_AUDIO#
With Integrated Class-D Stereo
HDA_SYNC_AUDIO
EMI R837 @
4.7K_0402_5%
Amplifier.
HDA_SDOUT_AUDIO
An integrated 5 V to 3.3 V Low-dropout
2
voltage regulator (LDO). 1 R838
0_0402_5%
2 HDA_BITCLK_AUDIO HDA_RST_AUDIO#
An integrated 3.3 V to 1.8V Low-dropout 1 1 1 1
@
C990 @
1
voltage regulator (LDO).
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
C987
C988
C989
C991
100P_0402_50V8J
2
D 2 2 2 2 D
@ @ @ @
ESD Reserve
+3VS
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1
C978
C979
C980
+LDO_OUT_3.3V
+3VS 2 2 2
1U_0603_10V4Z
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
@ 1 1 1 1 AVDD_3.3 pinis output of
C983
C984
C985
C986
1 1 internal LDO. NOT connect
C981
C982
to external supply.
2 2 2 2
2 2 Layout Note:Path from +5VS to LPWR_5.0
RPWR_5.0 must be very low
resistance (<0.01 ohms)
R839 0_0402_5%
+3VS 1 2
1U_0603_10V4Z
0.1U_0402_16V4Z
+5VS
+3VALW 1R840 @ 2 0_0402_5% 1 1
C992
C993
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
+5VS
1 1 Sense resistors must be
C994
C995
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 2 10 mils 1 1 1 1
connected same power
that is used for VAUX_3.3
10U_0603_6.3V6M
C996
C999
C1000
C1001
0.1U_0402_16V4Z
@
2 2
1 1
C997
C998
@ @
2 2 2 2 R842 1 2 5.11K_0402_1% +3VS
0.1U_0402_16V4Z
C
2 2
Port B C
SENSE_A R843 2 20K_0402_1% MIC_JD Port A
18
29
27
28
26
1 1
3
7
2
C1002
U45 R844 1 2 39.2K_0402_1% PLUG_IN_R
VDD_IO
FILT_1.65
FILT_1.8
VAUX_3.3
DVDD_3.3
AVDD_3.3
AVDD_5V
AVDD_HP
@ Please bypass caps very close to device.
2
LPWR_5.0 12
15 +MICBIASB
HDA_RST_AUDIO# RPWR_5.0
<14> HDA_RST_AUDIO# 9 RESET# CLASS-D_REF 17
R845 2K_0402_5% R846 4.7K_0402_5%
HDA_BITCLK_AUDIO 5 2 A@ 1 2 A@ 1
<14> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 36 SENSE_A R847 0_0402_5%
<14> HDA_SYNC_AUDIO SYNC SENSE_A
<14> HDA_SDIN0
R841 1 2 33_0402_5%
HDA_SDOUT_AUDIO
6
4
SDATA_IN 1 2 2.2U_0603_6.3V4Z
@
R845 & R846 for App & Nokia combo ear phone un-pop
<14> HDA_SDOUT_AUDIO SDATA_OUT
35 C1003 1 2 R848 100_0402_1% EXT_MIC
PORTB_R EXT_MIC <35>
34 C1004 1 2
PORTB_L
PC_BEEP B_BIAS 33 +MICBIASB
2.2U_0603_6.3V4Z
External MIC
10 PC_BEEP
C_BIAS 32 +MICBIASC
31 MIC_INR
PORTC_R MIC_INL
<35> CX_GPIO0
0_0402_5% @ CX_GPIO0 PORTC_L 30 Internal MIC
<33> EAPD 1 2 R849 38 GPIO0/EAPD#
<33> EC_MUTE# 2 1 37 GPIO1/SPK_MUTE#
0_0402_5% R850 23 R852 1 2 15_0402_5%
PORTA_R HP_OUTR <35>
EAPD active low 22 R851 1 2 15_0402_5% Headphone
PORTA_L HP_OUTL <35>
0=power down ex AMP 40 DMIC_CLK
1=power up ex AMP 1 DMIC_1/2 NC 24 Changed from 5.1ohm to 15ohm
NC 25 for "zi zi"noise.
NC 39
SPK_L2+ 11
SPK_L1- LEFT+
13 LEFT-
Internal SPEAKER AVEE 21
FLY_P 19
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
SPK_R2+ 16 20 1 2
SPK_R1- RIGHT+ FLY_N C1005 1U_0603_10V4Z
14 RIGHT- 1 1
C1006
C1007
GND
B
@
2 2
Combo Jack detect (normal close) B
CX20671-21Z_QFN40_6X6 MIC_JD
41
Short GND and GNDA on
GND1 & GND2 on layout D
1
Q107 33K_0402_5%
R853 @ LBSS138LT1G_SOT-23-3 2 R854 1 2 EXT_MIC
1 2 G
1
0_0402_5% S
3
C1008 +5VS PLUG_IN_R
1
1U_0402_6.3V6K
2
R855
PLUG_IN_R 10K_0402_5%
GND GNDA D
1
2
R856 2 Q108
R857 47K_0402_5% <35> PLUG_IN 20K_0402_5% G 2N7002_SOT23
Place colose to Codec chip CX_GPIO0 1 2 S
3
1 @
C1011
PC Beep @
0.1U_0402_16V4Z
C1009 2
EC Beep <33> BEEP# 1 2
0.1U_0402_16V4Z +MICBIASC
R858
C1010 PC_BEEP1 PC_BEEP
ICH Beep <14> FCH_SPKR 1 2 1 2
1
33_0402_5%
0.1U_0402_16V4Z R860
close to Codec
1
2.2K_0402_5% JSPK1
@ SPK_R1- L70 1 2 FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN 1
R859 SPK_R2+ L71 FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 1
1 2 2
2
10K_0402_5% MIC1 SPK_L1- L72 FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN 2
1 2 3 3
1 C1012 1 2 2.2U_0603_6.3V4Z MIC_INR SPK_L2+ L73 1 2 FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN 4
2
GNDA 4
2
1 1 MIC_INL 5
wide 30MIL GND1
2
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
A WM-64PCY_2P 6 A
45@ @ @ @ @ GND2
1 1 1 1
C1013
C1014
C1015
C1016
ACES_88231-04001
2 2
Use SD028000080 (0ohm) for R01 ME@
C1017
C1018
(SM010016720 bead) 2 2 2 2 @ D41 D42 @
1
TVNST52302AB0 C/C SOT523 TVNST52302AB0 C/C SOT523
@ @
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CX20671 Codec
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Monday, November 07, 2011 Sheet 30 of 51
5 4 3 2 1
A B C D E F G H
HDD CONN BT MODULE CONN
JHDD1
1 GND
<13> SATA_FTX_DRX_P1 SATA_FTX_DRX_P1 2
SATA_FTX_DRX_N1 RX+
<13> SATA_FTX_DRX_N1 3 RX-
4 GND
C613 1 2 0.01U_0402_16V7K SATA_FRX_DTX_N1 5
<13> SATA_FRX_C_DTX_N1 C614 1 TX-
<13> SATA_FRX_C_DTX_P1 2 0.01U_0402_16V7K SATA_FRX_DTX_P1 6 TX+
7 GND
1 BT@ BT@ 1
R814 C929
100K_0402_5% 0.1U_0402_16V4Z
+5VS +5VS_HDD 1 2 1 2
<13> BT_ON#
8 3.3V
@ J10 9 +3VS_BT
+3VS 3.3V
1 1 2 2 10 3.3V
11 +3VS
GND
JUMP_43X79 12 GND
0_0603_5% 30mils
13 R815 BT@
GND
D
14 3 1 +3VS_BT_R 2 1
5V
+5VS_HDD 15 5V 1
16 Q81 0.1U_0402_16V4Z
5V PMV65XP_SOT23-3~D C930
G
17
2
GND BT@ BT@
18 Reserved 2
19 GND
+5VS_HDD +3VS 20 23 JBT1
12V GND
21 12V GND 24 1 1
22 12V 2 2
1 1 1 1 1 <14> USB20_P4 3 3
@ SUYIN_127043FB022G278ZR <14> USB20_N4 4 4
C615 C616 C617 C608 C620 ME@ BTON_LED:NC 5 5 G1 7
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V6K 10U_0603_6.3V6M 0.1U_0402_16V4Z <32> BT_ACTIVE 6 8
2 2 2 2 2 6 G2
ACES_87213-0600G
ME@
2 ODD CONN 15'' 2
JODD1
<13> SATA_FTX_C_DRX_P2 15@ C969 1 2 0.01U_0402_16V7K SATA_FTX_DRX_P2_15 1
15@ C968 1 1
<13> SATA_FTX_C_DRX_N2 2 0.01U_0402_16V7K SATA_FTX_DRX_N2_15 2 2
3 3
<13> SATA_FRX_C_DTX_N2
15@ C934 1 2 0.01U_0402_16V7K SATA_FRX_DTX_N2_15 4 4 short J12, no zero power ODD function
15@ C935 1 2 0.01U_0402_16V7K SATA_FRX_DTX_P2_15 5
<13> SATA_FRX_C_DTX_P2 @R819
@ R819 1 ODD_DETECT#_R 5
2 0_0402_5% 6 6
+5V_ODD 7 @ J12
R873 1 @ 7
<14> ODD_DETECT# 2 0_0402_5% 8 8 1 1 2 2
R820 1 @ 2 0_0402_5% ODD_DA#_R 9
<33> ODD_DA# 9 +5V_ODD
10 10 JUMP_43X79
+5VS
+3VS R821 1 @ 2 10K_0402_5% 11 GND
12 GND
D
3 1
@ Q46 2N7002_SOT23 1 1
1
ACES_87056-01001-001 Q82 @ @
@ PMV65XP_SOT23-3~D C936 C932
G
D
1 3
2
<14> ODD_DA#_FCH R817 @ 10U_0603_6.3V6M 0.1U_0402_16V4Z
ME@ 10K_0402_5% 2 2
@
G
2
2
1 R818 2
+3VS 100K_0402_5%
1
1
@
OUT
3 C937 3
0.01U_0402_16V7K
2
<13> ODD_EN 2 IN
ODD CONN 14''
GND
Q83
DTC124EKAT146_SC59-3
3
@
JODD2 ME@
1 GND
SATA_FTX_C_DRX_P2 14@ C967 1 2 0.01U_0402_16V7K SATA_FTX_DRX_P2_14 2
SATA_FTX_C_DRX_N2 14@ C966 1 SATA_FTX_DRX_N2_14 RX+
2 0.01U_0402_16V7K 3 RX-
4 GND
SATA_FRX_C_DTX_N2 14@ C965 1 2 0.01U_0402_16V7K SATA_FRX_DTX_N2_14 5
SATA_FRX_C_DTX_P2 14@ C964 1 TX-
2 0.01U_0402_16V7K SATA_FRX_DTX_P2_14 6 TX+
7 GND
ODD_DETECT#_R 8
+5V_ODD DP
9 +5V
10 +5V
ODD_DA#_R 11 MD
12 GND GND1 14
13 GND GND2 15
TYCO_2-1759838-8~D
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 31 of 51
A B C D E F G H
A B C D E
Mini-Express Card for WLAN/WiMAX(Half)
+1.5VS +3VS_WLAN +1.5VS
+3VS +3VS_WLAN
J5 1 1 1 1
1
@ @ @
1 2 J6 C627 C1023 C628 C629
1
1 2 4.7U_0603_6.3V6K
<14,28> FCH_PCIE_WAKE# R480 1 2 0_0402_5% WLAN_WAKE# JUMP_43X79 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
@
JUMP_43X79
2
<31> BT_ACTIVE R481 1 @ 2 0_0402_5%
@
JWLN1
2
1
1 WAKE# 3.3V 2 1
3 NC GND 4
R525 1 2 0_0402_5% 5 6 +1.5VS_WLAN
<13> BT_DISABLE# NC 1.5V
<14> WLAN_CLKREQ# 7 8 LPC_FRAME#_R
CLKREQ# NC LPC_AD3_R
9 GND NC 10
11 12 LPC_AD2_R
<12> CLK_PCIE_WLAN# REFCLK- NC
13 14 LPC_AD1_R
<12> CLK_PCIE_WLAN REFCLK+ NC
15 16 LPC_AD0_R
PCI_RST#_R GND NC
17 NC GND 18
CLK_PCI_DB 19 20
NC NC WL_OFF# <13>
21 GND PERST# 22 APU_PCIE_RST# <12,17,28>
23 24 R484 1 @ 2 0_0402_5% +3VALW
<5> PCIE_CRX_DTX_N1 PERn0 +3.3Vaux
25 26 R485 1 2 0_0402_5% +3VS_WLAN
<5> PCIE_CRX_DTX_P1 PERp0 GND
27 GND +1.5V 28
29 30 R486 1 2 @ 0_0402_5% FCH_SCLK0 <10,11,14>
GND SMB_CLK R487 1
<5> PCIE_CTX_DRX_N1 31 PETn0 SMB_DATA 32 2 @ 0_0402_5% FCH_SDATA0 <10,11,14>
<5> PCIE_CTX_DRX_P1 33 PETp0 GND 34
35 GND USB_D- 36 USB20_N2 <14>
+3VS_WLAN 37 38
NC USB_D+ USB20_P2 <14>
39 NC GND 40
41 NC LED_WWAN# 42
43 NC LED_WLAN# 44
100_0402_1% 45 46
R490 NC LED_WPAN#
47 NC +1.5V 48
<33,34> EC_TX_P80_DATA 1 2 49 NC GND 50
<33,34> EC_RX_P80_CLK 1 2 51 NC +3.3V 52
R491
100_0402_1% 53 54
GND GND
TAITW_PFPET0-AFGLBG1ZZ4N0
2
For EC to detect ME@
R492
debug card insert. 100K_0402_5%
1
2 2
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
LPC_FRAME#_R R493 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# <12,33>
LPC_AD3_R R494 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 <12,33>
LPC_AD2_R R495 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 <12,33>
LPC_AD1_R R496 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 <12,33>
LPC_AD0_R R497 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <12,33>
PCI_RST#_R R498 1 @ 2 0_0402_5% APU_PCIE_RST#
CLK_PCI_DB CLK_PCI_DB <12>
3 3
Close U33
REMOTE1+ +3VS
1 SMSC thermal sensor REMOTE1+
Close to DDR
1
1
1
C782
2200P_0402_50V7K +3VS placed near by VRAM R674
@
C783 2
C
Q72
2 REMOTE1- 100P_0402_50V8J B MMST3904-7-F_SOT323-3
10K_0402_5%
@ 2 E
3
U33 REMOTE1-
2
REMOTE2+ 1 10 EC_SMB_CK2 <18,24,33>
VDD SMCLK
1
@ REMOTE1+ 2 9 EC_SMB_DA2 <18,24,33>
C784 DP1 SMDATA
2200P_0402_50V7K
2
REMOTE1- 3 8 REMOTE2+
Under WLAN
2 REMOTE2- C785 DN1 ALERT#
1
1
0.1U_0402_16V4Z REMOTE2+ 4 7 @ C
1 DP2 THERM# C786 Q73 @
2
REMOTE2- 5 6 100P_0402_50V8J B MMST3904-7-F_SOT323-3
DN2 GND 2 E
3
REMOTE2-
EMC1403-2-AIZL-TR_MSOP10
Address 1001_101xb REMOTE1,2+/-:
Trace width/space:10/10 mil
Change from SA000029210 to SA000046C00 for main source Trace length:<8"
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini PCIE/Thermal IC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 32 of 51
A B C D E
+3VALW
+EC_AVCC +5VS
+3VLP
1 1 1 1 1 1
0.1U_0402_16V4Z
C632
0.1U_0402_16V4Z
C633
0.1U_0402_16V4Z
C634
0.1U_0402_16V4Z
C635
1000P_0402_50V7K
C637
1000P_0402_50V7K
C639
L45 1 2 TP_CLK R499 1 2 4.7K_0402_5%
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 1
TP_DATA R500 1 2 4.7K_0402_5%
C636 2 2 2 2 2 2
0.1U_0402_16V4Z C638
111
125
1000P_0402_50V7K U31
22
33
96
67
9
1 ECAGND 2
1 2
L46 FBM-11-160808-601-T_0603 BATT_TEMP 1 2
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
C641 100P_0402_50V8J
ACIN 1 2
C642 100P_0402_50V8J
<14> GATEA20 1 GATEA20/GPIO00 GPIO0F 21
2 23 BEEP#
<14> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <30>
<12> SERIRQ 3 SERIRQ GPIO12 26 NOVO# <35>
4 27 ACOFF
<12,32> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <41>
LPC_AD3 5 +5VALW
<12,32> LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output
<12,32> LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMP
<12,32> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <40>
@ LPC_AD0 10 LPC & MISC 64 USB_ON# R504 1 2 10K_0402_5%
<12,32> LPC_AD0 LPC_AD0 GPIO39
2 1 2 @ 1 65
ADP_I/GPIO3A ADP_I <40,41>
C640 22P_0402_50V8J R501 10_0402_5% 12 AD Input 66
<12,16> CLK_PCI_EC CLK_PCI_EC GPIO3B
13 75 BRDID +3VALW
<12> PLT_RST# PCIRST#/GPIO05 GPIO42
1 2 EC_RST# 37 76 Ra
+3VALW EC_RST# IMON/GPIO43 APU_IMON <47>
R502 47K_0402_5% EC_SCI# 20
<14> EC_SCI# EC_SCII#/GPIO0E
2 38 BRDID R505 1 2 100K_0402_5%
<40> BATT_LEN# GPIO1D
DAC_BRIG/GPIO3C 68
C643 70 R506 1 2 33K_0402_5%
0.1U_0402_16V4Z EN_DFAN1/GPIO3D
1
DA Output IREF/GPIO3E 71
KSI0 55 72 +3VALW Rb
KSI1 KSI0/GPIO30 CHGVADJ/GPIO3F
56 KSI1/GPIO31
KSI2 57 EC_MUTE# R503 1 2 10K_0402_5%
KSI3 KSI2/GPIO32
58 KSI3/GPIO33 EC_MUTE#/GPIO4A 83 EC_MUTE# <30>
KSI4 59 84 USB_ON# ID BRD ID Ra Rb Vab
KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# <35,36,37>
KSI5 60 85 INT#
KSI6 KSI5/GPIO35 CAP_INT#/GPIO4C
61 KSI6/GPIO36 PS2 Interface EAPD/GPIO4D 86 EAPD <30>
KSO[0..17] KSI7 62 87 TP_CLK 0 R10 MP x 0 0V
<35> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <35>
KSO0 39 88 TP_DATA
KSI[0..7] KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <35>
KSO1 40
<35> KSI[0..7] KSO2 KSO1/GPIO21
41 KSO2/GPIO22 1 R03 PVT 100K 8.2K 0.25V
KSO3 42 97
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE <47>
KSO4 43 98
KSO5 KSO4/GPIO24 WOL_EN/GPXIOA01
KSO6
44 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 99 VLDT_EN <44> 2 R02 DVT 100K 18K 0.5V
45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 NTC_V <40>
KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27
47 KSO8/GPIO28 3 R01 EVT 100K 33K 0.82V
KSO9 48 119
KSO10 KSO9/GPIO29 SPIDI/GPIO5B
49 KSO10/GPIO2A SPIDO/GPIO5C 120
KSO11 50 SPI Flash ROM 126
KSO12 KSO11/GPIO2B SPICLK/GPIO58
51 KSO12/GPIO2C SPICS#/GPIO5A 128
+3VALW KSO13 52 +3VS
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
KSO15 54 73 ENBAKL
KSO15/GPIO2F ENBKL/GPIO40 ENBAKL <24>
1
R507 1 @ 2 47K_0402_5% KSO1 KSO16 81 74 RST#
KSO17 KSO16/GPIO48 PECI_KB930/GPIO41
82 KSO17/GPIO49 FSTCHG/GPIO50 89
R508 1 @ 2 47K_0402_5% KSO2 90 R509
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <35>
91 CAPS_LED# 10K_0402_5%
CAPS_LED#/GPIO53 CAPS_LED# <35>
EC_SMB_CK1 77 GPIO 92
<40,41> EC_SMB_CK1 PWR_LED# <35>
2
+3VS EC_SMB_DA1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 EC_TACH
<40,41> EC_SMB_DA1 78 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 93 BATT_LOW_LED# <35>
EC_SMB_CK2_SUS 79 SM Bus 95 SYSON
<7> EC_SMB_CK2_SUS EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <38,43>
EC_SMB_DA2_SUS 80 121
<7> EC_SMB_DA2_SUS EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <47>
1
127 SUSP#
PM_SLP_S4#/GPIO59
1
R512 @
10K_0402_5% 6 100 C645
<14> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <14>
@ 14 101 EC_LID_OUT# @ 1000P_0402_50V7K
<14> PM_SLP_S5# EC_LID_OUT# <14>
2
EC_FAN_PWM EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 Turbo_V R757 2
<14> EC_SMI# 15 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 102 Turbo_V <40>
16 103 H_PROCHOT#_EC 2 1
<25> CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT <40>
17 104 0_0402_5%
GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <7,40,42>
18 GPO 105 BKOFF#
GPIO0C BKOFF#/GPXIOA08 BKOFF# <24,25>
19 GPIO 106 PBTN_OUT#
<31> ODD_DA# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <14>
<25> EC_INVT_PWM 25 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 107 H_PROCHOT# <7,40,47>
<34> EC_TACH 28 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 108 VGA_GATE# <14>
+3VALW EC_PME# 29 EC_PME#/GPIO15 D
1
EC_TX_P80_DATA 30
<32,34> EC_TX_P80_DATA EC_TX/GPIO16
R518 EC_SMB_CK1 EC_RX_P80_CLK 31 110 ACIN H_PROCHOT#_EC 2 Q109
<32,34> EC_RX_P80_CLK EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <18,41>
2.2K_0402_5% 32 112 EC_ON G 2N7002H_SOT23-3
<14,47> FCH_PWRGD PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <35,42>
<34> EC_FAN_PWM 34 114 ON/OFF <35> S
3
R519 EC_SMB_DA1 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 LID_SW#
36 NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 115 LID_SW# <35>
2.2K_0402_5% 116 SUSP#
SUSP#/GPXIOD05 SUSP# <38,44,46>
GPXIOD06 117
PECI_KB9012/GPXIOD07 118
AGND/AGND
+3VALW T68 XCLKI 122 +3VALW
XCLKO XCLKI/GPIO5D V18R
GND/GND
GND/GND
GND/GND
GND/GND
<12,16> RTC_CLK 1 2 123 XCLKO/GPIO5E V18R 124
R513 0_0402_5% 1
2
GND0
C646 R517
R523 R524 4.7U_0603_6.3V6K 10K_0402_5%
2
2
2.2K_0402_5% 2.2K_0402_5%
11
24
35
94
113
69
R516 C647
1
100K_0402_5% 20P_0402_50V8 KB9012QF A3 LQFP 128P_14X14 1 2 EC_PME#
2
<28> LAN_WAKE#
ECAGND
EC_SMB_CK2_SUS R520 0_0402_5%
EC_SMB_DA2_SUS
1
1 1
@ @ POP for susclk implemented
C650 C651 20100810 JCAP1
100P_0402_50V8J 100P_0402_50V8J 1
2 2 RST# 1
2 2
+3VS 3 3
EC_SMB_DA2 4
EC_SMB_CK2 4
5 5
6 6
INT# 7 7
+5VS 8 8
+3VS
9 GND1
10 GND2
+3VS
ACES_50521-0084N-P01
R886 R887 ME@
2.2K_0402_5% 2.2K_0402_5%
2
For Cap sensor function
EC_SMB_CK2_SUS 6 1 EC_SMB_CK2 <18,24,32>
5
Q113A
DMN66D0LDW-7_SOT363-6
EC_SMB_CK2_SUS
Security Classification Compal Secret Data Compal Electronics, Inc.
3 4 EC_SMB_DA2 <18,24,32> Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
Q113B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB9012/Cap sensor
DMN66D0LDW-7_SOT363-6 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 33 of 51
5 4 3 2 1
D D
FAN CONN
EC DEBUG PORT
+5VS
JFAN1 JECDP1
1 1 +3VALW 1 1
<33> EC_TACH 2 2 <32,33> EC_TX_P80_DATA 2 2
1 <33> EC_FAN_PWM 3 3 <32,33> EC_RX_P80_CLK 3 3
4 4 4 4
C626 5
10U_0603_6.3V6M G5 ACES_85205-0400
6 G6
2
ME@
ACES_85205-04001
ME@
C C
CPU VGA_L VGA_R
H1 H2 H3
HOLEA HOLEA HOLEA H4 H5
HOLEA HOLEA FD1 FD2 FD3 FD4
1
H_3P8 H_3P8 H_3P8
H_3P3 H_3P3
A B
M/B 橢圓孔 M/B 圓孔
H6 H7 H8 H9 H10 H11 H12 H13 H14 L R H17
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H15 H16 HOLEA
HOLEA HOLEA
B B
1
1
1
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_3P0X4P0N H_3P0X4P0N H_3P0N
D
2P8 * 9 pcd E
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN/SCREW/EC Debug
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 34 of 51
5 4 3 2 1
ON/OFF switch INT_KBD Conn.
KSI[0..7]
KSI[0..7] <33>
JKB1 FOR 14"
KSI1 1
+3VLP +3VALW KSO[0..17] KSO16 C938 1 KSI7 1
KSO[0..17] <33> 2 @ 100P_0402_50V8J 2 2
JKB2
KSI6 3 26
SW3 KSO17 C939 1 KSO9 3 GND2
2 @ 100P_0402_50V8J 4 4 25 GND1
SMT1-05_4P KSI4 5 5
2
1 3 KSO2 C940 1 2 @ 100P_0402_50V8J KSO1 C941 1 2 @ 100P_0402_50V8J KSI5 6 KSI1 24
KSO0 6 KSI7 24
7 23
Power Button 2 4 R701 R535 @ KSO15 C942 1 2 @ 100P_0402_50V8J KSO7 C943 1 2 @ 100P_0402_50V8J KSI2 8
7 KSI6 22
23
100K_0402_5% 100K_0402_5% KSI3 8 KSO9 22
9 9 21 21
KSO6 C944 1 2 @ 100P_0402_50V8J KSI2 C945 1 2 @ 100P_0402_50V8J KSO5 10 KSI4 20
6
5
1
KSO1 10 KSI5 20
11 11 19 19
R720 KSO8 C946 1 2 @ 100P_0402_50V8J KSO5 C947 1 2 @ 100P_0402_50V8J KSI0 12 KSO0 18
TOP Side J13
KSO2 13
12 KSI2 17
18
KSO13 C948 1 KSI3 KSO4 13 KSI3 17
1 2 1 2 2 @ 100P_0402_50V8J C949 1 2 @ 100P_0402_50V8J 14 14 16 16
0_0402_5% KSO7 15 KSO5 15
SHORT PADS KSO12 C950 1 KSO14 KSO8 15 KSO1 15
2 @ 100P_0402_50V8J C951 1 2 @ 100P_0402_50V8J 16 14
Bottom Side KSO6 17
16 KSI0 13
14
D24 @ KSO11 C952 1 KSI7 KSO3 17 KSO2 13
2 @ 100P_0402_50V8J C953 1 2 @ 100P_0402_50V8J 18 18 12 12
3 KSO12 19 KSO4 11
ON/OFF <33> 19 11
ON/OFFBTN# 1 KSO10 C954 1 2 @ 100P_0402_50V8J KSI6 C955 1 2 @ 100P_0402_50V8J KSO13 20 KSO7 10
KSO14 20 KSO8 10
2 51_ON# <39> 21 21 9 9
KSO3 C956 1 2 @ 100P_0402_50V8J KSI5 C957 1 2 @ 100P_0402_50V8J KSO11 22 KSO6 8
DAN202UT106_SC70-3 KSO10 22 KSO3 8
23 23 7 7
KSO4 C958 1 2 @ 100P_0402_50V8J KSI4 C959 1 2 @ 100P_0402_50V8J KSO15 24 KSO12 6
KSO16 24 KSO13 6
25 25 5 5
KSI0 C960 1 2 @ 100P_0402_50V8J KSO9 C961 1 2 @ 100P_0402_50V8J KSO17 26 KSO14 4
26 KSO11 4
27 27 3 3
KSO0 C962 1 2 @ 100P_0402_50V8J KSI1 C963 1 2 @ 100P_0402_50V8J 28 KSO10 2
D 28 2
1
29 31 KSO15 1
@ 29 GND 1
<33,42> EC_ON 2 30 30 GND 32
G Q106 CONN PIN define need double check Reserve for ESD. ACES_88514-2401
S 2N7002_SOT23-3 ACES_88514-3001 ME@
3
2
@ ME@
R641
10K_0402_5%
1
Power Button Board Conn. 8pin
+3VLP +3VALW
+5VALW
JPWRB1
2
ME@
R642
R532@ 100K_0402_5% 1
100K_0402_5% NOVO_BTN# 1
2 2
ON/OFFBTN# 3 5
1
D26 3 G1
4 4 G2 6
NOVO# 2
<33> NOVO#
2
1 NOVO_BTN# E-T_7182K-F04N-00R
3
R725
ON/OFF 10_0402_5%2 D25 @
DAN202UT106_SC70-3
PJSOT24C 3P C/A SOT-23
51_ON# 1 2
1
R722 @
0_0402_5%
IO board USB port
FOR 14" +USB_VCCA
J14 @
+USB_VCCB Card Reader/Audio Jack SB CONN
+5VALW +USB_VCCB 2 1
2MM JCR1
White LED1 14@ 0.1U_0402_16V4Z U42 check U40 ! <30> HP_OUTR 1
AN@ 1
1 GND VOUT 8 <30> HP_OUTL 2 2
<33> PWR_LED# PWR_LED# 1 2 2 R644 1 14@ +5VALW C1020 2 7 +5VS 2 R894 1 0_0402_5% CR_GND 3
300_0402_5% VIN VOUT 3
2 1 3 VIN VOUT 6 <30> EXT_MIC 4 4
<33,36,37> USB_ON# 4 EN FLG 5 USB_OC2# <14> 2 R895 1 0_0402_5% <30> PLUG_IN 5 5
19-213A-T1D-CP2Q2HY-3T_WHITE A@ +3VS 6 6
G547I2P81U_MSOP8 1 @ <14> USB20_N1 2 R687 1 0_0402_5% USB20_N1_R 7 7
BATT_LOW_LED# Orange LED2 14@ C1019
1000P_0402_50V7K
<14> USB20_P1 2 R686 1 0_0402_5% USB20_P1_R 8
9
8
BATT_LOW_LED# CR_GND 9
<33> BATT_LOW_LED# 1 2 2 R764 1 14@ +3VALW 10 10
2 +USB_VCCB
470_0402_5%
<14> USB20_N5 2 R534 1 0_0402_5% USB20_N5_R 11 11
2nd source SC500005910 S 2 R533 1 0_0402_5% USB20_P5_R 12
LED LTST-C191KFKT-5A 0603 ORANGE HT-191UD5_AMBER <14> USB20_P5 12
13 13
EMI request 14 14
BATT_CHG_LED# White LED5 14@
L47 @ L57 @
<30> CX_GPIO0
AN@ 2 R690
AN@ 2 R689
1 0_0402_5%
1 0_0402_5%
15
16
15
1 +MICBIASB 16
<33> BATT_CHG_LED# BATT_CHG_LED# 1 2 2 R765 1 14@ +5VALW USB20_N1 1 2 USB20_N1_R USB20_N5 1 2 USB20_N5_R 1
300_0402_5% 1 2 1 2 C734 + C733 A@ 2 R699 1 0_0402_5% 17 GND
220U_6.3V_M 470P_0402_50V7K A@ 2 R691 1 0_0402_5% 18 GND
19-213A-T1D-CP2Q2HY-3T_WHITE USB20_P1 4 4 3 3 USB20_P1_R USB20_P5 4 4 3 3 USB20_P5_R 6.3Φ * 5.9 2 2 ACES_51524-0160N-001
LED6 14@ WCM-2012-900T_4P WCM-2012-900T_4P SF000001500 ME@
White
<33> CAPS_LED# CAPS_LED# 1 2 2 R8 1 14@ +5VS
300_0402_5%
19-213A-T1D-CP2Q2HY-3T_WHITE
pin 6 5 4 3 2 1
+3VALW 1 R616 2
FOR 15" 14 VDD CLK DAT L R GND To TP/B Conn.
100K_0402_5% 15 VDD CLK DAT GND L R +5VS 2 R889 1 0_0402_5%
nonBBH@
LED B/D Conn BB-H VDD CLK DAT GND NC NC
+3VS 2 R890 1 0_0402_5% JTP1
2
JLED1 BB-L VDD CLK DAT GND L R BBH@ 8 GND
1 1 7
VDD
+5VALW 1 GND
14@ +3VALW 2
C716 2 C696 0.1U_0402_16V4Z
+5VS 3 3 6 6
0.1U_0402_16V4Z 3 LID_SW# LID_SW# 4 TP_CLK 5
2 OUTPUT LID_SW# <33> 4 <33> TP_CLK 5
5 TP_DATA 4
5 <33> TP_DATA 4
PWR_LED# 6 1 1 TP_3 3
GND
BATT_LOW_LED# 6 @ @ TP_2 3
2 7 7 2 2
14@ BATT_CHG_LED# 8 C697 C698 TP_1 1
Lid Switch C717 CAPS_LED# 9
8 100P_0402_50V8J 100P_0402_50V8J 1
1
10P_0402_50V8J SW_R 9 2 2 ACES_88058-060N
10 10
2
1
C541
C540
U37 14@ SW_L ME@
0.1U_0402_10V6K
0.1U_0402_10V6K
11 11
12 12 1 1
13 @ 15@
S-5711ACDL-M3T1S_SOT23-3 GND D15 TP_3
14 GND 2 R643 1
PSOT24C_SOT23-3 0_0402_5% @ @
ACES_88058-120N 2 2
1
ME@ 2 R619 1 TP_1
0_0402_5%
L R628 nonBBH@
R R626 nonBBH@
14@
0_0402_5% 0_0402_5%
SW4 14@ 2 1 TP_2 SW5 14@ 2 1 TP_1
SMT1-05_4P SMT1-05_4P
5
6
5
6
R629 14@ R627 14@
4 2 0_0402_5% 4 2 0_0402_5%
SW_L 2 1 TP_3 SW_R 2 1 TP_2
3 1 3 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/10/12 2013/10/12 Title
Issued Date Deciphered Date KBD/PWR/CR/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Monday, November 07, 2011 Sheet 35 of 51
A B C D E
unpop this MOS, need to short J14 !
1 1
+5VALW +USB_VCCA
@
U40
@ 1 8
C976 GND VOUT
2 VIN VOUT 7
2 1 0.1U_0402_16V4Z 3 VIN VOUT 6
<33,35,37> USB_ON# 4 EN FLG 5 USB_OC1# <14>
G547I2P81U_MSOP8
1 @
C977
1000P_0402_50V7K
2
2 2
Right Ext.USB FFC Conn.
+USB_VCCA
W=80mils JUSB4
+USB_VCCA 1
R835 2 1
1 <14> USB20_N0 1 0_0402_5% USB20_N0_R 2 2
1 R836 2 1 0_0402_5% USB20_P0_R 3 5
+ <14> USB20_P0 3 G1
C974 4 6
220U_6.3V_M C975 4 G2
2
470P_0402_50V7K E-T_7182K-F04N-00R
2 2
3 6.3Φ * 5.9 ME@ 3
SF000001500
D40 @
1
WCM-2012-900T_4P PJDLC05_SOT23-3
USB20_P0 4 3 USB20_P0_R
4 3
USB20_N0 1 2 USB20_N0_R
1 2
L69
Update to SM070001S00 for EMI request
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB cable port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Monday, November 07, 2011 Sheet 36 of 51
A B C D E
5 4 3 2 1
For EMI/ESD request
@ D23
D22
U3RXDN1 9 10 1 1U3RXDN1 @
U2DP1 3 6
U3RXDP1 8 9 2 2U3RXDP1 I/O2 I/O4
U3TXDN1 7 7 4 4U3TXDN1
D +5VALW +USB3_VCCA +USB3_VCCA D
W=80mils 2 GND VDD 5 +5VALW
U3TXDP1 6 6 5 5U3TXDP1
C692 U39
0.1U_0402_16V7K 1 8 3 3
GND VOUT
C748
C749
470P_0402_50V7K
1 2 2 7 1 4 U2DN1
VIN VOUT 8 I/O1 I/O3
3 VIN VOUT 6 1
220U_6.3V_M
<33,35,36> USB_ON# 4 EN FLG 5 USB_OC0# <14> 1 AZC099-04S.R7G_SOT23-6
+
G547I2P81U_MSOP8 1 @ YSCLAMP0524P_SLP2510P8-10-9
C1024
1000P_0402_50V7K 2 2 @ D29
2A/Active Low D30
U3RXDN2 9 10 1 1U3RXDN2 @
2 U2DP2 3 I/O2 I/O4 6
U3RXDP2 8 9 2 2U3RXDP2
U3TXDN2 7 7 4 4U3TXDN2
2 GND VDD 5 +5VALW
U3TXDP2 6 6 5 5U3TXDP2
3 3
1 4 U2DN2
8 I/O1 I/O3
AZC099-04S.R7G_SOT23-6
C C
YSCLAMP0524P_SLP2510P8-10-9
<14> USB30_N10 <14> USB30_N11
<14> USB30_P10 <14> USB30_P11
C847 1 2 U3TXDP1_L C848 1 2 U3TXDP2_L WCM-2012-900T_4P WCM-2012-900T_4P
<14> USB30_FTX_DRX_P0 <14> USB30_FTX_DRX_P1
0.1U_0402_16V7K 0.1U_0402_16V7K U3TXDN1_L 1 2 U3TXDN1 U3TXDN2_L 1 2 U3TXDN2
C849 1 U3TXDN1_L C850 1 U3TXDN2_L 1 2 1 2
<14> USB30_FTX_DRX_N0 2 <14> USB30_FTX_DRX_N1 2
0.1U_0402_16V7K 0.1U_0402_16V7K
U3TXDP1_L 4 3 U3TXDP1 U3TXDP2_L 4 3 U3TXDP2
<14> USB30_FRX_DTX_P0 <14> USB30_FRX_DTX_P1 4 3 4 3
L49 @ L53 @
<14> USB30_FRX_DTX_N0 <14> USB30_FRX_DTX_N1
WCM-2012-900T_4P WCM-2012-900T_4P
USB30_FRX_DTX_N0 1 2 U3RXDN1 USB30_FRX_DTX_N1 1 2 U3RXDN2
LP1 LP2 1 2 1 2
USB30_FRX_DTX_P0 4 3 U3RXDP1 USB30_FRX_DTX_P1 4 3 U3RXDP2
+USB3_VCCA +USB3_VCCA 4 3 4 3
W=80mils W=80mils L50 @ L54 @
B B
JUSB2 JUSB3 WCM-2012-900T_4P WCM-2012-900T_4P
U3TXDP1 9 U3TXDP2 9 USB30_N10 1 2 U2DN1 USB30_N11 1 2 U2DN2
SSTX+ SSTX+ 1 2 1 2
1 VBUS 1 VBUS
U3TXDN1 8 U3TXDN2 8
U2DP1 SSTX- U2DP2 SSTX- USB30_P10 4 U2DP1 USB30_P11 U2DP2
3 D+ 3 D+ 4 3 3 4 4 3 3
7 GND 7 GND
U2DN1 2 10 U2DN2 2 10 L51 @ L55 @
U3RXDP1 D- GND U3RXDP2 D- GND
6 SSRX+ GND 11 6 SSRX+ GND 11
4 GND GND 12 4 GND GND 12
U3RXDN1 5 13 U3RXDN2 5 13 U3TXDP1_L 1 R544 2 U3TXDP1 U3TXDP2_L 1 R631 2 U3TXDP2
SSRX- GND SSRX- GND 0_0402_5% 0_0402_5%
TAITW_PUBAU1-09FNLSCNN4H0 TAITW_PUBAU1-09FNLSCNN4H0 U3TXDN1_L 1 R545 2 U3TXDN1 U3TXDN2_L 1 R632 2 U3TXDN2
ME@ ME@ 0_0402_5% 0_0402_5%
USB30_FRX_DTX_P0 1 R546 2 U3RXDP1 USB30_FRX_DTX_P1 1 R633 2 U3RXDP2
0_0402_5% 0_0402_5%
USB30_FRX_DTX_N0 1 R547 2 U3RXDN1 USB30_FRX_DTX_N1 1 R634 2 U3RXDN2
0_0402_5% 0_0402_5%
USB30_P10 1 R550 2 U2DP1 USB30_P11 1 R635 2 U2DP2
0_0402_5% 0_0402_5%
USB30_N10 1 R551 2 U2DN1 USB30_N11 1 R636 2 U2DN2
0_0402_5% 0_0402_5%
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Left USB3.0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 37 of 51
5 4 3 2 1
A B C D E
+5VALW TO +5VS +3VALW TO +3VS +1.5V to +1.5VS
+1.5V Q55 +1.5VS
+5VALW U34 +5VS +3VALW U35 +3VS 3 1
DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8 1 1 1
1
8 1 8 1 @
1 7 2 1 1 1 7 2 1 1 C699 AP2301GN-HF_SOT23-3 C700 C701
1
6 3 6 3 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V6K R581
2
C702 C703 C704 C705 C706 C707 2 2 2 470_0603_5%
5 5
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V6K R582 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V6K R583 @
2
1 2 2 2 470_0603_5% 2 2 2 470_0603_5% 1
4
@ @
D
1 2
1 2
1
+VSB +VSB +5VALW
D D
2 SUSP
1
2 SUSP 2 SUSP G
1
G G S Q58
3
S Q56 R585 S Q57 2N7002_SOT23
3
R584 2N7002_SOT23 47K_0402_5% 2N7002_SOT23 100K_0402_5% @
20K_0402_5% @ @ R586
R588
2
5VS_GATE2 R587 15VS_GATE_R 3VS_GATE 2 R668 1 3VS_GATE_R 1.5VS_GATE 1 21.5VS_GATE_R
2
2
10K_0402_5% 1 1 75K_0402_5% 1 1
D D D
1
1
R688 10K_0402_5% R589 @
SUSP 2 Q59 0_0402_5% C708 SUSP 2 0_0402_5% C709 SUSP# 2 Q61 C710 C711
G 2N7002K_SOT23-3 @ 0.1U_0603_25V7K G Q60 @ 0.1U_0603_25V7K G 2N7002K_SOT23-3 0.1U_0402_25V6
S 2 S 2N7002K_SOT23-3 2 S 2 2
3
3
0.1U_0603_25V7K
+1.1VALW to +1.1VS
+1.1VALW U36 +1.1VS +RTCBATT +5VALW
DMN3030LSS-13_SOP8L-8 +5VALW
8 1
1
1 7 2 1 1
1
2 6 3 @ 2
C712 5 C713 C714 R591 R592 @
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V6K R590 100K_0402_5% 100K_0402_5% R593
2 2 2 470_0603_5% 100K_0402_5%
4
2
@ SUSP
<45> SUSP
2
2
SYSON#
Q63
D 1
1
+VSB DTC124EKAT146_SC59-3
2 SUSP
OUT
OUT
G
1
S Q62 Q64
3
2N7002_SOT23 2 SYSON 2 DTC124EKAT146_SC59-3
75K_0402_5% <33,44,46> SUSP# IN <33,43> SYSON IN
@ @
GND
GND
R594
2
1.1VS_GATE 2 R669 1 1.1VS_GATE_R
3
2
D 1
1
10K_0402_5% R596
SUSP 2 0_0402_5% C715
G Q65 @ 0.1U_0603_25V7K
S 2N7002K_SOT23-3 2
3
3 3
+1.5V +0.75VS
1
R597 R598
470_0603_5% 470_0603_5%
@ @
1 2
1 2
D D
2 SYSON# 2 SUSP
G G
S Q66 S Q67
3
2N7002_SOT23 2N7002_SOT23
@ @
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Tuesday, November 08, 2011 Sheet 38 of 51
A B C D E
5 4 3 2 1
DC030006J00 VIN
PF101 PL101
7A_24VDC_429007.WRML SMB3025500YA_2P
4 APDIN 1 2 APDIN1 1 2
4
3 3
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
2 2
1
D D
1 1
2
4602-Q04C-09R 4P P2.5
PC101
PC102
PC103
PC104
JDCIN1
ME@
Unpop for KB9012 VIN
LL4148_LL34-2
2
PD103 @
@PD104
@ PD104 PJ101
1
LL4148_LL34-2 @ JUMP_43X39 51ON-1
C
BATT+ 2 1 1 1 2 2
C
1
68_1206_5%
68_1206_5%
PR118
PR119
@ PQ104
@PQ104
TP0610K-T1-E3_SOT23-3
@ PR120 @ @
2
200_0603_5%
CHGRTCP 1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
100K_0402_1%
0.1U_0603_25V7K
1
PR123 @
1
@ PC112
PC113
1
2
@PR124
@ PR124 @
2
22K_0402_1%
1 2 51ON-3
+3VLP <35> 51_ON#
2
0_0402_5%
PR127
RTCVREF
1
200_0603_5%
@ PR128
@ PU102
1
APL5156-33DI-TRL_SOT89-3
3.3V
2
3 VOUT VIN 2CHGRTCIN
10U_0603_6.3V6M
1U_0805_25V6K
1
GND
@ PC114
@ PC115
B B
1
2
+CHGRTC
- JRTC2 + PR131
560_0603_5%
PR132
560_0603_5%
PD109
RB751V-40_SOD323-2
2 1 1 2 1 2 2 1 +RTCBATT
@ MAXEL_ML1220T10 1 2
RTCVREF
PD108
RB751V-40_SOD323-2
RTC Battery
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / Vin Detector /Pre-charge
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 39 of 51
5 4 3 2 1
5 4 3 2 1
VMB2 VMB
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 1 2 1 2 BATT+
2 2
3 EC_SMCA
3 EC_SMDA
4 4
5 5
1
6 6
1
7 PC201 PC202
7
100_0402_1%
100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K
2
D GND D
GND 9
PR201
PR202
TYCO_1775789-1
ADP_I need to write Charge Options Register (0x12H)=> bit6=1
2
2
@
0: IOUT is the 20x current amplifier output <default @ POR>
JBATT2
1: IOUT is the 40x current amplifier output
1 1
2 2 EC_SMB_CK1 <33,41> For KB930 --> Keep PU201 circuit
3 3
PH1 under CPU botten side :
4 4 (Vth = 0.825V)
5 5 EC_SMB_DA1 <33,41> CPU thermal protection at 93 +-3 degree C
6 6
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
7 7
Recovery at 56 +-3 degree C
GND 8
9
1
PR203
2 +3VALW PH201, PR205, PR211,PQ201,PR208,PR212
GND 6.49K_0402_1%
TYCO_1775789-1 VL
@
1 2
+3VLP
BATT_TEMP <33> A/D <33,41> ADP_I
21.5K_0402_1%
PR204
90W(DIS) : 6.65K
1
6.65K_0402_1%
12.7K_0402_1%
10K_0402_5%
PR207
65W(UMA) : 1.65K
PR205
PR206
1
@PC203
@ PC203 +3VS @
2
0.1U_0603_16V7K @ PU201
2
1 VCC TMSNS1 8 NTC_V
100K_0402_1%
C OTP_N_002 C
2 GND RHYST1 7 2 1
PR208
@ PR209
3 6 Turbo_V 10K_0402_1%
<7,33,47> H_PROCHOT# OT1 TMSNS2 PR210
@ ADP_OCP_2 1
100K_0402_1%_NCP15WF104F03RC
4 5 2
1
OT2 RHYST2
PH201
@ PQ201
D
10K_0402_1%
G718TM1U_SOT23-8 @ 29.4K_0402_1%
PR211
2ADP_OCP_1
OTP_N_003
Turbo_V
<33>
<33>
NTC_V
G
S SSM3K7002FU_SC70-3
2
1
PR212
@ 0_0402_5%
<33> PROCHOT 1 2 2 1 MAINPWON <7,33,42>
@ PR213 0_0402_5%
B B
P2
PQ205
+3VLP +3VALW
0.01U_0402_25V7K
TP0610K-T1-E3_SOT23-3
1
PC204
B+ 3 1 +VSBP
2
VMB2
100K_0402_1%
0.22U_0603_25V7K
PR214 PR215
2
1
100K_0402_1% 100K_0402_1%
1
PR216
PC205
PR217 PR218 <BOM Structure>
2
768K_0402_1% 10M_0402_5% PC206
1
1 2 0.1U_0603_25V7K
BATT_OUT <41>
2
PR219
2
10K_0402_1% PR220
8
1 2 PQ202 VL 22K_0402_1%
D 2N7002KW_SOT323-3
1
3 1 2
P
+
O 1 2
2
PR221 2 G
-
2
221K_0402_1% PU202A S PR222
3
LM393DG_SO8 100K_0402_1%
4
+3VLP PR224
D
1
PQ203 1K_0402_5% PJ201
D 2N7002KW_SOT323-3
1
1 2 2 PQ204 @ JUMP_43X39
<42,44> SPOK
2 1 2 G 2N7002W-T/R7_SOT323-3 1 1
2VREF_8205 +VSBP 2 2 +VSB
2
G
1U_0402_6.3V6K
S
3
1
PC207
PR223 PR226 S
3
10K_0402_1% 100K_0402_1%
2 1 RTCVREF
2
1
A @PR225
@ PR225 A
10K_0402_1%
<33> BATT_LEN#
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 40 of 51
5 4 3 2 1
5 4 3 2 1
P3
B+ Need EC write ChargeOption() bit[8]=0
P2
Setting (ACP to PHASE Rising Threshold)=1350mV(min)
PQ301 PQ302
AO4407A_SO8 SI4459_SO8
PR302
VIN 8 1 1 8
0.01_1206_1% B+
7
6
2
3
2
3
7
6
SH00000AA00
5 5 1 2 1 4 PQ303
AO4407A_SO8
PL301 2 3 1 8
4
1UH_PCMB061H-1R0MS_7A_20% 2 7
10U_0805_25V6K
10U_0805_25V6K
3 6
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
D
PQ304 5 D
47K_0402_5%
1 2
1
2
200K_0402_1%
0.1U_0603_25V7K
PC307
4
1
PR301
PC302
PC315
PC303
PC305
PC306
DTA144EUA_SC70-3 PC304 DISCHG_G
PC301
PR303
5600P_0402_25V7K
1
PR304
47K_0402_1%
2
2
2 1 2
2
ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR305
1DISCHG_G-1
10K_0402_1%
1
2
PD301
0.1U_0603_25V7K
P2-1 PR306
1
2 200K_0402_1%
PQ305 PQ306
1
+3VALW PC308 PC309 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3 +3VALW
PR307 <42> ACPRN PD302
1 2 2 1
3
20K_0402_1% 1SS355_SOD323-2
100K_0402_1%
1 2 0.1U_0603_25V7K 2 1 2
6
10K_0603_1%
PQ308
D
1
1
150K_0402_1%
2N7002KW_SOT323-3 PC310 PQ309
2
PR308
PR309
PR310
PQ307A 2 BATT_OUT <40>
2 2N7002KDW-2N_SOT363-6 G 0.1U_0603_25V7K P2 2N7002W-T/R7_SOT323-3
D
1
0.1U_0603_25V7K
S
3
@ 2 1 2 PACIN
PR313
1
1
PC311
VIN @PR312
@ PR312 @ @ G
1
10K_0402_5%
10K_0402_5%
2 1 1 2 S
3
2
2
390K_0603_1% 4.7M_0603_1%
2
1
P2-2
10_1206_5%
PR315
PR316
39.2K_0402_1%
5
6
7
8
C C
PR314
2N7002KDW-2N_SOT363-6
PQ310
AO4466L_SO8
PR319
3
PQ307B
@ @ <BOM Structure>
ACOK
CMPOUT
CMPIN
ACP
ACN
1
1
PR318 <33,40> ADP_I
2
47K_0402_1% PR317 21
1
PACIN 1 TP
PACIN 2 5 1 2 6 ACDET PC313 4
SH000005Y80
1
64.9K_0603_1% PC312 20 BQ24727VCC1 2
4
PC323 VCC PL302
ACON 1 2 7 IOUT
0.1U_0603_25V7K 4.7UH_PCMB104E-4R7MS_10A_20% PR320
2
3
2
1
1U_0603_25V6K
1
PQ311 100P_0603_50V8 19 0.01_1206_1%
PHASE
DTC115EUA_SC70-3 <33,40> EC_SMB_DA1 8 SDA
PU301 BATT+
BQ24727RGRR_VQFN20_3P5X3P5 LX_CHG 1 2 CHG
1 4
PR321 18 DH_CHG
HIDRV
5
6
7
8
2ACOFF-12 <33,40> EC_SMB_CK1
<33> ACOFF 1 9 SCL SA000051W00 2 3
1
PQ312
AO4466L_SO8
4.7_1206_5%
10K_0402_5% PR324 PC314
PR322
PR323 2.2_0603_5% 0.047U_0603_25V7M
1
10U_0805_25V6K
10U_0805_25V6K
1 2 10 17 BST_CHG 1 2 2 1 SRP SRN
ILIM BTST
1
16251_SN
PR325 +3VALW 316K_0402_1%
PD303
3
0_0402_5% PR326 4
LODRV
1
PC316
PC317
100K_0402_1% 16 2 1
GND
SRN
SRP
REGN
2N7002KW_SOT323-3
BM
2
2
RB751V-40_SOD323-2
680P_0603_50V7K
PQ313
D 11
1 12
13
14
15
3
2
1
1
1
10_0603_5%
PC319
6.8_0603_5%
2
PR328
2 PC318
<40> BATT_OUT BQ24727VDD
PR327
G 1U_0603_25V6K
2
S
3
2
2
PC320 DL_CHG
B 0.1U_0603_25V7K B
2 1
CHGVADJ=(Vcell-4)/0.10627
1
Vcell CHGVADJ
1
PC321
4V 0V 0.1U_0603_25V7K @PC322
2
2 0.1U_0603_25V7K
4.2V 1.882V
4.35V 3.2935V
BQ24727VDD
CC=0.25A~3A PR337
10K_0402_1%
1
IREF=1.016*Icharge PR336
1 2 ACIN <18,33>
IREF=0.254V~3.048V PR335 10K_0402_1%
47K_0402_1%
VCHLIM need over 95mV PACIN
2
1 2
ACPRN <42> PR339
2
12K_0402_1%
2
PQ316
A DTC115EUA_SC70-3 A
3
For disable pre-charge circuit.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 41 of 51
5 4 3 2 1
5 4 3 2 1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205 PJ402
+3VALWP 2 2 1 1 +3VALW
@ JUMP_43X118
1U_0603_10V6K
D D
1
PC401
PJ403
+5VALWP 2 1 +5VALW
2
2 1
@ JUMP_43X118
PR401 PR402
13K_0402_1% 30K_0402_1%
1 2 1 2
PR403 PR404
RT8205_B+ 20K_0402_1% 19.6K_0402_1% RT8205_B+
1 2 1 2
PJ401 Typ: 175mA
B+
0.1U_0603_25V7K
2 2 1 1 +3VLP
ENTRIP2
ENTRIP1
2200P_0402_50V7K
2200P_0402_50V7K
PC405
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0603_25V7K
@ JUMP_43X118 PR405 PR406
1
130K_0402_1% 66.5K_0402_1%
PC402
PC410
4.7U_0805_10V6K
1 2 1 2
1
1
PC403
PC404
PC406
PC407
PC408
PC409
2
8
7
6
5
5
6
7
8
PU401
2
2
PC411
ENTRIP2
REF
FB2
FB1
ENTRIP1
TONSEL
1
TPC8065-H_SO8
C PQ401 C
PQ402
25 P PAD
AO4466L_SO8
2
4 4
7 VO2 VO1 24
SPOK <40,44>
8 23 PR408 PC413
PR407 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3
3
2
1
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
PL401 PC412
2.2_0603_5%
UG_3V 10
VFB=2.0V 21 UG_5V PL402
4.7UH +-20% PCMC063T-4R7MN 5.5A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_PCMB104E-4R7MS_10A_20%
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
8
7
6
5
1
4.7_1206_5%
4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
5
6
7
8
PR409
PR410
PQ403
SKIPSEL
AO4712_SO8
VREG5
PQ404
GND
VIN
RT8205EGQW_WQFN24_4X4
NC
EN
1 1
2
2
4
+ PC415 4 + PC417
13
14
15
16
17
18
1
1
680P_0603_50V7K
TPC8A03-H_SO8
150U_B2_6.3VM_R45M PR411 150U_B2_6.3VM_R45M
680P_0603_50V7K
499K_0402_1%
2 2
PC418
PC419
1 2
2
1
2
3
2
B+
3
2
1
1
100K_0402_1%
1U_0603_10V6K
VL
1
PC420
1
Typ: 175mA
PR412
PC421
4.7U_0805_10V6K
B B
2
ENTRIP1 ENTRIP2
2
2
For KB9012 RT8205_B+
<33,35> EC_ON
6
PR418
1
10K_0402_5% PQ405B
0.1U_0603_25V7K
2 1 PQ405A 2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6 2 5 2VREF_8205 +3.3VALWP OCP(min)=5.81A
2
PC422
+5VALWP OCP(min)=8.44A
<7,33,40> MAINPWON
1
PR413
0_0402_5%
2 1
PR414
100K_0402_1%
VL 2 1
1
2N7002W-T/R7_SOT323-3
@ PR415
D
1
200K_0402_1%
<41> ACPRN 2 1 2 1 2 2 PQ406
G VS DTC115EUA_SC70-3
PQ407
40.2K_0402_1%
4.7U_0603_6.3V6M
S @ PR416
3
A A
1
100K_0402_1%
1
1
PR417
PC423
@
2
<33,35> EC_ON @
2
2
@ PQ408
DTC115EUA_SC70-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
For KB9012 3VALWP/5VALWP
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 42 of 51
5 4 3 2 1
A B C D
PJ501
1.5V_B+ 2 2 1 1 B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5
6
7
8
@ JUMP_43X118
1
PC502
PC503
PC504
PC505
PQ501
TPC8065-H_SO8
2
4
3
2
1
1
PR503 PC506 PL501 1
100K_0402_1% PU501 0_0603_5% 0.22U_0603_16V7K 1UH_PCMC063T-1R0MN_11A_20%
PR505 1 PGOOD VBST 10 BST_1.5V 1 2BST_1.5V-1 1 2 1 2 +1.5VP
PR501 2 1 2 9 DH_1.5V
0_0402_5% TRIP DRVH
4.7_1206_5%
1 2 3 8 LX_1.5V
EN SW
1
<33,38> SYSON 1
5
6
7
8
PR504
4 VFB V5IN 7 +5VALW
2
+
47K_0402_5%
.1U_0402_16V7K
PQ502 PC507
1
PC501 @
PR502
1 PR5062 5 6 DL_1.5V 220U_6.3V_M +1.5VP OCP(min)=15.6A
RF DRVL
1
PC508
2
470K_0402_1% 1U_0603_10V6K 2
PR507 11
2
TP
1000P_0603_50V7K
4 PJ502
1
2 1 2 TPS51212DSCR_SON10_3X3 2 2 1 1
PC509
VFB=0.7V
@ JUMP_43X118
11.5K_0402_1%
1
TPC8A03-H_SO8
3
2
1
2
PJ503 +1.5V
PR508 +1.5VP 2 1
10K_0402_1% 2 1
@ JUMP_43X118
2 2
PU502 PL503
4
PJ505 1UH_PH041H-1R0MS_3.8A_20%
2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+5VALW
PG
2 1 PVIN LX +1.8VSP
68P_0402_50V8J
@ JUMP_43X118 9 3
PVIN LX
1
680P_0603_50V7K 4.7_1206_5%
22U_0603_6.3V6K
1
1
PC511
8 SVIN
PC510
PR509
PR510
6 20K_0402_1%
2
2
FB
22U_0603_6.3V6K
22U_0603_6.3V6K
5
1 2
2
EN
1
PJ504
NC
NC
TP
3 3
FB=0.6Volt
PC513
PC514
+1.8VSP 2 1 +1.8VGS
2 1
PC512
PR511
11
2
1 2 EN_1.8VSP @ JUMP_43X118
2
<14,19,46> PXS_PWREN
0.1U_0402_10V7K
0_0402_5%
2
PC515 @
SY8033BDBC_DFN10_3X3
1
PR512 1.8VSP max current=4A
1M_0402_5%
1.8VSP_FB
2
1
1
PR513
10K_0402_1% 2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.5VP/+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 43 of 51
A B C D
5 4 3 2 1
D D
@ PJ601
+1.1VALWP_B+ 2 2 1
1 B+
2200P_0402_50V7K
JUMP_43X118
4.7U_0805_25V6-K
4.7U_0805_25V6-K
5
6
7
8
0.1U_0402_25V6
1
1
PC603
PQ601
TPC8065-H_SO8
PC602
PC604
PC605
2
2
PC606
0.1U_0603_25V7K 4
PR602
1 2 1 2
0_0603_5%
PU601
1 10 BST_+1.1VALWP
3
2
1
PGOOD VBST
PR601
1 2 TRIP_+1.1VALWP 2 9 UG_+1.1VALWP PL601
TRIP DRVH 1UH_PCMC063T-1R0MN_11A_20%
34K_0402_1%
PR603 EN_+1.1VALWP 3 8 SW_+1.1VALWP 1 2
0_0402_5% EN SW +1.1VALWP
1 2 FB_+1.1VALWP 4 7 +1.1VALWP_5V
<40,42> SPOK VFB V5IN +5VALW
RF_+1.1VALWP LG_+1.1VALWP
0.1U_0402_16V7K
5 RF DRVL 6
1
5
6
7
8
1
47K_0402_1%
PR604
PC601
4.7_1206_5%
C 1 C
PR605
1U_0603_10V6K
TPC8A03-H_SO8
11
220U_D2_4VY_R15M
TP
1
+
PC608
PC609
PC607
2
@ TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M
2
@
2
2
PR606 2 +1.1VALWP @ PJ602 +1.1VALW
4
470K_0402_1% 2 2 1
1
1
PQ602
680P_0603_50V7K
2
PC610
JUMP_43X118
3
2
1
2
@
PR607
5.76K_0402_1%
2 1
2
PR608
10K_0402_1%
@ PJ603
1
+1.2VSP_B+ 2 2 1
1 B+
2200P_0402_50V7K
JUMP_43X118
4.7U_0805_25V6-K
4.7U_0805_25V6-K
5
6
7
8
0.1U_0402_25V6
1
1
PC612
PQ603
TPC8065-H_SO8
PC611
PC613
PC614
2
2
B B
PC615
0.1U_0603_25V7K 4
PR609
1 2 1 2
0_0603_5%
PU602
@ PR617 1 10 BST_+1.2VSP
3
2
1
0_0402_5% PGOOD VBST
PR610
1 2 1 2 TRIP_+1.2VSP 2 9 UG_+1.2VSP PL602
<33> VLDT_EN TRIP DRVH
75K_0402_1% 1UH_PCMC063T-1R0MN_11A_20%
PR611 EN_+1.2VSP 3 8 SW_+1.2VSP 1 2
91K_0402_1% EN SW +1.2VSP
1 2 FB_+1.2VSP 4 7 +1.2VSP_5V
<33,38,46> SUSP# VFB V5IN +5VALW
RF_+1.2VSP LG_+1.2VSP
0.1U_0402_16V7K
5 RF DRVL 6
1
5
6
7
8
1
47K_0402_1%
PC616
4.7_1206_5%
1
1
PR612
PR614
1U_0603_10V6K
TPC8A03-H_SO8
11
220U_D2_4VY_R15M
TP
1
+
PQ604
PC618
PC619
PC617
2
TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M
2
@ @
2
2
PR613 2 +1.2VSP @ PJ604 +1.2VS
4
470K_0402_1% 2 2 1
1
1
PC620
680P_0603_50V7K
2
JUMP_43X118
3
2
1
2
@
PR615
7.15K_0402_1%
2 1
A A
2
PR616
10K_0402_1%
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +1.1VALWP/+1.2VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 44 of 51
5 4 3 2 1
5 4 3 2 1
D D
+1.5V
1
PJ701
1
JUMP_43X118
@
22
PU701
1 VIN NC 8 +3VALW PJ702
+0.75VSP 2 2 1 1 +0.75VS
PC702 2 7
GND NC
1
4.7U_0805_6.3V6K @ JUMP_43X118
1
3 6 PC703
PR702 VREF VCNTL
2
1K_0402_1% 4 5 1U_0603_10V6K
VOUT NC
9
2
PQ701 TP
2N7002W-T/R7_SOT323-3 APL5336KAI-TRL_SOP8P8
.1U_0402_16V7K
PR701
D
+0.75VSP
10U_0603_6.3V6M
49.9K_0402_1%
1K_0402_1%
PC704
10U_0603_6.3V6M
<38> SUSP 1 2 2
1
G
PC705
PC706
2
0.1U_0402_10V7K
C S PR703 C
2
1
PC701
PU702
APL5508-25DC-TRL_SOT89-3
PJ703
+3VS PJ704
1 1 2 2 2 IN OUT 3 +2.5VSP
+2.5VSP 2 1 +2.5VS
@ JUMP_43X39 2 1
1
B GND @ JUMP_43X39 B
4.7U_0805_6.3V6K
1
1
(0.38A,20mils ,Via NO.=1)
PC708
PR704 @
PC707 1 10K_1206_5%
1U_0603_10V6K
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +0.75VSP/2.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 45 of 51
5 4 3 2 1
A B C D
<21> VCCSENSE_VGA @ PJ801
VGA_CORE_B+ 2 2 1
1 B+
JUMP_43X118
1 1
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
0.1U_0402_25V6
1
1
PC803
PR802
PC802
PC804
PC805
0_0402_5%
2
5
PC806
TPCA8065-H_SOP-ADV8-5
2
10P_0402_25V8J
2 1
PQ801
2
2
4700P_0402_25V7K
PC801
10P_0402_25V8J PR803 4
41.2K_0402_1%
2
PR801
PC807
0_0402_5%
1
<21> VSSSENSE_VGA 1 2
19 1
3
2
1
PL801
21
20
18
17
16
PU801 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
VSNS
TRIP
MODE
PAD
SLEW
GND
+VGA_COREP
PR804
2 1
1 GSNS V5IN 15 +5VALW
2
11K_0402_1%
102K_0402_1%
1
PR805
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
TPCA8057-H 1N PPAK56-8
TPCA8057-H 1N PPAK56-8
1 1 1
PC808
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2 V3 DRVL 14 1 1 1
+ + +
PC809
PC810
PC811
PC812
PC813
PC814
1U_0603_10V6K PR806
PQ802
PQ803
4.7_1206_5%
21
5.62K_0402_1%
2
2 2 @ 2 2 2 2
PR807
3 13 UGATE2_VGA 4 4
V2 TPS51518RUKR_QFN20_3X3 DRVH
1
PC815
4 12 680P_0603_50V7K
21
V1 SW
5.62K_0402_1%
PR808 PC816
3
2
1
3
2
1
2
PR809
2.2_0603_5% 0.1U_0603_25V7K
5 BOOT2_VGA
11 2 1 BOOT2_2_VGA
1 2
V0 BST @
PGOOD
2 2
1 1
VREF
VID0
VID1
100K_0402_1%
EN
PR810
LGATE2_VGA
6
10
+VGA_COREP
2
Iocp=32.5A
0.1U_0402_10V7K
1
+3VS
PC817
2
PJ802
1
10K_0402_1%
+VGA_COREP 2 2 1 1 +VGA_CORE
<18>
<18>
PR811
Seymour
GPU_VID0
GPU_VID1
PR812 @ JUMP_43X118
0_0402_5%
<14,17,19> VGA_PWRGD 1 2 GPU_VID1 GPU_VID0 Core Voltage Level
2
PJ803
2 2 1 1
PR813 1 1 0.9V
0_0402_5% @ JUMP_43X118
1 2VRON_VGA
<19> PX_MODE @ PR814 1 0 1.0V
0_0402_5%
1 2
2
<33,38,44> SUSP# 0 1 1.05V
PC818 @
0.1U_0402_16V7K
1
0 0 1.1V
+1.5V
3 3
+5VALW PJ805
1
+VGA_PCIEP 2 2 1 1 +1.0VGS
PJ804 @
1
JUMP_43X79 JUMP_43X79
@ PR820 +5VALW
1
2
10K_0402_5% PC819
+3VS 1 2 GPU_VID0 1U_0402_6.3V6K
2
2
@ PR821
1
10K_0402_5%
1
+3VS 1 2 GPU_VID1 PR815 PC820
@ PD801 0_0402_5% 4.7U_0805_6.3V6K
6
@ PR822 PU802
2
10K_0402_5% RB751V-40_SOD323-2 5
VCNTL
2
GPU_VID0 VIN
1 2 1 2 7 POK
VOUT 4 +VGA_PCIEP
@ PR823
10K_0402_5% PR816
22U_0603_6.3V6K
VOUT 3
1
1 2 GPU_VID1 40.2K_0402_1%
PC823
PXS_PWREN 1 2 8 2
<14,19,43> PXS_PWREN EN FB
1
PR817
0.1U_0603_25V7K
GND
2
1
PC822
9 1.15K_0402_1%
PR818 VIN
2
20K_0402_1% APL5912-KAC-TRL_SO8 VGA_PCIE 1.0V 1.1 V
2
1
2
PC821
1
0.01U_0402_25V7K
PR819 4.53K 3K
PR819
4.53K_0402_1%
2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VGA_CORE/VGA_PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 46 of 51
A B C D
5 4 3 2 1
PC901 PR901
330P_0402_50V7K 2K_0402_1%
2 1 2 1
<7> APU_VDDNB_SEN_H PC902
PR902 PR903 @ PR904
2.74K_0402_1% 137K_0402_1%390P_0402_50V7K 32.4K_0402_1%
2 1 2 1 2 1 2 1
CPU_B+ PL901
PR905 PR906 PC903 PR907 PC904 FBMA-L11-453215-800LMA90T 1812
10_0402_5% 0_0402_5% 1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J 2 1 B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.01U_0402_25V7K
+APU_CORE_NB 2 1 2 1 2 1 2 1 2 1
1
220U_25V_M
@ PC905
1
+
PC908
PC909
PC910
PC906
VSUMP_NB 1000P_0402_50V7K PQ901
1
D D
2.61K_0402_1%
PC907
10K_0402_5%_ERTJ0ER103J
1
2 1
2
2
PR908
2
0.047U_0402_16V7-K
0.1U_0402_25V6
UGATE_NB1 4
2
11K_0402_1%
2
PR909
12
PH901
PC911
PC912
TPCA8065-H_PPAK56-8-5 PL902
1
3
2
1
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<BOM Structure>
1
PR910
590_0402_1% PHASE_NB1 1 4
+APU_CORE_NB
2
4.7_1206_5%
VSUMN_NB 2 1 FCCM_NB
1
PC915 2 3
1
1
@ PC914
0_0402_5%
PR911
@ PR912
@PR912 PR913 0.22U_0603_25V7K
PR914
PC913 100_0402_1% 220P_0402_50V7K BOOT_NB1 1 2 2 1 PR915
0.1U_0603_25V7K 2 1 2 1 LGATE_NB1 2.2_0603_5% 3.65K_0402_1%
2
PR916 VSUMP_NB 2 1
2
2 1 PHASE_NB1
1 2
680P_0603_50V7K
10K_0402_1% LGATE_NB1 4 4 PR917
PC916
UGATE_NB1 1_0402_1%
After rev1.1 must change to 133k PQ902 PQ907 VSUMN_NB 2 1
TPCA8057-H_PPAK56-8-5 TPCA8057-H_PPAK56-8-5
2
48
47
46
45
44
43
42
41
40
39
38
37
3
2
1
3
2
1
2
PU901
2
PR918 +APU_CORE_NB
ISUMP_NB
ISUMN_NB
FCCM_NB
LGATEX
PHASEX
UGATEX
ISEN1_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
PWM2_NB
107K_0402_1% PC917 PR921
1000P_0402_25V6K 10_0402_5% CPU_B+ Iocp=39A
1
+5VS 2 1 1 36 BOOT_NB1
1
PR919 27.4K_0402_1% ISEN2_NB BOOTX PR922
2 1 2 NTC_NB VIN 35 2 1
PH902 3 34 BOOT2 0_0603_5%
IMON_NB BOOT2
1
470K_0402_5%_TSM0B474J4702RE PR920 0_0402_5%
2 1
<7,33,40> H_PROCHOT# <7> APU_SVC 2 1 SVC 4 SVC UGATE2 33 UGATE2 PC918
PR923 0_0402_5% 0.22U_0603_25V7K CPU_B+
2
10K_0402_1%
2 1 5 32 PHASE2
VR_HOT_L PHASE2
1
PR925 0_0402_5%
2
2200P_0402_50V7K
+5VS
10U_0805_25V6K
10U_0805_25V6K
PR924
0.01U_0402_25V7K
C
<7> APU_SVD 2 1 SVD 6 SVD LGATE2 31 LGATE2 C
PR927 0_0402_5% ISL6277HRTZ-T_TQFN48_6X6
@PR926
@ PR926 +1.5VS 2 1 VDDIO 7 VDDIO VDDP 30
100K_0402_5% PR928 0_0402_5% PR929
2
1
PC919
PC920
PC921
PC922
2 1 SVT 8 29 2 1
<7> APU_SVT
1
SVT VDD
5
1U_0603_16V6K
PR965 +3VS PR930 0_0402_5% 1_0603_5%
APU_IMON
0_0402_5% 2 1 ENABLE 9 28 PQ903
<33> VR_ON
2
ENABLE PWM_Y
1
1U_0603_16V6K
2 1 PR931 0_0402_5%
PC924
PR932
<7,12> APU_PWRGD 2 1 PWROK 10 PWROK LGATE1 27 LGATE1
PC923
107K_0402_1%
2
1 2 11 26 PHASE1 UGATE1 4
IMON PHASE1
After rev1.1 must change to 133k
PC925 @ PR933 0_0402_5% 12 25 UGATE1
1000P_0402_25V6K NTC UGATE1 PL903
PGOOD
2 1
BOOT1
ISUMN
<14,33> FCH_PWRGD
ISUMP
COMP
ISEN3
ISEN2
ISEN1
+3VS
VSEN
1 2
RTN
TPCA8065-H_PPAK56-8-5 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
3
2
1
FB2
+5VS
FB
TP
PHASE1 1 4
PR934 27.4K_0402_1% PR936 +APU_CORE
13
14
15
16
17
18
19
20
21
22
23
24
49
1
2 1 0_0402_5% PC926 ISEN1 2 PR935 1 2 3 1 2 ISEN2
5
2 1 ISEN3 PR938 0.22U_0603_25V7K 10K_0402_1%
1
PH903 PR939 BOOT1 1 2 2 1 PR941 PR937
470K_0402_5%_TSM0B474J4702RE 2 1 ISEN2 BOOT1 100K_0402_5% 2.2_0603_5% 4.7_1206_5% PR942 10K_0402_1%
2 1 @ PR940 3.65K_0402_1%
2
10_0402_5% ISEN1 VSUM+ 2 1
1
0.22U_0402_10V6K
0.22U_0402_10V6K
LGATE1 4
1 2
1
PR944 @ VGATE <33> PC929
1
PR943 10K_0402_1% PQ904 680P_0603_50V7K PR945
10K_0402_1% PC930 TPCA8057-H_PPAK56-8-5 1_0402_1%
10P_0402_25V8K VSUM- 2 1
2
3
2
1
2
PC927
PC928
2 1
2
VSUM-
CPU_B+
VSUM+
2200P_0402_50V7K
2.61K_0402_1%
10U_0805_25V6K
10U_0805_25V6K
0.01U_0402_25V7K
10K_0402_5%_ERTJ0ER103J
PC931 PR947 PC932 @ PR948 +APU_CORE
1
1000P_0402_50V7K301_0402_1% 100P_0402_50V8J 32.4K_0402_1%
Iocp=49A
5
330P_0402_50V7K
PR946
0.022U_0402_16V7K
0.22U_0402_10V6K
2 1 2 1 2 1 2 1
PQ905
2
1
B B
PC936
PC937
PC938
PC940
2
2
11K_0402_1%
PR950 PR951 PC939
12
PH904
PR949
PC933
PC934
PC935
1.8K_0402_1% 137K_0402_1% 390P_0402_50V7K
2
2 1 2 1 2 1 UGATE2 4
1
1
1
PR953
560_0402_1% PR952 PC941
2
VSUM- 2 1 2K_0402_1% 680P_0402_50V7K TPCA8065-H_PPAK56-8-5 PL904
3
2
1
2 1 2 1 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
@ PC943
1
@ PR955 820P_0402_50V7K PHASE2 1 4
PC942 100_0402_1% PR954 +APU_CORE
0.1U_0603_25V7K 2 1 2 1 10_0402_5% PC944 ISEN2 2 PR956 1 2 3 1 2 ISEN1
2
1
2 1 +APU_CORE PR958 0.22U_0603_25V7K 10K_0402_1%
BOOT2 1 2 2 1 PR959 PR957
PR960 2.2_0603_5% 4.7_1206_5% PR961 10K_0402_1%
2 1 APU_VDD_SEN_H <7> 3.65K_0402_1%
0_0402_5% VSUM+ 2 1
1 2
LGATE2 4
PC945
PR963 PQ906 680P_0603_50V7K PR962
0.01U_0402_25V7K
2 1 TPCA8057-H_PPAK56-8-5 1_0402_1%
2
0_0402_5% APU_VDD_SEN_L <7> VSUM- 2 1
3
2
1
2
2 1
PC946
PR964
10_0402_5%
1
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE/CPU_CORE_NB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 47 of 51
5 4 3 2 1
5 4 3 2 1
+CPU_CORE_NB
D
+APU_CORE +CPU_CORE D
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
1
1
+APU_CORE_NB
PC1001
PC1002
PC1003
PC1004
PC1005
2
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
10U_0603_6.3V6K
22U_0603_6.3V6K
1
1
@ @ @
PC1006
PC1007
PC1008
PC1009
PC1010
PC1011
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
1
2
PC1012
PC1013
PC1014
PC1015
PC1016
2
2
22U_0603_6.3V6K
22U_0603_6.3V6K
22U_0603_6.3V6K
1
330U_D2_2VM_R7M
330U_D2_2VM_R7M
330U_D2_2VM_R7M
1 1 1
PC1017
PC1018
PC1019
+ + +
PC1020
PC1021
PC1034
2
2
@ @ @
2 2 @ 2
C C
+APU_CORE
330U_D2_2VM_R7M
330U_D2_2VM_R7M
330U_D2_2VM_R7M
330U_D2_2VM_R7M
1 1 1 1
+ + + +
PC1022
PC1023
PC1024
PC1025
+1.2VS
2 2 2 2 @
330U_D2_2VM_R7M
22U_0603_6.3V6K
10U_0603_6.3V6K
10U_0603_6.3V6K
10U_0603_6.3V6K
10U_0603_6.3V6K
10U_0603_6.3V6K
10U_0603_6.3V6K
1
1
+
PC1026
PC1027
PC1028
PC1029
PC1030
PC1031
PC1032
PC1033
2
2
2
B B
+1.2VS
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - PROCESSOR DECOUPLING
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 48 of 51
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1
for PWR
Item Reason for change PG# Modify List Date Phase
1
D D
C C
9
10
11
12
13
14
B B
15
16
17
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 49 of 51
5 4 3 2 1
5 4 3 2 1
+3VALW 1ms< T1 < 100ms : +3VALW rising time, for LAN chip request
+5VALW
T1
SPOK
+1.1VALW +3VALW need rampe up before +1.1VALW or at the same time.
EC_ON
D D
ON/OFFBTN# T2 < 50ms : EC_RSMRST# rising time
+3VALW need rampe up before EC_RSMRST# de-assertion at least 10ms
EC->FCH EC_RSMRST#
T2 +1.1VALW need rampe up before EC_RSMRST# de-assertion
T3
FCH -> EC RTC_CLK T3 > 16ms : EC_RSMRST# de-assert to start RTCCLK
EC->FCH PBTN_OUT#
T13
T13 > 200ns : PBTN_OUT# to SLP_S3#/S5# de-assertion
SLP_S5#
FCH -> EC SLP_S3#
EC -> PWR SYSON
1.5V
EC -> PWR SUSP#
+0.75VS
C +1.1VS C
+1.5VS
+2.5VS
+3VS
+5VS
EC -> PWR VR_ON
+APU_CORE
+APU_CORE_NB
PWR -> EC VGATE
B EC->FCH FCH_POK B
(FCH_PWRGD)
T11 T11< 32ms : FCH_POK assertion to clock out
FCH -> APU APU_CLK
DISP_CLK
T7
98ms< T7< 150ms : FCH_POK assertion to APU_PWRGD
FCH -> APU APU_PWRGD
KB_RST# should be de-asserted before FCH_POK
FCH -> EC KB_RST#
T9
101ms< T9< 113ms : FCH_POK assertion to A_RST# de-assertion
FCH -> Device PLT_RST#
A_RST#
FCH -> APU APU_RST#
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A3 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Friday, November 04, 2011 Sheet 50 of 51
5 4 3 2 1
PXS_PWREN +1.8VSP +1.8VGS
SY8033
D
+5VALWP +5VALW +5VS D
ADAPTER
+3VALWP +2.5VSP
+3VALW +3VS APL5508
+2.5VS
RT8205E
B+ +3VGS
Charger PXS_PWREN
+1.5VS
BATTERY +1.5VGS
C PX_MODE C
+1.5VP +1.5V +0.75VSP +0.75VS
TPS51212 SUSP
APL5336
SYSON
+VGA_PCIEP +1.0VGS
APL5912
+1.2VSP +1.2VS PXS_PWREN
TPS51212
SUSP#
+1.1VALWP +1.1VALW +1.1VS
TPS51212
SPOK
B B
+APU_CORE_NB
+APU_CORE
VR_ON ISL6277
+VGA_COREP +VGA_CORE
PX_MODE
TPS51518
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/10/12 Deciphered Date 2013/10/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA8611P
Date: Wednesday, November 09, 2011 Sheet 51 of 51
5 4 3 2 1
www.s-manuals.com
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