En AX8575 Service Manual 091008 (Up - By.nasirahmed)
En AX8575 Service Manual 091008 (Up - By.nasirahmed)
1. Wave Type
● CELLULAR : G7W
● PCS: G7W
2. Frequency Scope
Transmit Frequency (MHz) Receive Frequency (MHz)
CELLULAR PCS CELLULAR PCS GPS
824.82 ~ 848.19 1850~1910 869.82~893.19 1930~1990 1575.42
Classification Function
MSM6575-NSP Terminal operation control and digital signal processing
Memory MCP OneNAND Flash Memory (2G) + SDRAM (1G)
(TYAB0A111081KC) Storing of terminal operation program
7. Frequency Stability
● CELLULAR : ±0.5PPM
● PCS : ±0.1PPM
AX8575
SERVICE
SERVICEMANUAL
MANUAL
General
General Introduction
Introduction
The AX8575 phone has been designed to operate on the latest digital mobile communication technology, Code
Division Multiple Access (CDMA). This CDMA digital technology has greatly enhanced voice clarity and can
provide a variety of advanced features. Currently, CDMA mobile communication technology has been
commercially used in Cellular and Personal Communication Service (PCS). The difference between them is the
operating frequency spectrum. Cellular uses 800MHz and PCS uses 1.9GHz. The AX8575 support GPS Mode, we
usually call it tri-band phone. Also, AX8575 works on Advanced Mobile Phone Service (S-GPS). We call it dual-
mode phone. If one of the Cellular, PCS base stations is located nearby, Call fail rate of triple-mode phone is less
than dual-mode phone or single-mode phone.
The CDMA technology adopts DSSS (Direct Sequence Spread Spectrum). This feature of DSSS enables the phone
to keep communication from being crossed and to use one frequency channel by multiple users in the same specific
area, resulting that it increases the capacity 10 times more compared with that in the analog mode currently used.
Soft/Softer Handoff, Hard Handoff, and Dynamic RF power Control technologies are combined into this phone to
reduce the call being interrupted in a middle of talking over the phone.
Cellular and PCS CDMA network consists of MSO (Mobile Switching Office), BSC (Base Station Controller), BTS
(Base station Transmission System), and MS (Mobile Station). The following table lists some major CDMA
Standards.
Chapter1.
Chapter1. System
System Introduction
Introduction
1. CDMA Abstract
The CDMA mobile communication system has a channel hand-off function that is used for collecting the information
on the locations and movements of mobile telephones from the cell site by automatically controlling several cell site
through the setup of data transmission routes, and then enabling one switching system to carry out the automatic
remote adjustment. This is to maintain continuously the call state through the automatic location confirmation and
automatic radio channel conversion when the busy subscriber moves from the service area of one cell site to that of
another by using automatic location confirmation and automatic radio channel conversion functions. The call state
can be maintained continuously by the information exchange between switching systems when the busy subscriber
moves from one Cellular system area to the other Cellular system area.
In the Cellular system, the cell site is a small-sized low output type and utilizes a frequency allocation system that
considers mutual interference, in an effort to enable the re-use of corresponding frequency from a cell site separated
more than a certain distance.
Unlike the time division multiple access (TDMA) or frequency division multiple access (FDMA) used in the band
limited environment, the Code Division Multiple Access (CDMA) system which is one of digital Cellular systems is
a multi-access technology under the interference limited environment. It can process more number of subscribers
compared to other systems (TDMA system has the processing capacity three times greater than the existing FDMA
system whereas CDMA system, about 12~15 times of that of the existing system).
CDMA system can be explained as follows; TDMA or CDMA can be used to enable each person to talk alternately
or provide a separate room for each person when two persons desire to talk with each other at the same time, whereas
FDMA can be used to enable one person to talk in soprano, whereas the other in bass (one of the two talkers can
carry out synchronization for hearing in case there is a bandpass filter function in the area of the hearer). Another
available method is to make two persons to sing in different languages at the same time, space, and frequency when
wishing to let the audience hear the singing without being confused. This is the characteristic of CDMA.
On the other hand, when employing the CDMA technology, each signal has a different pseudo-random binary
sequence used to spread the spectrum of carrier. A great number of CDMA signals share the same frequency
spectrum. In the perspective of frequency area or time area, several CDMA signals are overlapped. Among these
types of signals, only desired signal energy is selected and received through the use of pre-determined binary
sequence; desired signals can be separated, and then received with the correlators used for recovering the spectrum
into its original state. At this time, the spectrums of other signals that have different codes are not recovered into its
original state, and appears as the self-interference of the system.
When employing the narrow band modulation (30kHz band) that is the same as the analog FM modulation system
used in the existing Cellular system, the multi-paths of radio waves create a serious fading. However, in the CDMA
broadband modulation (1.25MHz band), three types of diversities (time, frequency, and space) are used to reduce
serious fading problems generated from radio channels in order to obtain high-quality calls.
Time diversity can be obtained through the use of code interleaving and error correction code whereas frequency
diversity can be obtained by spreading signal energy to wider frequency band. The fading related to normal
frequency can affect the normal 200~300KHz among signal bands and accordingly, serious effect can be avoided.
Moreover, space diversity (also called path diversity) can be realized with the following three types of methods.
First, it can be obtained by the duplication of cell site receive antenna. Second, it can be obtained through the use of
multi-signal processing device that receives a transmit signal having each different transmission delay time and then,
combines them. Third, it can be obtained through the multiple cell site connection (Soft Handoff) that connects the
mobile station with more than two cell sites at the same time.
The CDMA system utilizes the forward (from a base station to mobile stations) and backward (from the mobile
station to the base station) power control in order to increase the call processing capacity and obtain high-quality calls.
In case the originating signals of mobile stations are received by the cell site in the minimum call quality level (signal
to interference) through the use of transmit power control on all the mobile stations, the system capacity can be
maximized. If the signal power of mobile station is received too strong, the performance of that mobile station is
improved. However, because of this, the interference on other mobile stations using the same channel is increased
and accordingly, the call quality of other subscribers is reduced unless the maximum accommodation capacity is
reduced.
In the CDMA system, forward power control, backward open loop power control, and closed loop power control
methods are used. The forward power control is carried out in the cell site to reduce the transmit power on mobile
stations less affected by the multi-path fading and shadow phenomenon and the interference of other cell sites when
the mobile station is not engaged in the call or is relatively nearer to the corresponding cell site. This is also used to
provide additional power to mobile stations having high call error rates, located in bad reception areas or far away
from the cell site.
The backward open loop power control is carried out in a corresponding mobile station; the mobile station measures
power received from the cell site and then, reversely increases/decreases transmit power in order to compensate
channel changes caused by the forward link path loss and terrain characteristics in relation to the mobile station in the
cell site. By doing so, all the mobile transmit signals received by the base station have same strength.
Moreover, the backward closed loop power control used by the mobile station is performed to control power using
the commands issued out by the cell site. The cell site receives the signal of each corresponding mobile station and
compares this with the pre-set threshold value and then, issues out power increase/decrease commands to the
corresponding mobile station every 1.25msec (800 times per second). By doing so, the gain tolerance and the
different radio propagation loss on the forward/backward link are complemented.
The bi-directional voice service having variable data speed provides voice communication which employs voice
encoder algorithm having power variable data rate between the base station and the mobile station. On the other hand,
the transmit voice encoder performs voice sampling and then, creates encoded voice packets to be sent out to the
receive voice encoder, whereas the receive voice encoder demodulates the received voice packets into voice samples.
One of the two voice encoders described in the above is selected for use depending on inputted automatic conditions
and message/data; both of them utilize four-stage frames of 9600, 4800, 2400, and 1200 bits per second for Cellular
and 14400,7200,3600,1800 bits per second for PCS, so PCS provide relatively better voice quality (almost twice
better than the existing cellular system). In addition, this type of variable voice encoder utilizes adaptive threshold
values on selecting required data rate. It is adjusted in accordance with the size of background noise and the data rate
is increased to high rate only when the voice of caller is inputted.
Therefore, background noise is suppressed and high-quality voice transmission is possible under the environment
experiencing serious noise. In addition, in case the caller does not talk, data transmission rate is reduced so that the
transmission is carried out in low energy. This will reduce the interference on other CDMA signals and as a result,
improve system performance (capacity increased by about two times).
Voice privacy is provided in the CDMA system by means of the private long code mask used for PN spreading.
Voice privacy can be applied on the traffic channels only. All calls are initiated using the public long code mask for
PN spreading. The mobile station user may request voice privacy during call setup using the origination message or
page response message, and during traffic channel operation using the long code transition request order.
The Transition to private long code mask will not be performed if authentication is not performed. To initiate a
transition to the private or public long code mask, either the base station or the mobile station sends a long code
transition request order on the traffic channel.
A handoff in which the mobile station commences communications with a new base station without interrupting
communications with the old base station. Soft handoff can only be used between CDMA channels having identical
frequency assignments.
Unlike the existing analog Cellular system, the CDMA system can reuse the same frequency at the adjacent cell.
there is no need to prepare a separate frequency plan. Total interference generated on mobile station signals received
from the cell site is the sum of interference generated from other mobile stations in the same cell site and interference
generated from the mobile station of adjacent cell site. That is, each mobile station signal generates interference in
relation to the signals of all the other mobile stations.
The subscriber capacity of the CDMA system is flexible depending on the relation between the number of users and
service classes. For example, the system operator can increase the number of channels available for use during the
busy hour despite the drop in call quality. This type of function requires 40% of normal call channels in the standby
mode during the handoff, in an effort to avoid call disconnection resulting from the lack of channels.
In addition, in the CDMA system, services and service charges are classified further into different classes so that
more transmit power can be allocated to high class service users for easier call set-up; they can also be given higher
priority of using hand-off function than the general users.
The hardware structure of CDMA mobile phone is made up of radio frequency (RF) part and logic part. The RF part
is composed of Receiver part (Rx), Transmitter part (Tx) and Local part (LO). For the purpose of operating on tri-
band, It is necessary dual Tx path, tri Rx path, dual PLL and switching system for band selection. The mobile phone
antenna is connected with the frequency separator which divide antenna input/output signals between Cellular
frequency band (824~894 MHz) and PCS frequency band (1850~1990MHz). Each separated path is linked with the
Cellular duplexer and PCS duplexer. Duplexer carries out separating Rx band and Tx band. The Rx signals from the
antenna are converted into intermediate frequency (IF) band by the frequency synthesizer and frequency down
converter. And then, pass SAW filter which is a band pass filter for removing out image frequency. The IF output
signals that have been filtered is converted into digital signals via Analog-to-Digital Converter (ADC). In front of the
ADC, switching system is required to choose which band path should be open. The digital signals send to 5
correlators in each CDMA de-modulator. Of these, one is called a searcher whereas the remaining 4 are called data
receivers (fingers). Digitalized IF signals include a great number of call signals that have been sent out by the
adjacent cells. These signals are detected with pseudo-noise sequence (PN Sequence). Signal to interference ratio
(C/I) on signals that match the desired PN sequence are increased through this type of correlation detection process,
but other signals obtain processing gain by not increasing the ratio. The carrier wave of pilot channel from the cell
site most adjacently located is demodulated in order to obtain the sequence of encoded data symbols. During the
operation with one cell site, the searcher searches out multi-paths in accordance with terrain and building reflections.
On three data receivers, the most powerful 3 paths are allocated for the parallel tracing and receiving. Fading
resistance can be improved a great deal by obtaining the diversity combined output for de-modulation. Moreover, the
searcher can be used to determine the most powerful path from the cell sites even during the soft handoff between the
two cell sites. Moreover, 3 data receivers are allocated in order to carry out the de-modulation of these paths. Output
data that has been demodulated changes the data string in the combined data row as in the case of original
signals(deinterleaving), and then, are demodulated by the forward error correction decoder which uses the Viterbi
algorithm.
Mobile station user information send out from the mobile station to the cell site pass through the digital voice
encoder via a mike. Then, they are encoded and forward errors are corrected through the use of convolution encoder.
Then, the order of code rows is changed in accordance with a certain regulation in order to remove any errors in the
interleaver. Symbols made through the above process are spread after being loaded onto PN carrier waves. At this
time, PN sequence is selected by each address designated in each call.
Signals that have been code spread as above are digital modulated (QPSK) and then, power controlled at the
automatic gain control amplifier (AGC Amp). Then, they are converted into RF band by the frequency synthesizer
synchronizing these signals to proper output frequencies.
Transmit signals obtained pass through the duplexer filter and then, are sent out to the cell site via the antenna.
1)CELLULAR : 45 MHz
2)PCS : 80 MHz
1)CELLULAR : 20 Channels
2) PCS : 48 Channels
1) CDMA : ±0.5PPM
2) PCS : ±0.1PPM
1) CELLULAR : 1.25MHz
2) PCS: 1.25 MHz
4.1.10 Battery Type, Capacity and Operating Time. Unit = Hours : Minutes
Standard (1000mAh)
CELLULAR About 530.7 Hours (SCI=2)
Standby Time
PCS About 546 Hours (SCI=2)
CELLULAR 362 Minutes (-92dBm input)
Talk time
PCS 351 Minutes (-92dBm input)
5. Installation
1) The Battery pack is keyed so it can only fit one way. Align the groove in the battery pack with the rail on the back
of the phone until the battery pack rests flush with the back of the phone.
2) Slide the battery pack forward until you hear a “click”, which locks the battery in place.
1) Plug the adapter into a wall outlet. The adapter can be operated from a 110V source. When AC power is connected
to the adapter.
2) Insert the adapter IO plug into the phone with the installed battery pack.
Red light indicates battery is being charged.. Green light indicates battery is fully charged.
CHAPTER
CHAPTER 2. 2. NAM
NAM Input
Input Method
Method
(Inputting
(Inputting of
of telephone
telephone numbers
numbers included)
included)
1. NAM Programming Method
1) Press “##77647268575”+CALL” and then, press “000000”
9) Security Code
You can decide to edit Security Code.
Press “OK” to edit more advanced NAM1 items.
Press “BACK” to edit previous NAM1 items.
Press “EDIT’ to edit security code.
CHAPTER
CHAPTER 3.
3. Circuit
Circuit Description
Description
1. RF Transmit/Receive Part
1.1 Overview
The TX and RX part employs the Direct-Conversion system. The TX and RX frequencies are respectively
824.04~848.97 and 869.04~893.97 for cellular and 1850~1910 and 1930~1990 for PCS. The block diagram is shown
in [Figure 1-1]. CDMA RF signals received through the antenna are separated by the Quadplexer.
RF Signal fed into the low noise amplifier in RTR6500(LNA) through the quadplexer. Then, they are fed into Mixer
in RTR6500. In RTR6500, the RF signal is changed into baseband signal directly. Then, this signal is changed into
digital signal by the analog to digital converter (ADC, A/D Converter), and the digital circuit part of the
MSM(Mobile Station Modem) 6575 processes the data from ADC. The digital processing part is a demodulator.
In the case of transmission, RTR6500 receives OQPSK-modulated analog signal from the MSM6575.
The RTR6500 connects directly with MSM6575 using an analog baseband interface. In RTR6500, the baseband
quadrature signals are upconverted to the Cellular or PCS frequency bands and amplified to provide signal drive
capability to the power amp.
After that, the RF signal is amplified by the Power Amp in order to have enough power for radiation. Finally, the RF
signal is sent out to the cell site via the antenna after going through the quadplexer.
LPF
Up-convert
[U109] [F102]
Interface with
Mobile Connectivity
Loop TX LO Other functions
[U111]
S/W
Filter Circuit
coupler
Air Interfaces Camera
Detector TX _ Gain
Control RTR
VCTCXO [U103]
Quad- Loop Filter
6500 [U201]
Buffer Audio
plexer Pre- LNA
[U105] PRX LO
SBI Housekeeping MSM
Circuit
ADC
ADC
6575
LPF
Quad
D’convert ADC
LPF
[F101] General
GPIOs w/TLMN
LG Electronics Inc.
N.C
LPF ADC Housekeeping
Quad
D’convert
N.C LPF ADC Input Power
SRX LO PM Interfaces
[U112] Management
Circuit
[F103]
LPF LPF ADC
GPS Quad Output Voltage
GPS LO
BPF D’convert LPF LPF ADC Regulation
Circuit
AX8575
GPS LNA
Module Loop Filter
AX8575
1.2 Description of RX Part Circuit
The ACFM-7107 is a quadplexer that combines a US PCS & cellular band duplexer into a single, miniature package
with a single antenna port.
The main function of quadplexer is to prohibit the other band signals from flowing into the
one band circuit and vice versa. The specification of AX8575 quadplexer is described below:
The RTR6500 has cellular, and PCS LNA, respectively. The characteristics of Low Noise Amplifier (LNA) are low
noise Fig., high gain, high intercept point and high reverse isolation. The frequency selectivity characteristic of
mobile phone is mostly determined by LNA.
The specification of AX8575 LNA is described below:
The characteristics of Low Noise Amplifier (LNA) are low noise Fig., high gain, high intercept point and high
reverse isolation. The frequency selectivity characteristic of mobile phone is mostly determined by LNA.
The specification of AX8575 GPS LNA is described below
The main function of RX RF SAW filter is to attenuate mobile phone spurious frequency, attenuate noise amplified
by the LNA and suppress second harmonic originating in the LNA.
The RTR6500 device performs signal down-conversion for Cellular, PCS and GPS tri-band applications. It contains
all the circuitry (with the exception of external filters) needed to support conversion of received RF signals to Base-
band signals. The three down-converting Mixers (Cellular, PCS and GPS), and a programmable PLL for generating
RX LO frequency and an RX LO Buffer Amplifier and RX Voltage Controlled Oscillator. The GPS LNA & mixers
offer the most advanced and integrated CDMA RX solution designed to meet cascaded Noise Fig. (NF) and Third-
order Intercept Point (IIP3) requirements of IS-98D and J-STD-018 specifications for Sensitivity, Two-Tone Inter-
modulation, and Single-tone Desensitization.
Operation modes and band selection are specially controlled from the Mobile Station Modem
MSM6575.
The specification of AX8575 Mixers is described below:
The RTR6500 Base-band to RF Transmit Processor performs all TX signal-processing functions required between
digital Base-band and the Power Amplifier Modulator (PAM). The Base-band quadrate signals are up-converted to
the Cellular or PCS frequency bands and amplified to provide signal drive capability to the PAM. The RTR6500
includes mixers for up-converting analog Base-band to RF, a programmable PLL for generating TX LO frequency a
TX LO Buffer Amplifier and TX Voltage Controlled Oscillator, cellular and PCS driver amplifiers and TX power
control through an 85 dB VGA. As added benefit, the single sideband up-conversion eliminates the need for a band
pass filter normally required between the up-converter and driver amplifier.
I, I/, Q and Q/ signals proceed from the MSM6575 to RTR6500 are analog signal. In CDMA mode, These signals
are modulated by Offset Quadrature Phase Shift King (OQPSK). I and Q are 90 deg. out of phase, and I and I/ are
180 deg. The mixers in RTR6500 converts baseband signals into RF signals. After passing through the upconverters,
RF signal is inputted into the Power AMP.
The Dual power amplifier that can be used in the PCS and CDMA mode has linear amplification capability and high
efficiency. For higher efficiency, it is made up of one MMIC (Monolithic Microwave Integrated Circuit) for which
RF input terminal and internal interface circuit are integrated onto one IC after going through the AlGaAs/GaAs HBT
(heterojunction bipolar transistor) process. The module of power amplifier is made up of an output end interface
circuit including this MMIC. The maximum power that can be inputted through the input terminal is +10dBm and
conversion gain is about 26.5dB. RF transmit signals that have been amplified through the power amplifier are sent to
the duplexer.
.
1.4 Description of Frequency Synthesizer Circuit
The temperature variation of mobile phone can be compensated by VCTCXO. The reference frequency of a mobile
phone is 19.2 MHz. The receiver frequency tuning signals called TRK_LO_ADJ from MSM as 0.5 V~2.5 V DC via
R and C filter in order to generate the reference frequency of 19.2 MHz and input it into the frequency synthesizer.
Frequency stability depending on temperature is ±2.0 ppm.
2.1 Overview
The digital/voice processing part processes the user's commands and processes all the digital and voice signal
processing in order to operate in the phone. The digital/voice processing part is made up of a main keypad/touch
keypad/LCD, receptacle part, voice processing part, mobile station modem part, memory part, and power supply part.
2.2 Configuration
This is used to transmit keypad signals to MSM6575. It is made up of a keypad backlight part that illuminates the
keypad, LCD part that displays the operation status onto the screen, and a receptacle that receives and sends out voice
and data with external sources.
The voice processing part is made up of an audio codec used to convert MIC signals into digital voice signals and
digital voice signals into analog voice signals, amplifying part for amplifying the voice signals and sending them to
the ear piece, amplifying part that amplifies ringer signals coming out from MSM6575, and amplifying part that
amplifies signals coming out from MIC and transferring them to the audio processor.
MSM is the core elements of CDMA terminal and carries out the functions of CPU, encoder, interleaver,
deinterleaver, Viterbi decoder, Mod/Demod, and vocoder.
The memory part is made up of a NAND Flash memory and a SDRAM for storing data.
The power supply part is made up of circuits for generating various types of power, used for the digital/voice
processing part.
Once the main keypad is pressed, the key signals are sent out to MSM6575 for processing. Touch keypad is pressed,
Ack signals are sent out to MSM6575 for processing. In addition, when the key is pressed, the keypad/LCD lights up
through the use of 19 LEDs. The terminal status and operation are displayed on the screen for the user with the
characters and icons on the LCD.
Moreover, it exchanges audio signals and data with external sources through the receptacle, and then receives power
from the battery or external batteries.
MIC signals are amplified through OP AMP, inputted into the audio codec (included in MSM6575) and converted
into digital signals. Oppositely, digital audio signals are converted into analog signals after going through the audio
codec. These signals are amplified at the audio amplifier and transmitted to the ear-piece. The signals from
MSM6575 activate the ringer by using signals generated in the timer in MSM6575.
The MSM6575 device integrates the ARM1136-J™ and ARM926EJ-S™ processor cores, offering the ARM®
Jazelle™ Java® hardware accelerator: one low-power, high-performance QDSP5000™ application digital signal
processor (aDSP) and one QDSP4000™ modem digital signal processor (mDSP) core, hardware acceleration for
video, imaging, and graphics, and a wideband stereo codec to support enhanced digital audio applications. The
hardware acceleration eliminates the need for the multimedia companion processors normally required for video and
audio-based applications that support MP3 music files, a MIDI synthesizer, video and still image record and playback,
and 2D/3D graphics functions. By removing the need for costly applications coprocessors and memory subsystems,
the MSM6575 solution reduces BOM costs and increases standby and talk times. QUALCOMM provides a complete
software suite and advance mobile subscriber software (AMSS) for building handsets based on the MSM6575 chipset.
AMSS software is designed to run on a SURF phone platform, an optional development platform optimized to assist
in evaluating, testing, and debugging AMSS software.
Quad
LPF
Up- Baseband GPIOs w/TLMN
convert
Processor Memory support
Quad
LPF
Up-
[U109] [F102] convert
Interface with
Mobile Connectivity
Loop TX LO Other functions
S/W
coupler
Filter Circuit [U111]
Detector TX _ Gain
Control
RTR Air Interfaces Camera
VCTCXO [U103 ]
Quad- Loop Filter Buffer
6500 [U201]
Audio
ple xe r Pre- LNA
[U105] PRX LO
SBI Housekeeping MSM
Circuit
LPF ADC
ADC
6575
Quad
D’convert LPF ADC
[F101] General
N.C
GPIOs w/TLMN
LPF ADC Housekeeping
Quad
LG Electronics Inc.
D’convert
N.C LPF ADC Input Power
SRX LO PM Interfaces
[U112] Management
Circuit
[F103]
LPF LPF ADC
GPS Quad Output Voltage
GPS LO Regulation
BPF Circuit
D’convert LPF LPF ADC
GPS LNA
Module Loop Filter
AX8575
AX8575
LCD
In the bypass mode, MSM has complete control over all LCD operations, excluding camera processing function. In
other words, it indicates when LCD is initialized and GUI of system is displayed on the LCD.
CAMERA
DSP provides clock to operate sensor and controls internal register of sensor through the I2C master embedded in
DSP to make sensor operate normally. After completion of internal register setting, sensor supplies YUV422 image
data, synchronous signal and pixel clock synchronized with pixel of image data to DSP. VSYNC is a synchronized
signal to differentiate frames and HREF is a synchronized signal to differentiate lines. These signals are synchronized
with the pixel clock. Input image data through the sensor interface is previewed on the LCD up to 30fps through the
IMAGE ENHANCER.
EXTERNAL CODEC
Normally codec bypass signal from MSM6575 to Speaker, Receiver or Headset. However, when we listen to the
music in “My Music” folder codec performs 3-D sound enhancement and automatic level control for microphone or
line input. The on-chip ADC and DAC are of a high quality using a multi-bit, low-order oversampling architecture to
deliver optimum performance with low power consumption. It supports I2S audio data format between DSP and
codec. A speaker amplifier, using digital amplifier system, realizes low power consumption than that of linear
amplifier. In addition, power-down mode is available to minimize the current consumption when used.
CHAPTER
CHAPTER 4.
4. Trouble
Trouble Shooting
Shooting
4.1 Rx Part Trouble
Test
4.1.1 DCN Rx TestPoint
Point
Dual RX SAW Filter
Quadplexer
RTR6500 TCXO
Check
Checkflow
flow
Start
1. Check
DC Power Supply circuit 4. Check
RF Signal path
2. Check
VCTCXO NO
5. Check
Rx I/Q data
Test
TestPoint
Point
C173
C183 C176 C158
C171
C154 C156
C155 C170
C159
C174 C184
C178
C169
Circuit
CircuitDiagram
Diagram
TP1 TP2
RFIC(RTR6500)
TP7
TP3
TP8
TP4
TP9
TP5
TP6 TP10
TP11
Power Distributes in RTR6500
TP12 TP14
TP13 TP15
Checking
CheckingFlow
Flow
Start
Check C178,C169,C171,C173,C170
No The Problem may be Logic part
+2.1V_RX1 is OK? Refer to Logic troubleshoot
Yes
Check C176,C155,C158,C159,C154
No
The Problem may be Logic part
+2.1V_RX0 is OK? Refer to Logic troubleshoot
Yes
Check C156
No The Problem may be Logic part
+VDD_RX0_B is OK? Refer to Logic troubleshoot
Yes
Check C183 No The Problem may be Logic part
+VDD_RX0_D is OK? Refer to Logic troubleshoot
Yes
Check C184
No The Problem may be Logic part
+VDD_RX1_D is OK? Refer to Logic troubleshoot
Yes
Check C174
No The Problem may be Logic part
+VDD_RX1_B is OK? Refer to Logic troubleshoot
Yes
DC Power supply Circuit is OK. See next Page to check
VCTCXO circuit.
Test
TestPoint
Point
C175 U103
C109
Circuit
CircuitDiagram
Diagram
VCTCXO
TP1
RFIC(RTR6500)
TP2
Checking
CheckingFlow
Flow
Start
No
Check C109 No
The Problem may be Logic part
Is the output 2.85V?
Refer to Logic troubleshoot
(Refer to Fig. 4.1.1.(b))
Yes
Replace U103. And then recheck C175, C109.
No
Start
Waveform
Waveform
Test
TestPoint
Point
Top Side
TCXO
RTR6500
Dual
Rx SAW Filter
Quadplexer
Bottom Side
Mobile Switch
Circuit
CircuitDiagram
Diagram
TP1
TP2
Checking
CheckingFlow
Flow
Start
Yes
Yes
Yes
Yes
RF signal path is OK.
See next page to check Rx I/Q data signal.
Waveform
Waveform
U100 pin2
U105 pin1
Test
TestPoint
Point
RTR6500
U111 Pin55(RX0_IP)
Pin56(RX0_IM)
Pin57(RX0_QP)
Pin58(RX0_QM)
Circuit
CircuitDiagram
Diagram
Checking
CheckingFlow
Flow
Start
NO
NO
Waveform
Waveform
RX0_IP RX0_QP
RX0_QM
RX0_IM
Test
TestPoint
Point
Dual RX SAW Filter
Quadplexer
RTR6500 TCXO
Checking
CheckingFlow
Flow
Start
Rx TEST SETUP(Joyphone )
- Test C hannel: 600
- Tes t Band : U S PCS
- SID: 5269
- Sect or Power: - 30 dB m Spec trum Analyzer Setting
Osc illosc ope Setting
3. Check
Control signal
1. Check
DC Power Supply circuit 4. Check
RF Signal path
2. Check
VCTCXO NO
5. Check
Rx I/Q data
Test
TestPoint
Point
C173
C183 C176 C158
C171
C154 C156
C155 C170
C159
C174 C184
C178
C169
Circuit
CircuitDiagram
Diagram
TP1 TP2
RFIC(RTR6500)
TP7
TP3
TP8
TP4
TP9
TP5
TP6 TP10
TP11
TP12 TP14
TP13 TP15
Checking
CheckingFlow
Flow
Start
Check C178,C169,C171,C173,C170
No The Problem may be Logic part
+2.1V_RX1 is OK? Refer to Logic troubleshoot
Yes
Check C176,C155,C158,C159,C154
No
The Problem may be Logic part
+2.1V_RX0 is OK? Refer to Logic troubleshoot
Yes
Check C156
No The Problem may be Logic part
+VDD_RX0_B is OK? Refer to Logic troubleshoot
Yes
Check C183 No The Problem may be Logic part
+VDD_RX0_D is OK? Refer to Logic troubleshoot
Yes
Check C184
No The Problem may be Logic part
+VDD_RX1_D is OK? Refer to Logic troubleshoot
Yes
Check C174
No The Problem may be Logic part
+VDD_RX1_B is OK? Refer to Logic troubleshoot
Yes
DC Power supply Circuit is OK. See next Page to check
VCTCXO circuit.
Test
TestPoint
Point
C175 U103
C109
Circuit
CircuitDiagram
Diagram
VCTCXO
TP1
RFIC(RTR6500)
TP2
Checking
CheckingFlow
Flow
Start
No
Check C109 No
The Problem may be Logic part
Is the output 2.85V?
Refer to Logic troubleshoot
(Refer to Fig. 4.1.2.(b))
Yes
Replace U103. And then recheck C175, C109.
No
Start
Waveform
Waveform
Test
TestPoint
Point
Top Side
TCXO
RTR6500
Dual
Rx SAW Filter
Quadplexer
Bottom Side
Mobile Switch
Circuit
CircuitDiagram
Diagram
TP1
TP2
Checking
CheckingFlow
Flow
Start
YES
YES
YES
YES
Waveform
Waveform
U100 pin2
U105 pin2
Test
TestPoint
Point
RTR6500
U111 Pin55(RX0_IP)
Pin56(RX0_IM)
Pin57(RX0_QP)
Pin58(RX0_QM)
Circuit
CircuitDiagram
Diagram
Checking
CheckingFlow
Flow
Start
NO
NO
Waveform
Waveform
RX0_IP RX0_QP
RX0_QM
RX0_IM
4.2.1 DCN Tx
Test
TestPoint
Point
Top Side Bottom Side
Quadplexer
RTR6500
VCTCXO
Mobile Switch
Dual Tx SAW
Dual PAM
Checking
CheckingFlow
Flow
Start 4. Check
RF SAW
1. Check
NO
7. Check
DC Power Supply circuit
Mobile Switch
2. Check
VCTCXO Redownload S/W, Cal
3. Check
RTR 6500
Test
TestPoint
Point
C411
PMIC(MAX8675)
RTR6500
Circuit
CircuitDiagram
Diagram
PMIC(MAX8675)
TP1
Power Distributes in RTR6500
TP2
TP3
TP4
Checking
CheckingFlow
Flow
Start
Check C411.
No The Problem may be Logic part
+2.1V_TX is OK? Refer to Logic troubleshoot
Yes
Check C138.
No
The Problem may be Logic part
+2.1V_TX is OK? Refer to Logic troubleshoot
Yes
Check C120
No The Problem may be Logic part
+2.1V_TX is OK? Refer to Logic troubleshoot
Yes
Check C132 No The Problem may be Logic part
+VDD_TX_A is OK? Refer to Logic troubleshoot
Yes
DC Power supply Circuit is OK. See next Page to check
VCTCXO circuit.
Test
TestPoint
Point
C175 U103
C109
Circuit
CircuitDiagram
Diagram
VCTCXO
TP1
RFIC(RTR6500)
TP2
Checking
CheckingFlow
Flow
Start
No
Check C109. No
The Problem may be Logic part
Is the output 2.85V?
Refer to Logic troubleshoot.
(Refer to Fig. 4.2.1 (b))
Yes
Replace U103. And then recheck C175, C109.
No
Waveform
Waveform
Test
TestPoint
Point
C175(TCXO)
Pin#16(TX_ON)
C166
Circuit
CircuitDiagram
Diagram
RFIC(RTR6500)
C166(TP1)
DCN PA output
Pin#16
C175(TP2)
Checking
CheckingFlow
Flow
Start
No
Check pin#16.(TX_ON)
No
Check TX_ON signal & MSM.
Whether the level is higher than 2.5V.
Yes
Check C175 No
Refer to Fig. 4.2.1.4 (d). Check TCXO circuit.
Is it similar?
Yes
Replace U107.
Waveform
Waveform
Test
TestPoint
Point
F102
C166
C149
Circuit
CircuitDiagram
Diagram
C149(TP1)
C166(TP2)
Checking
CheckingFlow
Flow
Start
Check C149, C166. Yes RF Tx SAW circuit is OK. See next page
Refer to Fig.4.2.1 (e).
to check DCN PA.
Is it similar?
No
Replace F102.
Waveform
Waveform
RF_IN
RF_OUT
Test
TestPoint
Point
C123(PA_OUT)
C149(PA_IN)
C146(VMOD, PA_R1)
C147(VBP, PA_R0)
C145(PA_ON0)
C187(VCC1, VCC2)
Dual PAM(U109)
Circuit
CircuitDiagram
Diagram
C187(TP1)
C149(TP2)
C123(TP3)
C147(TP4)
C146(TP5)
C145(TP6)
Checking
CheckingFlow
Flow
Start
No
Yes
Check C145(PA_ON0)
No
Check PA_ON0 line.
whether it is higher than 2.2V.
Yes
Check C146(VMOD,
Check C132 PA_R1) No
Check PA_R1 line.
Whether
+VDD_TX_A
it is lower
is than
OK? 0.5V
Yes
Check Check
C147(VBP,
C132PA_R0) No
Check PA_R0 line.
Whether
+VDD_TX_A
it is lower
is than
OK? 0.5V
Yes
Replace U109.
Waveform
Waveform
RF_IN RF_OUT
Test
TestPoint
Point
U105
L100(ANT_port) Pin#3(DCN_TX_Port)
Circuit
CircuitDiagram
Diagram
L100(TP1) TP2
Checking
CheckingFlow
Flow
Start
Check L100, pin#3. Yes Quadplexer circuit is OK. See next page
Refer to Fig.4.2.1 (g).
to check mobile switch.
Is it similar?
No
Replace U105
Waveform
Waveform
DCN_TX_Port ANT_Port
Test
TestPoint
Point
U102(Mobile Switch)
L101(RF_IN)
L127(RF_OUT)
Circuit Diagram
Circuit Diagram
L101(TP1) L127(TP2)
Checking
CheckingFlow
Flow
Start
No
Replace U102.
Waveform
Waveform
RF_IN RF_OUT
4.2.2 PCS Tx
Test
TestPoint
Point
Top Side Bottom Side
Quadplexer
RTR6500
VCTCXO
Mobile Switch
Dual Tx SAW
Dual PAM
Checking
CheckingFlow
Flow
Start 4. Check
RF SAW
1. Check
NO
7. Check
DC Power Supply circuit
Mobile Switch
2. Check
VCTCXO Redownload S/W, Cal
3. Check
RTR 6500
Test
TestPoint
Point
C411
PMIC(MAX8675)
RTR6500
Circuit
CircuitDiagram
Diagram
PMIC(MAX8675)
TP1
Power Distributes in RTR6500
TP2
TP3
TP4
Checking
CheckingFlow
Flow
Start
Check C411.
No The Problem may be Logic part
+2.1V_TX is OK? Refer to Logic troubleshoot
Yes
Check C138.
No
The Problem may be Logic part
+2.1V_TX is OK? Refer to Logic troubleshoot
Yes
Check C120
No The Problem may be Logic part
+2.1V_TX is OK? Refer to Logic troubleshoot
Yes
Check C132 No The Problem may be Logic part
+VDD_TX_A is OK? Refer to Logic troubleshoot
Yes
DC Power supply Circuit is OK. See next Page to check
VCTCXO circuit.
Test
TestPoint
Point
C175 U103
C109
Circuit
CircuitDiagram
Diagram
VCTCXO
TP1
RFIC(RTR6500)
TP2
Checking
CheckingFlow
Flow
Start
No
Check C109. No
The Problem may be Logic part
Is the output 2.85V?
Refer to Logic troubleshoot
(Refer to Fig. 4.2.2(b))
Yes
Replace U103. And then recheck C175, C109.
No
Waveform
Waveform
Test
TestPoint
Point
C175(TCXO)
C164
Pin#16(TX_ON)
Circuit
CircuitDiagram
Diagram
RFIC(RTR6500)
C164(TP1)
PCS PA output Pin#16
C175(TP2)
Checking
CheckingFlow
Flow
Start
No
Check pin#16.(TX_ON)
No
Check TX_ON signal & MSM.
whether the level is higher than 2.5V.
Yes
Check C175
No
Check TCXO circuit.
Refer to Fig. 4.2.2 (d). Is it similar?
Yes
Replace U108.
Waveform
Waveform
Test
TestPoint
Point
C148
C164
F102
Circuit
CircuitDiagram
Diagram
C148(TP1)
C164(TP2)
Checking
CheckingFlow
Flow
Start
Check C148, C164. Yes RF Tx SAW circuit is OK. See next page
Refer to Fig.4.2.2 (e).
to check PCS PA.
Is it similar?
No
Replace F102.
Waveform
Waveform
RF_IN
RF_OUT
Test
TestPoint
Point
Dual PAM(U109)
C146(VMOD, PA_R1)
C147(VBP, PA_R0)
C142(PA_ON1)
C187(VCC1, VCC2)
C148(PA_IN)
C122(PA_OUT)
Circuit
CircuitDiagram
Diagram
C187(TP1)
C146(TP3)
C147(TP4)
C142(TP5)
C148(TP6)
C122(TP2)
Checking
CheckingFlow
Flow
Start
No
Yes
Check C142(PA_ON1)
No
Check PA_ON1 line.
whether it is higher than 2.2V.
Yes
Check C146(VMOD,
Check C132 PA_R1) No
Check PA_R1 line.
Whether
+VDD_TX_A
it is lower
is than
OK? 0.5V
Yes
Check Check
C147(VBP,
C132PA_R0) No
Check PA_R0 line.
Whether
+VDD_TX_A
it is lower
is than
OK? 0.5V
Yes
Replace U109.
Waveform
Waveform
RF_IN RF_OUT
Test
TestPoint
Point
Pin#4(PCS_TX_Port)
U105
L100(ANT_port)
Circuit Diagram
Circuit Diagram
L100(TP1) TP2
Checking
CheckingFlow
Flow
Start
Check L100, pin#4. Yes Quadplexer circuit is OK. See next page
Refer to Fig.4.2.2 (g).
to check mobile switch.
Is it similar?
No
Replace U105.
Waveform
Waveform
PCS_TX_Port ANT_Port
Test
TestPoint
Point
U102(Mobile Switch)
L101(RF_IN)
L127(RF_OUT)
Circuit Diagram
Circuit Diagram
L101(TP1) L127(TP2)
Checking
CheckingFlow
Flow
Start
No
Replace U102
Waveform
Waveform
RF_IN RF_OUT
4.3.1 Power
+1.2V_MSMC1
+2.3V_BUCK2
+2.6V_MSMP
+1.8V_MSMP1
PMIC +2.6V_MSMA
(U400)
+2.85V_TCXO
TCXO_OUT
TCXO_IN
Circuit
CircuitDiagram2
Diagram2
PS_HOLD
PMIC
(U400)
USB_FULL SPEED D+
USB_FULL SPEED D-
Circuit
CircuitDiagram3
Diagram3
CON400
10
6
8
HSMU-5SB-24DR2
GND1
GND3
GND5
1
+V_CHAR P1 <VBUS>
USB_D-
2
1608 P2 <D->
10n
C401
47p
C406
C400
1608
10n
R407 3
P3 <D+>
USB_D+
200k
4
+2.6V_MSMA P4 <ID>
ICVL0505101V150FR
5
P5 <GND>
ACC_ADC
TVS,5V,100W
TVS,5V,100W
GND2
GND4
11 GND6
SDB1040
D402
D401
R431
C408
D400
33n
9
7
USB_FULL SPEED D-
USB_D-
U401
UART-TP
NC3
C402
12
27p
NC2
11
NC1
10
USB_D+
9
USB_D-
8
+V_CHAR 7
USB-POWER
USB_D+ +VPWR 6
VBATT
PWR_ON_SW ON_SW
C403
F400 5
27p
DG2722
USB_FULL SPEED D+
V_CHAR
4
1 6 UART-TXD
D+ HSD1- 3
2 7 UART-RXD
D- 2
USB SW
HSD1+
3 8 GND
GND _OE USB20_EN/ 1
4 9 R408 100
HSD2- V+ +VPWR
5 10
USB20_SEL
(F400)
HSD2+ S
C407
100n
USB20_D+
USB_HIGH SPEED D+
USB20_D- R416
USB_HIGH
TA_DET/
SPEED D- 22k
+2.6V_MSMP2
R409 C3
470k
2 Q400
USB_D- B KTC4075E
R410
150k
+/-1% E1
DSP SIA417D
0.1u
C409
F601
7
D5
1 6
D1 D4
2 5
D2 D3
3 4
G S1 +1.3V_DSP_CORE
S2
8
DSP_USB_PWR_EN/
+2.6V_MSMP2
+1.8V_DSP_IO
+3.3V_DSP_USB
+1.3V_DSP_CORE +3.0V_DSP_IO
2.2u
1u
1u
1u
1u
2.2u
C600 1u
1u
1u
C612 1u
1u
C611 10n
1u
1u
1u
1u
1u
1u
C604
C605
C601
C602
C603
C606
C607
C614
C613
C644
C618
C617
C610
C620
C615
E11
J2
A5
C1
C3
K6
D8
H3
K5
E5
G6
D5
B5
D3
H4
G3
L5
VDDA33_USB
VDDAP_DAC
VDDAA_DAC
VDDD_CO1
VDDD_CO234
VDDD_CO567
VDDD12_USB
VDDD12_PLL
VDDQ
VDDD_GA
VDDD_MC
VDDD_GB
VDDD_GC
VDDD_GD
VDDA_OSC
VDDD_GE
VDDD_RTC
TP608
J7
D2[0] GPIO_A0
J8
D2[1] GPIO_A1 TP617
H8
D2[2] GPIO_A2
K10
D2[3] GPIO_A3 J5
L9 PWRON DSP_PWRON
D2[4] GPIO_A4
K11
D2[5] GPIO_A5 A6
K9 LHPOUT AMP_L
D2[6] GPIO_A6
L10
D2[7] GPIO_A7 A7
J9 RHPOUT AMP_R
D2[8] GPIO_A8
L11
D2[9] GPIO_A9 B6
H7 HVCOM
D2[10] GPIO_A10
J11 TP620
D2[11] GPIO_A11 A3
H10 LOUT
D2[12] GPIO_A12 A4
H11 ROUT
D2[13] GPIO_A13 TP621
H9
D2[14] GPIO_A14 B3
G11 BPLIN
TP601 D2[15] GPIO_A15 B4
G7 BPRIN
TP602 DSP_INT/ GPIO_A16
G9
TP603 EBI2_AD GPIO_A17 A2
VREF
0.1u
0.1u
G10 CS/
DSP_CS/ GPIO_A18 A1
10u
10u
TP604 VMID
F9 WR/
WE2/ GPIO_A19
TP605 F6 OE/
OE2/ GPIO_A20 R606 68k
C623
C625
C622
C624
F4
F11 DACIOEN
GPIO_A21 G4 R640 68k
F10 I2CIOEN
GPIO_A22
F8
DSP
GPIO_A23 H1
G8 GPIO_E0
GPIO_A24 F2
D9 GPIO_E1
GPIO_A25 G1
GPIO_E2
B10 F3
MOVI_D[0]
A11
GPIO_B0
U600 GPIO_E3
G2
MOVI_D[1]
B11
GPIO_B1
TCC8121 GPIO_E4
(U600)
10p
A10 K4
MOVI_D[3] GPIO_B3 XIN
B9 GPIO_B4 L4
XOUT
DSX321G_12MHZ_8PF
A9 GPIO_B5
4
C9 GPIO_B6 H2
XTIN
C7 J4
1M
GPIO_B7 XTOUT
U511
B8
MOVI_CMD GPIO_B8
D6 L7
GPIO_B9 nTRST NTRST
C8 H5
MOVI_CLK DSP_TDI
R623
GPIO_B10 TDI
C6 K8
GPIO_B11 TMS DSP_TMS
3
R610 D7 J6
100k
GPIO_B12 TCK DSP_TCK C632
C5 L8 8p
GPIO_B13 RTCK DSP_RTCK
B7 H6
GPIO_B14 TDO DSP_TDO
R621
D10 1
DSP_SD_DATA[0] GPIO_C0
USB_HIGH SPEED D+
K7
F7
nRESET DSP_RESET/
DSP_SD_DATA[1] GPIO_C1
C10
DSP_SD_DATA[2] GPIO_C2
USB_VBUS
K1 R622
E8
DSP_SD_DATA[3] GPIO_C3 L2 NRESET
D11
USB_DP USB20_D+ R620
DNI
DSP_SD_CMD GPIO_C4 L1
E10 USB_DM USB20_D- +3.3V_DSP_USB
DSP_SD_CLK GPIO_C5
USB_TXRTUNE
J1 DNI
USB_HIGH SPEED D-
C11 44.2 R619
TP600 GPIO_C6
10k
D1 J10
DSP_USB_DETECT GPIO_D0 SDR_CKE
R617
E1 R618
DSP_SD_DETECT 100k R608
GPIO_D1
4.7k
D2 G5
GPIO_D2 TEST
TP619 E2
GPIO_D3
VSSD12_CO1
VSSD12_CO4
VSSD12_PLL
VSSA33_USB
VSSD12_CO7
VSSD12_CO2
F1
VSSAP_DAC
VSSAA_DAC
TP606 GPIO_D4
VSSA_OSC
E3
VSSD_GD
VSSD_GB
VSSD_MC
VSSD_GE
VSSD_GC
VSSD_GA
TP607 GPIO_D5
VSSQ
A8
B1
B2
C2
C4
D4
E4
E6
E7
E9
F5
J3
K2
K3
L3
L6
Circuit
CircuitDiagram4
Diagram4
+VBATT
+1.3V_DSP_CO
RE
+1.8V_DSP_IO
SUB PM
(U601) +3.3V_DSP_US
B
+3.0V_DSP_IO
+3.0V_DSP_SD
DSP
(U600)
Test
Testpoint
point
USB_D+
+1.8V_MSMP1 USB_D-
+1.2V_MSMC
PS_HOLD +2.6V_MSMPA
+VBATT +2.3V_BUCK2
+2.6V_MSMP2
PMIC
U400
+USB_FULL
SPEED D+
+USB_FULL
SPEED D-
+TCXO_IN
+2.85V_TCXO
SLEEP CLK
LDO
+1.3V_DSP_COR
+3.0V_DSP_IO E
TCXO_OUT
+3.3V_DSP_USB +1.8V_DSP_IO
Checking
CheckingFlow
Flow
START
Check battery voltage > 3.4V Charge of Change Battery and try again
NO
YES
YES
YES
YES
YES
YES
Checking
CheckingFlow
Flow
Logic level of
Replace MSM (U202)
PS_HOLD=High? NO
YES
Does it work properly?
NO
Redownload sw again
Change the board
YES
NO
+5V_VCHAR
CON400
USB_DETECT
ACCESSORY_ADC
+VBATT
CHG_MODE
Test
Testpoint
point
ACCESSORY_ADC
USB_DETECT
CON400
+VBATT
+5V_VCHAR
CHG_MODE
Checking
CheckingFlow
Flow
START
Battery Change
NO
YES
YES
YES
YES
NO
When the phone is charged, Change the MSM (U201)
CHG_MODE(R428)=0V?
Checking
CheckingFlow
Flow
USB_DETECT
If connect USB Cable, 2.6V Replace Q400
If connect TA, 0V ? NO
YES
download software
try again
Circuit
CircuitDiagram
Diagram
Test
TestPoint
Point
CAM_MCLK
+2.8V_CAM
_CORE
+2.8V_CAM
_ANALOG
+2.8V_CAM
_IO
CAM_PCLK
Check
Checkflow
flow
START
YES
YES
YES
YES
4.3.3 LCD
Circuit
CircuitDiagram
Diagram
Test
TestPoint
Point
+2.8V_LCD
MD DI FILTER
Check
Checkflow
flow
START
YES
YES
YES
Circuit
CircuitDiagram
Diagram
Test
TestPoint
Point
TP5002
SCL
SDA
LED_VOUT
Check
Checkflow
flow
LCD Backlight
START
YES
YES
Test
TestPoint
Point
+2.6V_TOUCH
TOUCH_PENIRQ/
TOUCH_SCL
TOUCH_SDA
TP5002
Checking
CheckingFlow
Flow
Start
YES
YES
YES
NO
Circuit
CircuitDiagram
Diagram
Test
TestPoint
Point
+3.0V_LIN_MOTOR
LIN_PWM_FREQ
LIN_MOT_EN
Checking
CheckingFlow
Flow
Start
NO
YES
YES
YES
Circuit
CircuitDiagram
Diagram
Test
TestPoint
Point
GC2
GC1
+3.0V_PD_SENSOR
IOUT
Checking
CheckingFlow
Flow
Start
NO
YES
CHECKING THE GC1 & GC2 & IOUT? Change the PHOTO SENSOR
NO
YES
YES
Circuit
CircuitDiagram
Diagram
PMIC
Test
Testpoint
point
TP500
U502
R508
C505
R506
Checking
CheckingFlow
Flow
START
NO
Check the Voltage of C505 = 2.6V ? Replace U400
YES
NO
Logic level High at TP500 ? Replace U502
YES
YES
NO
Dose it work properly ? Change FPCB
YES
YES
YES
Circuit
CircuitDiagram
Diagram
FPCB
MAIN
Test
Testpoint
point
U103
R105
R109
R107 C104
Checking
CheckingFlow
Flow
FPCB
START
NO
Check the Voltage of C430 = 2.8V ? Change main board
YES
NO
Check the Voltage of C104 = 2.8V ? Change FPCB
YES
NO
Check the I2C & Logic
Replace U103
High Level at R105 = 2.8V ?
YES
4.3.9 Audio
Circuit
CircuitDiagram
Diagram
NAND_FLASH_CS/
+1.275V_MSMC
SDRAM_DQM[1]
SDRAM_DQM[0]
SDRAM_CLK_EN
100n
+1.8V_MSMP1
NAND_READY/
HS_UART_CS/
10n
10n
10n
HOST_WAKEUP
10n
0.1u
MOVI_SD_EN
SDRAM_RAS/
SDRAM_CAS/
SUB_PM_SCL
SUB_PM_SDA
LCD_RESET/
10n
SDRAM_CLK
SDRAM_WE/
SDRAM_CS/
NANDF_ALE
NANDF_CLE
NANDF_WP/
1u
1608
C227
LCD_CS/
TA_DET/
10u
D1[25]
D1[24]
D1[11]
D1[10]
D1[31]
D1[30]
D1[29]
D1[28]
D1[27]
D1[26]
D1[15]
D1[14]
D1[13]
D1[12]
SLEEP/
C211
C213
C209
C210
C212
D1[1]
A[14]
A[13]
A[12]
A[10]
D1[9]
D1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[0]
A[11]
C215
C216
A[4]
A[7]
A[6]
A[2]
A[1]
A[0]
A[8]
A[5]
A[3]
OE2/
WE2/
A[9]
C214
+2.6V_MSMP2
10n
10n
10n
100n
AD11
AB14
AE12
AD13
AD14
TP200
W14
AE4
V15
T18
AE6
H21
F22
E24
H19
J19
R21
AA1
AD8
B10
B13
AE8
AD5
AD9
D24
F24
R24
A23
VDD_C11 AB2
AD7
R4
R5
N8
T2
T1
P5
P4
M8
P7
N5
P2
P1
K4
K7
K5
J1
J5
J2
J4
N4
J7
V4
M4
G1
K8
R7
N1
N2
N7
M7
M5
L5
L8
L7
L1
V1
V5
E2
Y1
G2
H5
G4
H4
B4
Y5
L2
L4
R8
V2
W4
U5
Y4
D2
H2
W2
VDD_P1_1 F2
K2
M2
R2
U2
XMEM2_CS_N[1]
XMEM2_CS_N[0]
BT_CLK/GPIO[25]
LCD2_EN/GPIO[37]
A1[14]
A1[13]
A1[12]
A1[11]
A1[10]
D1[15]
D1[14]
D1[13]
D1[12]
D1[11]
D1[10]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
GPIO[79]/SDRAM1_A[0]
GPIO[77]/XMEM1_CS_N[3]
SDRAM1_CS_N[0]/XMEM1_CS_N[2]
GPIO[76]/XMEM1_CS_N[1]/SDRAM_CS_N[3]
XMEM1_CS_N[0]/SDRAM_CS_N[2]
NAND2_FLASH_READY/GPIO[33]
NAND2_ALE/LB2_N/A2[0]
BT_SBST/GPIO[24]
BT_SBCK/GPIO[23]
BT_SBDT/GPIO[22]
A1[9]
A1[8]
A1[7]
A1[6]
A1[5]
A1[4]
A1[3]
A1[2]
A1[1]
D1[9]
D1[8]
D1[7]
OE1_N/SDRAM_CLK_EN[2]
LCD2_CS_N/GPIO[38]
BT_DATA/GPIO[20]
BT_TX_RX_N/GPIO[21]
A1[15]/SDRAM1_D[24]
SDRAM1_DQM[0]/LB1_N
SDRAM1_DQM[1]/UB1_N
SDRAM1_WE_N/WE1_N
VDD_C10
SDRAM1_CLK/ROM1_CLK
SDRAM1_CLK_EN
SDRAM1_RAS_N/ROM1_ADV_N
NAND2_CLE/UB2_N
SDRAM1_CAS_N/XMEM1_LWAIT_N
A1[16]/SDRAM1_S[25]
A1[17]/SDRAM1_D[26]
VDD_P1_2
VDD_P1_3
VDD_P1_4
VDD_P1_5
A1[18]/SDRAM_D[27]
NAND2_RE_N/OE2_N
HROM1_WAIT_N
WE2_N
VDD_C12
VDD_C13
A1[21]/SDRAM1_D[30]
A1[20]/SDRAM1_D[29]
A1[19]/SDRAM1_D[28]
VDD_C1
VDD_C2
VDD_C3
VDD_C4
VDD_C5
VDD_C6
VDD_C7
VDD_C8
VDD_C9
VDD_P2_1
VDD_P2_2
VDD_P2_3
A1[22]/SDRAM1_D[31]
VDD_Qfuse
C218
C220
C224
C222
G25 SBST
SSBI1
TP201
E9
AUX_SBDT/GPIO[4]
AUX_SBCK/GPIO[7]
VDD_A2 N22 <TEMP.DETECT>
0.1u
B17
100n
100n
VDD_A3
10n
AB24
RX0_I_P I_IP_CH0 AD21
VDD_A4
AA24 R208
RX0_I_M I_IM_CH0
AA16 22k
VDD_A5
W24
RX0_Q_P Q_IP_CH0 AD16 +2.85V_TCXO TEMP_ADC
VDD_A6
C221
C217
C219
C223
Y24
RX0_Q_M Q_IM_CH0
33n
C225
AD22
+/-1%
150k
R212
V24 VDD_A7
RX1_I_P I_IP_CH1 T24
U24 VDD_A8 R211
1
RX1_I_M I_IM_CH1 T25 1608
U22 VDD_A9
NCP18WD683E03RB
RX1_Q_P Q_IP_CH1 W25
V22 VDD_A10
RX1_Q_M Q_IM_CH1 Y25
VDD_A11
B11
TX_I_P I_OUT B20
B12
VDD_MDDI +1.8V_MSMP1
C202 TX_I_M I_OUT_N AA14
A12 A2[19]
10n
TX_Q_P Q_OUT V14
+2.6V_MSMA A11 A2[18]
TX_Q_M Q_OUT_N AB13
D12 A2[17] EBI2_AD
DAC_REF DAC_REF AD12
A2[16] A2[16]
U201
G11
PA_ON1 PA_ON1/GPIO[2] W13
E16 A2[15] A2[15]
PA_ON0 PA_ON0 AB12
E11 A2[14] A2[14]
TX_ON TX_ON
MSM6575-NSP
AA13
D17 A2[13]
PA_R1 PA_RANGE1 AE10
G17 A2[12]
PA_R0 PA_RANGE0 AD10
D20 A2[11]
TCXO_EN TCXO_EN/GPIO[94] AB11
H13 A2[10]
TRK_LO_MSM TRK_LO_ADJ AA12
E13 A2[9]
TX_AGC_ADJ TX_AGC_ADJ
N24
PA_POWER_CTL
A2[8]
A2[7]
W12
V13
<PCB Revison CHECK>
AA22
PA_DAC_EXT_REF AB10
Y22 A2[6]
BATT_ADC HKAIN[5] AA11
AA21
A2[5]
W21
V17
V18
ACC_ADC
N14
N15
P14
P15
U18
P11
P12
P13
V19
W19
AA5
HKAIN[4] AB9
V9
R210
U8
V8
W7
U19 A2[4]
VICHG HKAIN[3] V12
100k
AD23 A2[3] +2.85V_TCXO VER_ADC
TEMP_ADC HKAIN[2] AA9 +/-1%
W22 AB4 A2[2]
BATT_TEMP_ADC
C226
HKAIN[1] AA10
33n
R213
V21 AB22 A2[1]
75k
VER_ADC HKAIN[0] AA8
D18 A1 AC1 D2[15] D2[15]
MSM_TCXO TCXO
AB8
A9 A2 AC25 D2[14] D2[14]
USB_XTAL_48_IN W11
B9 A3 AD1 D2[13] D2[13]
USB_XTAL_48_OUT W10
C230 27p A15 A24 AD2 D2[12] D2[12]
SLEEP_XTAL_IN AD6
B15 A25 AD24 D2[11] D2[11]
1
SLEEP_XTAL_OUT AB7
R200
G13 B1 AD25 D2[10] D2[10]
1m X202 RESIN/ RESIN_N V11
G12 RESOUT_N B2 AE1 D2[9] D2[9]
W9
2
H9
H17
H18
N11
N12
M13
L14
L15
M11
M12
N13
J18
L12
L13
M14
M15
MDDIC_DATP T8
NL17SZ16XV5T2G B22 GPIO[75]/SDRAM1_DQM[3] SDRAM_DQM[3]
MDDIC_DATN U4
U200
A21 MDDIC_STBP
GPIO[74]/SDRAM_CLK_EN[3]
U7
D1[23] H 100K 56K 61,70
A22
GPIO[73] D1[22]
MDDIC_STBN AA2
M25 GPIO[72] D1[21] 1.0 100K 75K 71,83
USB_DATA USB_DAT_VP Y2
N21 GPIO[71] D1[20]
USB_SE0 USB_SE0_VM E1
M24
USB_OE_TP_N
GPIO[70] D1[19] 1.1 100K 100K 84,97
USB_OE/ GPIO[69]
P8
D1[18]
P18
DSP_PWRON USB_RX_DATA/GPIO[29] T4
J25
USB_SUSPEND/GPIO[17]
GPIO[68] D1[17] 1.2 100K 130K 98,AC
CAM_RESET/ GPIO[67]
T7
D1[16]
H10
HS_UART_RES/ RX_VCO_SEL/GPIO[43]
G9
GPIO[66]
JDET_INT
A5 UHF_VCO_1_SEL/GPIO[28] H14
CAM_PWR_DOWN
AA17
CAMIF_FOCUS[1]/GPIO[64] FMR_RBDS_INT
HPH_R HPH_R D10
W17 GPIO[53] BT_RESET/
HPH_L HPH_L G10
GPIO[52]
E14 MMC_DATA/GPIO[32] PMIC_IRQ/
A6
GPIO[51] AUDIO_SW1_EN
3D & FMR I2C BAT_ID_PULL_UP L18
G14
MMC_CLK/GPIO[31]
GPIO[50]
B6
KYPD[11]
MMC_CMD/GPIO[30]
H11
E19 GPIO[49] KYPD[9]
CAM_D[7] CAMIF_DATA9/GPIO[61] D5
G16 GPIO[45] CP_RESET/
CAM_D[6] CAMIF_DATA8/GPIO[60] D8
D21 GPIO[44] LIN_PWM_FREQ
CAM_D[5] CAMIF_DATA7/GPIO[59]
E8
H15 GPIO[42] PS_HOLD
CAM_D[4] CAMIF_DATA6/GPIO[58]
G8
K18 GPIO[40] HS_UART_LOWPWR
CAM_D[3] CAMIF_DATA5/GPIO[57]
D7
D19
CAMIF_FOCUS[0]/GPIO[39] EAR_JACK_SENSE
CAM_D[2] CAMIF_DATA4/GPIO[56] AA15
G21 GPIO[36]/XMEM2_CS_N[3] DSP_INT/
CAM_D[1] CAMIF_DATA3/GPIO[55] W15
GPIO[35]/XMEM2_CS_N[2] DSP_CS/
AUX_PCM_SYNC/SDAC_L_R_N/TSIF_ERROR/[GPIO102]
E18
CAM_D[0] CAMIF_DATA2/GPIO[54] AE11
DSP_RESET/
AUX_PCM_DOUT/SDAC_DOUT/TSIF_INTR/GPIO[103]
H25 GPIO[34]/A2[20]
3D_FMR_I2C_SCL CAMIF_DATA1/GPIO[81] E22
GPIO[19] PROXI_SCL
AUX_PCM_CLK/SDAC_CLK/TSIF_NULL/GPIO[80]
H24
3D_FMR_I2C_SDA CAMIF_DATA0/GPIO[83] M18
E6 GPIO[18]/RINGER AUDIO_SW2_EN
CAM_VSYNC CAMIF_VSYNC/GPIO[16]
D6
F21 GPIO[12]/GRFC[9] TOUCH_I2C_SCL
CAM_HSYNC CAMIF_HSYNC/GPIO[15]
E7
J22 GPIO[11]/GRFC[8] TOUCH_I2C_SDA
CAMIF_PCLK/GPIO[82]
CAM_PCLK P22
PROXI_SDA
AUX_PCM_DIN/SDAC_MCLK/GPIO[14]
KEYSENSE3_N/GPIO[47]
KEYSENSE2_N/GPIO[46]
KEYSENSE1_N/GPIO[63]
KEYSENSE0_N/GPIO[62]
K22
PROXI_OUT
SYNTH2/GPIO[65]
SYNTH1/GPIO[41]
SYNTH0/GPIO[92]
UIM2_RESET/TSIF_ENABLE/GPIO[86] L22
M21 CAMIF_ZOOM[1]/UART1_DP_RX/GPIO[96] MKEY_BL_EN
3D_INT UIM2_PWR_EN/TSIF_DATA/GPIO[85] K25
CAMIF_ZOOM[0]/UART1_DP_TX/GPIO[95]
EAR_MIC_KEY M19
UIM2_DATA/TSIF_SYNC/GPIO[84] CHG_MODE/
LINE_R_IN
LINE_R_IP
LINE_L_IN
LINE_L_IP
RESERVED1
RESERVED2
GND_RET1
HPH_VREF
GND_RET2
V7
MICBIAS
LINE_OP
LINE_ON
AUX_OUT
LCD_VSYNC_OUT MDP_VSYNC_PRIMARY/GPIO[105]
EAR1OP
EAR1ON
TRST_N
MIC1P
MIC1N
MIC2P
MIC2N
AUXIP
AUXIN
CCOMP
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
AA4
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
SD_DETECT/ MDP_VSYNC_SCONDA/GPIO[104]
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
RCLK
TMS
TDI
TDO
TCK
CON200
JTAG_STD_2COLUMN_10P
H1
R25
W1
A4
A10
A13
AB1
AE7
AE14
U1
M22
F25
R1
M1
K1
F1
AE5
AE9
AE13
P25
A8
A14
AC24
B23
D1
D25
AA20
E15
G15
D14
A16
D16
D15
AE21
U25
V25
W16
W18
K21
N18
AE22
U21
P21
D13
P19
R19
V16
L19
E4
C24
AA19
AE15
G22
G18
AB19
AE16
B16
A20
A17
AA25
AB15
AB25
D11
E17
N25
T19
AB16
AB17
H7
B5
AE18
AE17
AE20
AE19
AD18
AD17
AB20
AB21
AB18
AA18
1
TCK TCK
2
RTCK RTCK
3
1u
TDO
1u
C208
TDO
1u
4
22n
22n
22n
22n
TDI TDI
RCV-
RCV+
C201
C200
5
TMS TMS
22n
TCK
22n
6
TRST_N TRST
LCD_ID_CHECK
KYPD[7]
KYPD[5]
KYPD[3]
KYPD[1]
C206
HS_UART_INT
ONO/
C204
C203
C205
BT_WAKEUP
RTCK 7
+2.6V_MSMP2 VCC
TDO 8
C229
RESIN/ RESIN
C228
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_SYNC
TDI 9
BT_PCM_CLK
FMR_ANALOG_R
FMR_ANALOG_L
PS_HOLD PS_HOLD
TMS 10
GND
TRST_N
MIX_L
MIX_R
MIC+
EAR_MIC
CAM_SDA
CAM_SCL
C207
0.1u
R207
2.2k
MIC_BIAS
Circuit
CircuitDiagram
Diagram
<AUDIO SUBSYSTEM>
C531
1u
+2.6V_MSMP2 R500 0
+VPWR
FMR_ANALOG_R
B1
B4
C502
C503
100n
LSVDD
VDD
1u
HPH_L
E1 A4
MIX_R INM+ LSOUT+ SPK+
16
15
14
13
NLAS3799BMNR2G
D1 A3
U503
MIX_L INM- LSOUT- SPK-
COMA
NOA
VCC
NCD
C500
220n
1 12 C2 D2
AMP_R NCA COMD INR SET
2 11 C501 R509
AUDIO_SW1_EN IN_A_B NOD
220n 24
3 10 C1 U500 E3
FMR_ANALOG_L NOB IN_C_D INL HPL LHP_EJ
4 9 LM49151
COMB NCC
+2.6V_MSMP2 C3
C510
100n
C512
100k
BYPASS
COMC
GND
NCB
NOC
R501
1.2k
R502
1.2k
A1
I2CVDD
B2
5
7
8
R503
AUDIO_I2C_SDA SDA
24
B3 E2
AMP_L AUDIO_I2C_SCL RHP_EJ
CPVSS
CPGND
SCL HPR
GND
C1N
C1P
ICVS0505500FR
ICVS0505500FR
A2
C4
D3
D4
E4
C504
2.2u
AUDIO_SW2_EN
HPH_R
C507
2.2u
C509
2.2u
10k
10k
R531
< TO FPCB CONNECTOR >
R532
R507
R505
CON701 +2.6V_MSMP2
AXT534124
1 34
2 33 R710 100
RCV+
R706
2.2k
R717
2.2k
KYPD[7]
3 32
RCV- +VPWR
4 31
SPK+
5 30 PROXI_SCL
SPK-
PWR_ON_SW 6 29
PROXI_SDA
R716 100 7 28
KYPD[11] PROXI_OUT
R709 100 27
KYPD[9]
8 PD_OUT
R711 100 9 26
KYPD[5] R712
PD_GAIN_CTRL1
100 10 25
KYPD[3] PD_GAIN_CTRL2
R713 100 11 24
KYPD[1] MKEY_BL
12 23
+2.8V_PROXI
13 22
LHP_EJ +3V_PD_SENSOR
14 21
RHP_EJ MIC+
15 20
EAR_JACK_SENSE MIC_BIAS
16 19
EAR_MIC
17 18
FMR_ANT
ESD9X5_0ST5G
ESD9X5_0ST5G
ULCE0505C015FR
DUMMY
35
36
37
38
ESD9X5_0ST5G
R700
C708
C729
100p
C702
C704
C722
C705
100p
C706
100p
C707
100p
C723
C703
100p
C727
C728
R718
10n
33p
33p
27p
27p
27p
1u
R707
R708
1
Test
Testpoint
point
C500
R500
C502
R507
R505
C503
Test
Testpoint
point
L102
L101
Checking
CheckingFlow
Flow
START
Voltage at R500,C502,C503 NO
Check the battery Voltage
Is about 4.2V
Yes
NO NO
Check the audio signal at Check the Soldering of
Replace U503 or MSM
C500, C501 C500, C501
Yes
Yes
Re-solder C500, C501
Yes
Yes
Yes
Circuit
CircuitDiagram
Diagram
MSM6575
NAND_FLASH_CS/
+1.275V_MSMC
SDRAM_DQM[1]
SDRAM_DQM[0]
SDRAM_CLK_EN
100n
+1.8V_MSMP1
NAND_READY/
HS_UART_CS/
10n
10n
10n
HOST_WAKEUP
10n
0.1u
MOVI_SD_EN
SDRAM_RAS/
SDRAM_CAS/
SUB_PM_SCL
SUB_PM_SDA
LCD_RESET/
10n
SDRAM_CLK
SDRAM_WE/
SDRAM_CS/
NANDF_ALE
NANDF_CLE
NANDF_WP/
1u
1608
C227
LCD_CS/
TA_DET/
10u
D1[25]
D1[24]
D1[11]
D1[10]
D1[31]
D1[30]
D1[29]
D1[28]
D1[27]
D1[26]
D1[15]
D1[14]
D1[13]
D1[12]
SLEEP/
C211
C213
C209
C210
C212
D1[1]
A[14]
A[13]
A[12]
A[10]
D1[9]
D1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[0]
A[11]
C215
C216
A[4]
A[7]
A[6]
A[2]
A[1]
A[0]
A[8]
A[5]
A[3]
OE2/
WE2/
A[9]
C214
+2.6V_MSMP2
10n
10n
10n
100n
AD11
AB14
AE12
AD13
AD14
TP200
W14
AE4
V15
T18
AE6
H21
F22
E24
H19
J19
R21
AA1
AD8
B10
B13
AE8
AD5
AD9
D24
F24
R24
A23
VDD_C11 AB2
AD7
R4
R5
N8
T2
T1
P5
P4
M8
P7
N5
P2
P1
K4
K7
K5
J1
J5
J2
J4
N4
J7
V4
M4
G1
K8
R7
N1
N2
N7
M7
M5
L5
L8
L7
L1
V1
E2
V5
Y1
G2
H5
G4
H4
B4
Y5
L2
L4
R8
V2
W4
U5
Y4
D2
H2
W2
VDD_P1_1 F2
K2
M2
R2
U2
XMEM2_CS_N[1]
XMEM2_CS_N[0]
BT_CLK/GPIO[25]
LCD2_EN/GPIO[37]
A1[14]
A1[13]
A1[12]
A1[11]
A1[10]
D1[15]
D1[14]
D1[13]
D1[12]
D1[11]
D1[10]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
GPIO[79]/SDRAM1_A[0]
GPIO[77]/XMEM1_CS_N[3]
SDRAM1_CS_N[0]/XMEM1_CS_N[2]
BT_SBST/GPIO[24]
BT_SBCK/GPIO[23]
BT_SBDT/GPIO[22]
GPIO[76]/XMEM1_CS_N[1]/SDRAM_CS_N[3]
XMEM1_CS_N[0]/SDRAM_CS_N[2]
NAND2_FLASH_READY/GPIO[33]
NAND2_ALE/LB2_N/A2[0]
A1[9]
A1[8]
A1[7]
A1[6]
A1[5]
A1[4]
A1[3]
A1[2]
A1[1]
D1[9]
D1[8]
D1[7]
OE1_N/SDRAM_CLK_EN[2]
LCD2_CS_N/GPIO[38]
BT_DATA/GPIO[20]
BT_TX_RX_N/GPIO[21]
A1[15]/SDRAM1_D[24]
SDRAM1_DQM[0]/LB1_N
SDRAM1_DQM[1]/UB1_N
SDRAM1_WE_N/WE1_N
VDD_C10
SDRAM1_CLK/ROM1_CLK
SDRAM1_CLK_EN
SDRAM1_RAS_N/ROM1_ADV_N
NAND2_CLE/UB2_N
SDRAM1_CAS_N/XMEM1_LWAIT_N
A1[16]/SDRAM1_S[25]
VDD_P1_2
VDD_P1_3
VDD_P1_4
VDD_P1_5
A1[18]/SDRAM_D[27]
A1[17]/SDRAM1_D[26]
NAND2_RE_N/OE2_N
VDD_C12
VDD_C13
HROM1_WAIT_N
WE2_N
A1[21]/SDRAM1_D[30]
A1[20]/SDRAM1_D[29]
A1[19]/SDRAM1_D[28]
VDD_C1
VDD_C2
VDD_C3
VDD_C4
VDD_C5
VDD_C6
VDD_C7
VDD_C8
VDD_C9
VDD_P2_1
VDD_P2_2
VDD_P2_3
A1[22]/SDRAM1_D[31]
VDD_Qfuse
C218
C220
C224
C222
G25 SBST
SSBI1
TP201
E9
AUX_SBDT/GPIO[4]
AUX_SBCK/GPIO[7]
VDD_A2 N22 <TEMP.DETECT>
0.1u
B17
100n
100n
VDD_A3
10n
AB24
RX0_I_P I_IP_CH0 AD21
VDD_A4
AA24 R208
RX0_I_M I_IM_CH0
AA16 22k
VDD_A5
W24
RX0_Q_P Q_IP_CH0 AD16 +2.85V_TCXO TEMP_ADC
VDD_A6
C221
C217
C219
C223
Y24
RX0_Q_M Q_IM_CH0
33n
C225
AD22
+/-1%
150k
R212
V24 VDD_A7
RX1_I_P I_IP_CH1 T24
U24 VDD_A8 R211
1
RX1_I_M I_IM_CH1 T25 1608
U22 VDD_A9
NCP18WD683E03RB
RX1_Q_P Q_IP_CH1 W25
V22 VDD_A10
RX1_Q_M Q_IM_CH1 Y25
VDD_A11
B11
TX_I_P I_OUT B20
B12
VDD_MDDI +1.8V_MSMP1
C202 TX_I_M I_OUT_N AA14
A12 A2[19]
10n
TX_Q_P Q_OUT V14
+2.6V_MSMA A11 A2[18]
TX_Q_M Q_OUT_N AB13
D12 A2[17] EBI2_AD
DAC_REF DAC_REF AD12
A2[16] A2[16]
U201
G11
PA_ON1 PA_ON1/GPIO[2] W13
E16 A2[15] A2[15]
PA_ON0 PA_ON0 AB12
E11 A2[14] A2[14]
TX_ON TX_ON
MSM6575-NSP
AA13
D17 A2[13]
PA_R1 PA_RANGE1 AE10
G17 A2[12]
PA_R0 PA_RANGE0 AD10
D20 A2[11]
TCXO_EN TCXO_EN/GPIO[94] AB11
H13 A2[10]
TRK_LO_MSM TRK_LO_ADJ AA12
E13 A2[9]
TX_AGC_ADJ TX_AGC_ADJ
N24
PA_POWER_CTL
A2[8]
A2[7]
W12
V13
<PCB Revison CHECK>
AA22
PA_DAC_EXT_REF AB10
Y22 A2[6]
BATT_ADC HKAIN[5] AA11
AA21
A2[5]
W21
V17
V18
ACC_ADC
N14
N15
P14
P15
U18
P11
P12
P13
V19
W19
AA5
HKAIN[4] AB9
V9
R210
U8
V8
W7
U19 A2[4]
VICHG HKAIN[3] V12
100k
AD23 A2[3] +2.85V_TCXO VER_ADC
TEMP_ADC HKAIN[2] AA9 +/-1%
W22 AB4 A2[2]
BATT_TEMP_ADC
C226
HKAIN[1] AA10
33n
R213
V21 AB22 A2[1]
75k
VER_ADC HKAIN[0] AA8
D18 A1 AC1 D2[15] D2[15]
MSM_TCXO TCXO
AB8
A9 A2 AC25 D2[14] D2[14]
USB_XTAL_48_IN W11
B9 A3 AD1 D2[13] D2[13]
USB_XTAL_48_OUT W10
C230 27p A15 A24 AD2 D2[12] D2[12]
SLEEP_XTAL_IN AD6
B15 A25 AD24 D2[11] D2[11]
1
SLEEP_XTAL_OUT AB7
R200
G13 B1 AD25 D2[10] D2[10]
1m X202 RESIN/ RESIN_N V11
G12 RESOUT_N B2 AE1 D2[9] D2[9]
W9
2
H9
H17
H18
N11
N12
M13
L14
L15
M11
M12
N13
J18
L12
L13
M14
M15
MDDIC_DATP T8
NL17SZ16XV5T2G B22 GPIO[75]/SDRAM1_DQM[3] SDRAM_DQM[3]
MDDIC_DATN U4
U200
A21 MDDIC_STBP
GPIO[74]/SDRAM_CLK_EN[3]
U7
D1[23] H 100K 56K 61,70
A22
GPIO[73] D1[22]
MDDIC_STBN AA2
M25 GPIO[72] D1[21] 1.0 100K 75K 71,83
USB_DATA USB_DAT_VP Y2
N21 GPIO[71] D1[20]
USB_SE0 USB_SE0_VM E1
M24
USB_OE_TP_N
GPIO[70] D1[19] 1.1 100K 100K 84,97
USB_OE/ GPIO[69]
P8
D1[18]
P18
DSP_PWRON USB_RX_DATA/GPIO[29] T4
J25
USB_SUSPEND/GPIO[17]
GPIO[68] D1[17] 1.2 100K 130K 98,AC
CAM_RESET/ GPIO[67]
T7
D1[16]
H10
HS_UART_RES/ RX_VCO_SEL/GPIO[43]
G9
GPIO[66]
JDET_INT
A5 UHF_VCO_1_SEL/GPIO[28] H14
CAM_PWR_DOWN
AA17
CAMIF_FOCUS[1]/GPIO[64] FMR_RBDS_INT
HPH_R HPH_R D10
W17 GPIO[53] BT_RESET/
HPH_L HPH_L G10
GPIO[52]
E14 MMC_DATA/GPIO[32] PMIC_IRQ/
A6
GPIO[51] AUDIO_SW1_EN
3D & FMR I2C BAT_ID_PULL_UP L18
G14
MMC_CLK/GPIO[31]
GPIO[50]
B6
KYPD[11]
MMC_CMD/GPIO[30]
H11
E19
GPIO[49] KYPD[9]
CAM_D[7] CAMIF_DATA9/GPIO[61] D5
G16
GPIO[45] CP_RESET/
CAM_D[6] CAMIF_DATA8/GPIO[60] D8
D21 GPIO[44] LIN_PWM_FREQ
CAM_D[5] CAMIF_DATA7/GPIO[59]
E8
H15 GPIO[42] PS_HOLD
CAM_D[4] CAMIF_DATA6/GPIO[58]
G8
K18 GPIO[40] HS_UART_LOWPWR
CAM_D[3] CAMIF_DATA5/GPIO[57]
D7
D19
CAMIF_FOCUS[0]/GPIO[39] EAR_JACK_SENSE
CAM_D[2] CAMIF_DATA4/GPIO[56] AA15
G21 GPIO[36]/XMEM2_CS_N[3] DSP_INT/
CAM_D[1] CAMIF_DATA3/GPIO[55] W15
GPIO[35]/XMEM2_CS_N[2] DSP_CS/
AUX_PCM_SYNC/SDAC_L_R_N/TSIF_ERROR/[GPIO102]
E18
CAM_D[0] CAMIF_DATA2/GPIO[54] AE11
DSP_RESET/
AUX_PCM_DOUT/SDAC_DOUT/TSIF_INTR/GPIO[103]
H25 GPIO[34]/A2[20]
3D_FMR_I2C_SCL CAMIF_DATA1/GPIO[81] E22
GPIO[19] PROXI_SCL
AUX_PCM_CLK/SDAC_CLK/TSIF_NULL/GPIO[80]
H24
3D_FMR_I2C_SDA CAMIF_DATA0/GPIO[83] M18
E6 GPIO[18]/RINGER AUDIO_SW2_EN
CAM_VSYNC CAMIF_VSYNC/GPIO[16]
D6
F21 GPIO[12]/GRFC[9] TOUCH_I2C_SCL
CAM_HSYNC CAMIF_HSYNC/GPIO[15]
E7
J22 GPIO[11]/GRFC[8] TOUCH_I2C_SDA
CAMIF_PCLK/GPIO[82]
CAM_PCLK GPIO[10]/GRFC[7]
P22
PROXI_SDA
AUX_PCM_DIN/SDAC_MCLK/GPIO[14]
J21 CAMCLK_PO/GP_MN/GPIO[13]
CAM_MCLK T21
C2 GPIO[9]/GRFC[6] USB20_SEL
UIM_CLK/GPIO[91] E10
F4 GPIO[6]/GRFC[3] DSP_USB_PWR_EN/
GPS_MODE UIM_RESET/GPIO[90] D9
G5
GPIO[5] UART_EN
LIN_MOT_EN UIM_PWR_EN/GPIO[89] B7
F5 GPIO[3] USB20_EN/
KEYSENSE4_N/GPIO[48]
KEYSENSE3_N/GPIO[47]
KEYSENSE2_N/GPIO[46]
KEYSENSE1_N/GPIO[63]
KEYSENSE0_N/GPIO[62]
K22
PROXI_OUT
SYNTH2/GPIO[65]
SYNTH1/GPIO[41]
SYNTH0/GPIO[92]
UIM2_RESET/TSIF_ENABLE/GPIO[86] L22
M21 CAMIF_ZOOM[1]/UART1_DP_RX/GPIO[96] MKEY_BL_EN
3D_INT UIM2_PWR_EN/TSIF_DATA/GPIO[85] K25
CAMIF_ZOOM[0]/UART1_DP_TX/GPIO[95]
EAR_MIC_KEY M19
UIM2_DATA/TSIF_SYNC/GPIO[84] CHG_MODE/
LINE_R_IN
LINE_R_IP
LINE_L_IN
LINE_L_IP
RESERVED1
RESERVED2
GND_RET1
HPH_VREF
GND_RET2
V7
MICBIAS
LINE_OP
LINE_ON
AUX_OUT
LCD_VSYNC_OUT MDP_VSYNC_PRIMARY/GPIO[105]
EAR1OP
EAR1ON
TRST_N
MIC1P
MIC1N
MIC2P
MIC2N
AUXIP
AUXIN
CCOMP
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
AA4
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
SD_DETECT/ MDP_VSYNC_SCONDA/GPIO[104]
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
RCLK
TMS
TDI
TDO
TCK
CON200
JTAG_STD_2COLUMN_10P
H1
R25
W1
A4
A10
A13
AB1
AE7
AE14
U1
M22
F25
R1
M1
K1
F1
AE5
AE9
AE13
P25
A8
A14
AC24
B23
D1
D25
AA20
E15
G15
D14
A16
D16
D15
AE21
U25
V25
W16
W18
K21
N18
AE22
U21
P21
D13
P19
R19
V16
L19
E4
C24
AA19
AE15
G22
G18
AB19
AE16
B16
A20
A17
AA25
AB15
AB25
D11
E17
N25
T19
AB16
AB17
H7
B5
AE18
AE17
AE20
AE19
AD18
AD17
AB20
AB21
AB18
AA18
1
TCK TCK
2
RTCK RTCK
3
1u
TDO
1u
C208
TDO
1u
4
22n
22n
22n
22n
TDI TDI
RCV-
RCV+
C201
C200
5
TMS TMS
22n
TCK
22n
6
TRST_N TRST
LCD_ID_CHECK
KYPD[7]
KYPD[5]
KYPD[3]
KYPD[1]
C206
HS_UART_INT
ONO/
C204
C203
C205
BT_WAKEUP
RTCK 7
+2.6V_MSMP2 VCC
TDO 8
C229
RESIN/ RESIN
C228
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_SYNC
TDI 9
BT_PCM_CLK
FMR_ANALOG_R
FMR_ANALOG_L
PS_HOLD PS_HOLD
TMS 10
GND
TRST_N
MIX_L
MIX_R
MIC+
EAR_MIC
CAM_SDA
CAM_SCL
C207
0.1u
R207
2.2k
MIC_BIAS
Circuit
CircuitDiagram
Diagram
CON701 +2.6V_MSMP2
AXT534124
1 34
2 33 R710 100
RCV+
R706
2.2k
R717
2.2k
KYPD[7]
3 32
RCV- +VPWR
4 31
SPK+
5 30 PROXI_SCL
SPK-
PWR_ON_SW 6 29
PROXI_SDA
R716 100 7 28
KYPD[11] PROXI_OUT
R709 100 27
KYPD[9]
8 PD_OUT
R711 100 9 26
KYPD[5] R712
PD_GAIN_CTRL1
100 10 25
KYPD[3] PD_GAIN_CTRL2
R713 100 11 24
KYPD[1] MKEY_BL
12 23
+2.8V_PROXI
13 22
LHP_EJ +3V_PD_SENSOR
14 21
RHP_EJ MIC+
15 20
EAR_JACK_SENSE MIC_BIAS
16 19
EAR_MIC
17 18
FMR_ANT
ESD9X5_0ST5G
ESD9X5_0ST5G
ULCE0505C015FR
DUMMY
35
36
37
38
ESD9X5_0ST5G
R700
C708
C729
100p
C702
C704
C722
C705
100p
C706
100p
C707
100p
C723
C703
100p
C727
C728
R718
10n
33p
33p
27p
27p
27p
1u
R707
R708
1
Test
Testpoint
point
R708
C704
C702
R707
Test
Testpoint
point
D103
D102
R708
C704
C702
R707
Checking
CheckingFlow
Flow
START
Yes
Yes
NO NO
Check the audio signal at Check the soldering at
Replace the receiver
RCV contact pad RCV+, RCV- contact pad
Yes
Yes
Re-solder receiver
Circuit
CircuitDiagram
Diagram
<AUDIO SUBSYSTEM>
C531
1u
+2.6V_MSMP2 R500 0
+VPWR
FMR_ANALOG_R
B1
B4
C502
C503
100n
LSVDD
VDD
1u
HPH_L
E1 A4
MIX_R INM+ LSOUT+ SPK+
16
15
14
13
NLAS3799BMNR2G
D1 A3
U503
MIX_L INM- LSOUT- SPK-
COMA
NOA
VCC
NCD
C500
220n
1 12 C2 D2
AMP_R NCA COMD INR SET
2 11 C501 R509
AUDIO_SW1_EN IN_A_B NOD
220n 24
3 10 C1 U500 E3
FMR_ANALOG_L NOB IN_C_D INL HPL LHP_EJ
4 9 LM49151
COMB NCC
+2.6V_MSMP2 C3
C510
100n
C512
100k
BYPASS
COMC
GND
NCB
NOC
R501
1.2k
R502
1.2k
A1
I2CVDD
B2
5
7
8
R503
AUDIO_I2C_SDA SDA
24
B3 E2
AMP_L AUDIO_I2C_SCL RHP_EJ
CPVSS
CPGND
SCL HPR
GND
C1N
C1P
ICVS0505500FR
ICVS0505500FR
A2
C4
D3
D4
E4
C504
2.2u
AUDIO_SW2_EN
HPH_R
C507
2.2u
C509
2.2u
10k
10k
R531
< TO FPCB CONNECTOR >
R532
R507
R505
CON701 +2.6V_MSMP2
AXT534124
1 34
2 33 R710 100
RCV+
R706
2.2k
R717
2.2k
KYPD[7]
3 32
RCV- +VPWR
4 31
SPK+
5 30 PROXI_SCL
SPK-
PWR_ON_SW 6 29
PROXI_SDA
R716 100 7 28
KYPD[11] PROXI_OUT
R709 100 27
KYPD[9]
8 PD_OUT
R711 100 9 26
KYPD[5] R712
PD_GAIN_CTRL1
100 10 25
KYPD[3] PD_GAIN_CTRL2
R713 100 11 24
KYPD[1] MKEY_BL
12 23
+2.8V_PROXI
13 22
LHP_EJ +3V_PD_SENSOR
14 21
RHP_EJ MIC+
15 20
EAR_JACK_SENSE MIC_BIAS
16 19
EAR_MIC
17 18
FMR_ANT
ESD9X5_0ST5G
ESD9X5_0ST5G
ULCE0505C015FR
DUMMY
35
36
37
38
ESD9X5_0ST5G
R700
C708
C729
100p
C702
C704
C722
C705
100p
C706
100p
C707
100p
C723
C703
100p
C727
C728
R718
10n
33p
33p
27p
27p
27p
1u
R707
R708
1
Circuit
CircuitDiagram
Diagram
<EARPHONE JACK>
NC1
C518
470p
10u
11
NO1 COM2 4
5 NC2 VCC2 9
8 VCC1 12
NO2 +2.6V_MSMP2
10 S1 GND2 3
EAR_JACK_SENSE
C530
7 6
EAR_MIC_KEY S2 GND1
1u
R522
15k
EAR_MIC
R530
200k
+2.6V_MSMP2
C506
C513
27p
100n
3/4POLE DETECT
U506
NCS2200SQ2T2G
1 5
EAR_MIC_KEY OUT VCC
+2.6V_MSMP2
2 VEE R527
680k
3 4
EAR_MIC IN+ IN-
C524
1u
R526
39k
Test
Testpoint
point
C728
C727
Test
Testpoint
point
D102
R110 L104
D100 L106
L105 L100
Checking
CheckingFlow
Flow
START
Yes
Headset detect problem
Yes
4 3
Headset
Headsetreceiving
receivingpath
pathproblem
problem
START
Voltage at R500,C502,C503 NO
Replace C502,C503
Is about 4.2V
Yes
NO NO
Check the audio signal at Check the Soldering of
Replace U503 or MSM
C500, C501 C500, C501
Yes
Yes
Re-solder C509, C510
Yes
Yes
Re-solder R503,R509
Yes
Yes
Re-solder L104,L105
Yes
Headset
Headsetdetect
detectproblem
problem
1 Headset detect
problem
Yes
Replace FPCB or Ear-jack
Yes
Check the soldering of CON701
Headset
Headsetsending
sendingpath
pathproblem
problem
Headset
sending
path problem 3
No
Check the voltage R530
whether its range is high?
Yes
No
Does it work? Replace headset
Yes
No
Change main
Does it work well?
board
Yes
Circuit
CircuitDiagram
Diagram
NAND_FLASH_CS/
+1.275V_MSMC
SDRAM_DQM[1]
SDRAM_DQM[0]
SDRAM_CLK_EN
100n
+1.8V_MSMP1
NAND_READY/
HS_UART_CS/
10n
10n
10n
HOST_WAKEUP
10n
0.1u
MOVI_SD_EN
SDRAM_RAS/
SDRAM_CAS/
SUB_PM_SCL
SUB_PM_SDA
LCD_RESET/
10n
SDRAM_CLK
SDRAM_WE/
SDRAM_CS/
NANDF_ALE
NANDF_CLE
NANDF_WP/
1u
1608
C227
LCD_CS/
TA_DET/
10u
D1[25]
D1[24]
D1[11]
D1[10]
D1[31]
D1[30]
D1[29]
D1[28]
D1[27]
D1[26]
D1[15]
D1[14]
D1[13]
D1[12]
SLEEP/
C211
C213
C209
C210
C212
D1[1]
A[14]
A[13]
A[12]
A[10]
D1[9]
D1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[0]
A[11]
C215
C216
A[4]
A[7]
A[6]
A[2]
A[1]
A[0]
A[8]
A[5]
A[3]
OE2/
WE2/
A[9]
C214
+2.6V_MSMP2
10n
10n
10n
100n
AD11
AB14
AE12
AD13
AD14
TP200
W14
AE4
V15
T18
AE6
H21
F22
E24
H19
J19
R21
AA1
AD8
B10
B13
AE8
AD5
AD9
D24
F24
R24
A23
VDD_C11 AB2
AD7
R4
R5
N8
T2
T1
P5
P4
M8
P7
N5
P2
P1
K4
K7
K5
J1
J5
J2
J4
N4
J7
V4
M4
G1
K8
R7
N1
N2
N7
M7
M5
L5
L8
L7
L1
V1
E2
V5
Y1
G2
H5
G4
H4
B4
Y5
L2
L4
R8
V2
W4
U5
Y4
D2
H2
W2
VDD_P1_1 F2
K2
M2
R2
U2
XMEM2_CS_N[1]
XMEM2_CS_N[0]
BT_CLK/GPIO[25]
LCD2_EN/GPIO[37]
A1[14]
A1[13]
A1[12]
A1[11]
A1[10]
D1[15]
D1[14]
D1[13]
D1[12]
D1[11]
D1[10]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
GPIO[79]/SDRAM1_A[0]
GPIO[77]/XMEM1_CS_N[3]
SDRAM1_CS_N[0]/XMEM1_CS_N[2]
GPIO[76]/XMEM1_CS_N[1]/SDRAM_CS_N[3]
XMEM1_CS_N[0]/SDRAM_CS_N[2]
NAND2_FLASH_READY/GPIO[33]
NAND2_ALE/LB2_N/A2[0]
BT_SBST/GPIO[24]
BT_SBCK/GPIO[23]
BT_SBDT/GPIO[22]
A1[9]
A1[8]
A1[7]
A1[6]
A1[5]
A1[4]
A1[3]
A1[2]
A1[1]
D1[9]
D1[8]
D1[7]
OE1_N/SDRAM_CLK_EN[2]
LCD2_CS_N/GPIO[38]
BT_DATA/GPIO[20]
BT_TX_RX_N/GPIO[21]
A1[15]/SDRAM1_D[24]
SDRAM1_DQM[0]/LB1_N
SDRAM1_DQM[1]/UB1_N
SDRAM1_WE_N/WE1_N
SDRAM1_CLK/ROM1_CLK
SDRAM1_CLK_EN
SDRAM1_RAS_N/ROM1_ADV_N
NAND2_CLE/UB2_N
VDD_C10
SDRAM1_CAS_N/XMEM1_LWAIT_N
A1[16]/SDRAM1_S[25]
VDD_P1_2
VDD_P1_3
VDD_P1_4
VDD_P1_5
A1[18]/SDRAM_D[27]
A1[17]/SDRAM1_D[26]
NAND2_RE_N/OE2_N
WE2_N
VDD_C12
VDD_C13
HROM1_WAIT_N
A1[21]/SDRAM1_D[30]
A1[20]/SDRAM1_D[29]
A1[19]/SDRAM1_D[28]
VDD_C1
VDD_C2
VDD_C3
VDD_C4
VDD_C5
VDD_C6
VDD_C7
VDD_C8
VDD_C9
A1[22]/SDRAM1_D[31]
VDD_P2_1
VDD_P2_2
VDD_P2_3
VDD_Qfuse
C218
C220
C224
C222
G25 SBST
SSBI1
TP201
E9
AUX_SBDT/GPIO[4]
AUX_SBCK/GPIO[7]
VDD_A2 N22 <TEMP.DETECT>
0.1u
B17
100n
100n
VDD_A3
10n
AB24
RX0_I_P I_IP_CH0 AD21
VDD_A4
AA24 R208
RX0_I_M I_IM_CH0
AA16 22k
VDD_A5
W24
RX0_Q_P Q_IP_CH0 AD16 +2.85V_TCXO TEMP_ADC
VDD_A6
C221
C217
C219
C223
Y24
RX0_Q_M Q_IM_CH0
33n
C225
AD22
+/-1%
150k
R212
V24 VDD_A7
RX1_I_P I_IP_CH1 T24
U24 VDD_A8 R211
1
RX1_I_M I_IM_CH1 T25 1608
U22 VDD_A9
NCP18WD683E03RB
RX1_Q_P Q_IP_CH1 W25
V22 VDD_A10
RX1_Q_M Q_IM_CH1 Y25
VDD_A11
B11
TX_I_P I_OUT B20
B12
VDD_MDDI +1.8V_MSMP1
C202 TX_I_M I_OUT_N AA14
A12 A2[19]
10n
TX_Q_P Q_OUT V14
+2.6V_MSMA A11 A2[18]
TX_Q_M Q_OUT_N AB13
D12 A2[17] EBI2_AD
DAC_REF DAC_REF AD12
A2[16] A2[16]
U201
G11
PA_ON1 PA_ON1/GPIO[2] W13
E16 A2[15] A2[15]
PA_ON0 PA_ON0 AB12
E11 A2[14] A2[14]
TX_ON TX_ON
MSM6575-NSP
AA13
D17 A2[13]
PA_R1 PA_RANGE1 AE10
G17 A2[12]
PA_R0 PA_RANGE0 AD10
D20 A2[11]
TCXO_EN TCXO_EN/GPIO[94] AB11
H13 A2[10]
TRK_LO_MSM TRK_LO_ADJ AA12
E13 A2[9]
TX_AGC_ADJ TX_AGC_ADJ
N24
PA_POWER_CTL
A2[8]
A2[7]
W12
V13
<PCB Revison CHECK>
AA22
PA_DAC_EXT_REF AB10
Y22 A2[6]
BATT_ADC HKAIN[5] AA11
AA21
A2[5]
W21
V17
V18
ACC_ADC
N14
N15
P14
P15
U18
P11
P12
P13
V19
W19
AA5
HKAIN[4] AB9
V9
R210
U8
V8
W7
U19 A2[4]
VICHG HKAIN[3] V12
100k
AD23 A2[3] +2.85V_TCXO VER_ADC
TEMP_ADC HKAIN[2] AA9 +/-1%
W22 AB4 A2[2]
BATT_TEMP_ADC
C226
HKAIN[1] AA10
33n
R213
V21 AB22 A2[1]
75k
VER_ADC HKAIN[0] AA8
D18 A1 AC1 D2[15] D2[15]
MSM_TCXO TCXO
AB8
A9 A2 AC25 D2[14] D2[14]
USB_XTAL_48_IN W11
B9 A3 AD1 D2[13] D2[13]
USB_XTAL_48_OUT W10
C230 27p A15 A24 AD2 D2[12] D2[12]
SLEEP_XTAL_IN AD6
B15 A25 AD24 D2[11] D2[11]
1
SLEEP_XTAL_OUT AB7
R200
G13 B1 AD25 D2[10] D2[10]
1m X202 RESIN/ RESIN_N V11
G12 RESOUT_N B2 AE1 D2[9] D2[9]
W9
2
WDOG_EN
B25 VSS_THERMAL AE3 D2[7]
AA7
D2[7]
1 2 AD4
CM315_12_5PF R22 MODE2
C1 AE23 D2[6] D2[6] A 100K 5.6K 07,15
X201 V10
ICRT20S48M0X514CR 3 T22 MODE1
C25 AE24 D2[5] D2[5]
AB6
Y21 MODE0
D4 AE25 D2[4]
AB5
D2[4] B 100K 12K 16,25
R204 10k AC2 D22 R11 D2[3] D2[3]
+1.8V_MSMP1 BOOT_MODE_2 W8
R205 10k AD20
BOOT_MODE_1
E5 R12 D2[2]
AD3
D2[2] C 100K 19.1K 26,34
R206 10k AD19 E20 R13 D2[1] D2[1]
+2.6V_MSMP2 BOOT_MODE_0 AA6
SLEEP_CLK(32.768KHZ) MDDI_D+ B19
MDDIH_DATP
E21 R14 D2[0] D2[0] D 100K 27K 35,43
GND 3 L25
4 Y
B18 G7 R15
GPIO[101]/SDCC_DAT[3] AUDIO_I2C_SDA
MDDI_D- MDDIH_DATN L24
A19
GPIO[100]/SDCC_DAT[2] AUDIO_I2C_SCL E 100K 36K 44,53
A 2 MDDI_STB+ MDDIH_STBP K19
A18 GPIO[99] FMR_RESET/
+2.6V_MSMP2 5 VCC NC 1 MDDI_STB- MDDIH_STBN T5
B21 GPIO[78]/A1[23]/SDRAM1_DQM[2] SDRAM_DQM[2] F 100K 47K 54,60
J8
G19
H8
H9
H17
H18
N11
N12
M13
L14
L15
M11
M12
N13
J18
L12
L13
M14
M15
MDDIC_DATP T8
NL17SZ16XV5T2G B22 GPIO[75]/SDRAM1_DQM[3] SDRAM_DQM[3]
MDDIC_DATN U4
U200
A21 MDDIC_STBP
GPIO[74]/SDRAM_CLK_EN[3]
U7
D1[23] H 100K 56K 61,70
A22
GPIO[73] D1[22]
MDDIC_STBN AA2
M25 GPIO[72] D1[21] 1.0 100K 75K 71,83
USB_DATA USB_DAT_VP Y2
N21 GPIO[71] D1[20]
USB_SE0 USB_SE0_VM E1
M24
USB_OE_TP_N
GPIO[70] D1[19] 1.1 100K 100K 84,97
USB_OE/ P18 GPIO[69]
P8
D1[18]
DSP_PWRON USB_RX_DATA/GPIO[29] T4
J25
USB_SUSPEND/GPIO[17]
GPIO[68] D1[17] 1.2 100K 130K 98,AC
CAM_RESET/ GPIO[67]
T7
D1[16]
H10
HS_UART_RES/ RX_VCO_SEL/GPIO[43]
G9
GPIO[66]
JDET_INT
A5 UHF_VCO_1_SEL/GPIO[28] H14
CAM_PWR_DOWN
AA17
CAMIF_FOCUS[1]/GPIO[64] FMR_RBDS_INT
HPH_R HPH_R D10
W17 GPIO[53] BT_RESET/
HPH_L HPH_L G10
GPIO[52]
E14 MMC_DATA/GPIO[32] PMIC_IRQ/
A6
GPIO[51] AUDIO_SW1_EN
3D & FMR I2C BAT_ID_PULL_UP L18
G14
MMC_CLK/GPIO[31]
GPIO[50]
B6
KYPD[11]
MMC_CMD/GPIO[30]
H11
E19
GPIO[49] KYPD[9]
CAM_D[7] CAMIF_DATA9/GPIO[61] D5
G16
GPIO[45] CP_RESET/
CAM_D[6] CAMIF_DATA8/GPIO[60] D8
D21 GPIO[44] LIN_PWM_FREQ
CAM_D[5] CAMIF_DATA7/GPIO[59]
E8
H15 GPIO[42] PS_HOLD
CAM_D[4] CAMIF_DATA6/GPIO[58]
G8
K18 GPIO[40] HS_UART_LOWPWR
CAM_D[3] CAMIF_DATA5/GPIO[57]
D7
D19
CAMIF_FOCUS[0]/GPIO[39] EAR_JACK_SENSE
CAM_D[2] CAMIF_DATA4/GPIO[56] AA15
G21 GPIO[36]/XMEM2_CS_N[3] DSP_INT/
CAM_D[1] CAMIF_DATA3/GPIO[55] W15
GPIO[35]/XMEM2_CS_N[2] DSP_CS/
AUX_PCM_SYNC/SDAC_L_R_N/TSIF_ERROR/[GPIO102]
E18
CAM_D[0] CAMIF_DATA2/GPIO[54] AE11
DSP_RESET/
AUX_PCM_DOUT/SDAC_DOUT/TSIF_INTR/GPIO[103]
H25 GPIO[34]/A2[20]
3D_FMR_I2C_SCL CAMIF_DATA1/GPIO[81] E22
GPIO[19] PROXI_SCL
AUX_PCM_CLK/SDAC_CLK/TSIF_NULL/GPIO[80]
H24
3D_FMR_I2C_SDA CAMIF_DATA0/GPIO[83] M18
E6 GPIO[18]/RINGER AUDIO_SW2_EN
CAM_VSYNC CAMIF_VSYNC/GPIO[16]
D6
F21 GPIO[12]/GRFC[9] TOUCH_I2C_SCL
CAM_HSYNC CAMIF_HSYNC/GPIO[15]
E7
J22 GPIO[11]/GRFC[8] TOUCH_I2C_SDA
CAMIF_PCLK/GPIO[82]
CAM_PCLK GPIO[10]/GRFC[7]
P22
PROXI_SDA
AUX_PCM_DIN/SDAC_MCLK/GPIO[14]
J21 CAMCLK_PO/GP_MN/GPIO[13]
CAM_MCLK T21
C2 GPIO[9]/GRFC[6] USB20_SEL
UIM_CLK/GPIO[91] E10
F4 GPIO[6]/GRFC[3] DSP_USB_PWR_EN/
GPS_MODE UIM_RESET/GPIO[90] D9
G5
GPIO[5] UART_EN
LIN_MOT_EN UIM_PWR_EN/GPIO[89] B7
F5 GPIO[3] USB20_EN/
KEYSENSE4_N/GPIO[48]
KEYSENSE3_N/GPIO[47]
KEYSENSE2_N/GPIO[46]
KEYSENSE1_N/GPIO[63]
KEYSENSE0_N/GPIO[62]
K22
PROXI_OUT
SYNTH2/GPIO[65]
SYNTH1/GPIO[41]
SYNTH0/GPIO[92]
UIM2_RESET/TSIF_ENABLE/GPIO[86] L22
M21 CAMIF_ZOOM[1]/UART1_DP_RX/GPIO[96] MKEY_BL_EN
3D_INT UIM2_PWR_EN/TSIF_DATA/GPIO[85] K25
CAMIF_ZOOM[0]/UART1_DP_TX/GPIO[95]
EAR_MIC_KEY M19
UIM2_DATA/TSIF_SYNC/GPIO[84] CHG_MODE/
LINE_R_IN
LINE_R_IP
LINE_L_IN
LINE_L_IP
RESERVED1
RESERVED2
GND_RET1
HPH_VREF
GND_RET2
V7
MICBIAS
AUX_OUT
LINE_OP
LINE_ON
LCD_VSYNC_OUT MDP_VSYNC_PRIMARY/GPIO[105]
EAR1OP
EAR1ON
TRST_N
MIC1P
MIC1N
MIC2P
MIC2N
AUXIP
AUXIN
CCOMP
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
AA4
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
SD_DETECT/ MDP_VSYNC_SCONDA/GPIO[104]
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
RCLK
TMS
TDI
TDO
TCK
CON200
JTAG_STD_2COLUMN_10P
H1
R25
W1
A4
A10
A13
AB1
AE7
AE14
U1
M22
F25
R1
M1
K1
F1
AE5
AE9
AE13
P25
A8
A14
AC24
B23
D1
D25
AA20
E15
G15
D14
A16
D16
D15
AE21
U25
V25
W16
W18
K21
N18
AE22
U21
P21
D13
P19
R19
V16
L19
E4
C24
AA19
AE15
B16
A20
A17
AA25
AB15
AB25
D11
E17
N25
T19
G22
G18
AB19
AE16
AB16
AB17
H7
B5
AE18
AE17
AE20
AE19
AD18
AD17
AB20
AB21
AB18
AA18
1
TCK TCK
2
RTCK RTCK
3
1u
TDO
1u
C208
TDO
1u
4
22n
22n
22n
22n
TDI TDI
RCV-
RCV+
C201
C200
5
TMS TMS
22n
TCK
22n
6
TRST_N TRST
LCD_ID_CHECK
KYPD[7]
KYPD[5]
KYPD[3]
KYPD[1]
C206
HS_UART_INT
ONO/
C204
C203
C205
BT_WAKEUP
RTCK 7
+2.6V_MSMP2 VCC
TDO 8
C229
RESIN/ RESIN
C228
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_SYNC
TDI 9
BT_PCM_CLK
FMR_ANALOG_R
FMR_ANALOG_L
PS_HOLD PS_HOLD
TMS 10
GND
TRST_N
MIX_L
MIX_R
MIC+
EAR_MIC
CAM_SDA
CAM_SCL
C207
0.1u
R207
2.2k
MIC_BIAS
Circuit
CircuitDiagram
Diagram
CON701 +2.6V_MSMP2
AXT534124
1 34
2 33 R710 100
RCV+
R706
2.2k
R717
2.2k
KYPD[7]
3 32
RCV- +VPWR
4 31
SPK+
5 30 PROXI_SCL
SPK-
PWR_ON_SW 6 29
PROXI_SDA
R716 100 7 28
KYPD[11] PROXI_OUT
R709 100 27
KYPD[9]
8 PD_OUT
R711 100 9 26
KYPD[5] R712
PD_GAIN_CTRL1
100 10 25
KYPD[3] PD_GAIN_CTRL2
R713 100 11 24
KYPD[1] MKEY_BL
12 23
+2.8V_PROXI
13 22
LHP_EJ +3V_PD_SENSOR
14 21
RHP_EJ MIC+
15 20
EAR_JACK_SENSE MIC_BIAS
16 19
EAR_MIC
17 18
FMR_ANT
ESD9X5_0ST5G
ESD9X5_0ST5G
ULCE0505C015FR
DUMMY
35
36
37
38
ESD9X5_0ST5G
R700
C708
C729
100p
C702
C704
C722
C705
100p
C706
100p
C707
100p
C723
C703
100p
C727
C728
R718
10n
33p
33p
27p
27p
27p
1u
R707
R708
1
Circuit
CircuitDiagram
Diagram
R532
R531
R509
R503
U500 U503
R125
R121
M100
Checking
CheckingFlow
Flow
START
Yes Yes
Re-solder R201
Yes
Yes
Test
TestPoint
Point
U302
C314
SLEEP_CLK(32.768KHZ)
Circuit
CircuitDiagram
Diagram
TP1
G22 SYNTH1/GPIO[41]
HS_UART_INT
G18 SYNTH0/GPIO[92]
LCD_ID_CHECK
U21
KYPD[7] KEYSENSE4_N/GPIO[48]
P21
KYPD[5] KEYSENSE3_N/GPIO[47]
D13
KYPD[3] KEYSENSE2_N/GPIO[46]
P19
KYPD[1] KEYSENSE1_N/GPIO[63]
R19
ONO/ KEYSENSE0_N/GPIO[62]
C203 22n AE18
MIC+ MIC1P
C204 22n AE17
MIC1N
C205 22n AE20
EAR_MIC MIC2P
C206 22n AE19
LG Electronics Inc.
MIC2N
AD18
AUXIP
AD17
AUXIN
AA19
TP2
HPH_VREF
AA18 AUX_OUT
TP3
AB20
LINE_R_IN
C200 1u AB21
FMR_ANALOG_R LINE_R_IP
AB18
LINE_L_IN
C201 1u AB19
FMR_ANALOG_L LINE_L_IP
AE16
RCV+ EAR1OP
AE15
RCV- EAR1ON
C207 C228 22n
0.1u AB16 LINE_OP
MIX_L
C200 C201
R207 C229 22n AB17 LINE_ON
Test
2.2k
MIX_R
V16
MIC_BIAS MICBIAS
AA20 CCOMP
C208
1u L19
AUX_PCM_CLK/SDAC_CLK/TSIF_NULL/GPIO[80]
U201
BT_PCM_CLK
TestPoint
E4
AUX_PCM_DOUT/SDAC_DOUT/TSIF_INTR/GPIO[103]
Point
BT_PCM_DOUT M22
AUX_PCM_DIN/SDAC_MCLK/GPIO[14]
Circuit Diagram
BT_PCM_DIN RF_OUT
H7
Circuit Diagram
AUX_PCM_SYNC/SDAC_L_R_N/TSIF_ERROR/[GPIO102]
BT_PCM_SYNC
K21 I2C_SDA/GPIO[26]
CAM_SDA
N18 I2C_SCL/GPIO[27]
CAM_SCL
E15
TRST_N
G15
TMS
D14
TDI
A16
TDO
D16
RCLK
D15
TCK
FMR_ANALOG_R FMR_ANALOG_L
B23 GND1
D1 GND2
D25 GND3
F25 GND4
H1
GND5
R25
GND6
W1
GND7
A4
GND8
TDI
TMS
TDO
TCK
RTCK
A10
GND9
TRST_N
A13
GND10
AB1
GND11
AE7
GND12
AE14
GND13
- 157/174-
AX8575
Checking
CheckingFlow
Flow
Start
Yes
Yes
Waveform
Waveform
CHAPTER
CHAPTER 5.
5. Safety
Safety
▣ IMPORTANT
Read This Information Before Using Your Hand-Held Portable Cellular Telephone
First introduction in 1984, the hand-held portable Cellular telephone is one of the most exciting and innovative
electronic products ever developed.
With it you can stay in contact with your office, your home, emergency service, and others. For the safe and efficient
operation of your phone, observe these guidelines.
Your Cellular phone is a radio transmitter and receiver. When it is ON, it receives and also sends out radio frequency
(RF) energy. The phone operates in the frequency range of 824 MHz to 894 MHz and employs commonly used
frequency modulation (FM) techniques. When you use your phone, the Cellular system handling your calls controls
the power level at which your phone transmits. The power level can range from 0.006 of a watt to .6 of a watt.
▣ Driving
Check the laws and regulations on the use of Cellular telephones in the areas where you drive. Always obey them.
Also, when using your phone while driving, please:
Give full attention to the driving. Use hands-free operation, if available, and pull off the road and park before making
or answering a call if driving conditions require.
▣ Electronic Devices
Most modem electronic equipment is shielded from RF energy. However, RF energy from Cellular telephones may
affect inadequately shielded electronic equipment.
RF energy may effect improperly installed or inadequately shielded electronic operating and entertainment system in
motor vehicles. Check with the manufacturer or its representative to determine if these systems are adequately
shielded from external RF energy. You should check with the manufacturer of any equipment that has been added to
your vehicle.
Consult the manufacturer of any personal medical devices (such as pacemakers, hearing aids, etc.) to determine if
they are adequately shielded from external RF energy.
Turn your phone OFF in health care facilities. When any regulations posted in the areas instruct you to do so.
Hospitals or health care facilities may be using equipment that could be sensitive to external RF energy.
▣ Aircraft
Turn your phone OFF before boarding any aircraft.
Use it on the ground only with crew permission. Do not use it in the air.
To prevent possible interference with aircraft systems, US Federal Aviation Administration (FAA) regulations
require you to have permission from a crew member to use your phone while the plane is on the ground. Using your
phone while the plane is in the air.
▣ Children
Do not allow children to play with your phone. It is not a toy. Children could hurt themselves or others (by poking
themselves or others in the eye with the antenna, for example). Children also could damage the phone, or make calls
that increase your telephone bills.
▣ Blasting Areas
To avoid interfering with blasting operations, turn you unit OFF when in a “blasting area” or in areas posted “Turn
off two-way radio”. Construction crews often use remote control RF devices to set off explosives.
Do not transport or store flammable gas, liquid, or explosives in the compartment of your vehicle which contains
your phone or accessories.
Vehicles using liquefied petroleum gas (such as propane or butane) must compl7y with the National Fire Protection
Standard (NFPA-58). For a copy of this standard, contact the National Fire Protection Association, One Battery
march Park, Quincy, MA 02269, Attn: Publication Sales Division.
Rule of Thumb: Using common sense at all times when handling, installing or using the phone. Any questions
should be directed to you nearest Service Center or authorized service technician or electrician.
CHAPTER
CHAPTER 6.
6. Glossary
Glossary
General Terms
Abbreviated Alert. An abbreviated alert is used to remind the mobile station user that previously selected alternative
routing features are still active.
Analog Access Channel. An analog control channel used by a mobile station to access a system to obtain service.
Analog Color-Code. An analog signal (see Supervisory Audio Tone) transmitted by a base station on an analog
voice channel and used to detect capture of a mobile station by an interfering base station or the capture of a base
station by an interfering mobile station.
Analog Control Channel. An analog channel used for the transmission of digital control information from a base
station to a mobile station or from a mobile station to a base station.
Analog Paging Channel. A forward analog control channel that is used to page mobile stations and send orders.
Analog Voice Channel. An analog channel on which a voice conversation occurs and on which brief digital
messages may be sent from a base station to a mobile station or from a mobile station to a base station.
Authentication. A procedure used by a base station to validate a mobile station’s identity.
Authentication Center (AC). An entity that manages the authentication information related to the mobile station.
Authentication Response (AUTHR). An 18-bit output of the authentication algorithm. It is used, for example, to
validate mobile station registrations, origination and terminations. A method of registration in which the mobile
station registers without an explicit command from the base station.
AWGN. Additive White Gaussian Noise.
Bad Frames. Frames classified as erasures (frame category 10) or9600bps frames, primary traffic only with bit
errors (frame category 9). See also Good Frames.
Base Station. A station in the Domestic Public Cellular Radio Telecommunications Service, other than a mobile
station, used for communicating with mobile stations. Depending upon the context, the term base station may refer to
a cell, a sector within a cell, an MSC, or other part of the Cellular system. See also MSC.
Base Station Authentication Response (AUTHBS). An 18-bit pattern generated by the authentication algorithm.
AUTHBS is used to confirm the validity of base station orders to update the Shared Secret Data.
Base Station Random Variable (RANDBS). A 32-bit random number generated by the mobile station for
authenticating base station orders to update the Shared Secret Data.
BCH Code. See Bose-Chaudhuri-Hocquenghem Code.
Busy-Idle Bits. The portion of the data stream transmitted by a base station on a forward analog control channel that
is used to indicate the current busy-idle status of the corresponding reverse analog control channel.
Call Disconnect. The process that releases the resources handling a particular call. The disconnect process beings
either when the mobile station user indicates the end of the call by generating an on-hook condition or other call
release mechanism, or when the base station initiates a release.
Call History Parameter (COUNT). A modulo-64 event counter maintained by the mobile station and
Authentication Center that us used for clone detection.
Candidate Set. The set of pilots that have been received with sufficient strength by the mobile station to be
successfully demodulated, but have not been placed in the Active Set by the base station. See also Active Set.
Neighbor Set, and Remaining Set.
. See Code Division Multiple Access
CDMA Channel. The set of channels transmitted between the base station within a given CDMA frequency
assignment. See also Forward CDMA Channel and Reverse CDMA Channel.
CDMA Channel Number. An 11-bit number corresponding to the center of the CDMA frequency assignment.
CDMA Frequency Assignment. A 1.23MHz segment of spectrum centered on one of the 30KHz channels of the
existing analog system.
Code Channel. A subchannel of a Forward CDMA Channels. A Forward CDMA Channel contains 64 code channels.
Code channel zero is assigned to the Pilot Channel. Code channels 1 through 7 may be assigned to the either Paging
Channels or the Traffic Channels. Code Channel 32 may be assigned to either a Sync Channel or a Traffic Channel.
The remaining code channels may be assigned to Traffic Channels.
Code Division Multiple Access (CDMA). A technique for spread-spectrum multiple-access digital communications
that creates channels through the use of unique code sequences.
Code Symbol. The output of an error-correcting encoder. Information bits are input to the encoder and code symbols
are output from the encoder. See Convolutional Code.
Continuous Transmission. A mode of operation in which Discontinuous Transmission is not permitted.
Control Mobile Attenuation Code (CMAC). A 3-bit field in the Control-Filler Message that specifies the
maximum authorized power level for a mobile transmitting on an analog reverse control channels.
Convolution Code. A type of error-correcting code. A code symbol can be considered as the convolution of the
input data sequence with the impulse response of a generator function.
CRC. See Cyclic Redundancy Code.
Cyclic Redundancy Code (CRC). A class of linear error detecting codes which generate parity check bits by
finding the remainder of a polynomial division.
Data Burst Randomizer. The function that determines which power control groups within a frame are transmitted
on the Reverse Traffic Channel when the data rate is lower than 9600 bps. The data burst randomizer determines, for
each mobile station, the pseudo random position of the transmitted power control groups in the frame while
guaranteeing that every modulation symbol is transmitted exactly once.
DBc. The ratio (in dB) of the sideband power of a signal, measured in a given bandwidth at a given frequency offset
from the center frequency of the same signal, to the total inband power of the signal. For CDMA, the total inband
power of the signal is measured in a 1.23MHz bandwidth around the center frequency of the CDMA signal.
DBm. A measure of power expressed in terms of its ration (in dB) to one milliwatt.
DBm/Hz. A measure of power spectral density. DBm/Hz is the power in one Hertz of bandwidth. Where power is
expressed in units of dBm.
DBW. A measure of power expressed in terns of its ration (in dB) to one Watt.
Dedicated Control Channel. An analog control channel used for the transmission of digital control information from
either a base station or a mobile station.
Deinterleaving. The process of unpermuting the symbols that were permuted by the interleaver..
Deinterleaving is performed on received symbols prior to decoding.
Digital Color Code (DCC). A digital signal transmitted by a base station on a forward analog control channel that is
used to detect capture of a base station by an interfering mobile station.
Dim-and-Burst. A frame in which primary traffic is multiplexed with either secondary traffic or signaling traffic.
Discontinuous Transmission (DTX). A mode of operation in which a mobile station transmitter autonomously
switches between two transmitter power levels while the mobile station is in the conversation state on an analog voice
channel.
Distance-Based Registration. An autonomous registration method in which the mobile station registers whenever it
enters a cell whose distance from the cell in which the mobile station last registered exceeds a given threshold.
DTMF. See Dual Tone Multifrequency.
Dual-Tone Multifrequency (DTMF). Signaling by the simultaneous transmission of two tones, one from a group of
low frequencies and another from a group of high frequencies. Each group of frequencies consists of four frequencies.
Eb. The energy of an information bit.
Ec/I0. The ratio in (dB) between the pilot energy accumulated over one PN chip period (Ec) to the power spectral
density in the received bandwidth (Io).
Effective Radiated Power (ERP). The transmitted power multiplied by the antenna gain referenced to a half wave
dipole.
Electronic Serial Number (ESN). A 32-bit number assigned by the mobile station manufacturer, uniquely
identifying the mobile station equipment.
Encoder Tail Bits. A fixed sequence of bits added to the end of a block of data to reset the convolutional encoder to
a known state.
ERP. See Effective Radiated Power.
ESN. See Electronic Serial Number.
Extended Protocol. An optional expansion of the signaling message between the base station and mobile station to
allow for the addition of new system features and operational capabilities.
Fade Timer. A timer kept by the mobile station as a measure of Forward Traffic Channel continuity. If the Fade
timer expires, the mobile station drops the call.
Flash. An indication sent on an analog voice channel or CDMA Traffic Channel indicating that the user Directed the
mobile station to invoke special processing.
Foreign NID Roamer. A mobile station operating in the same system (SID) but a different network (NID)Form the
one in which service was subscribed. See also Foreign SID Roamer and Roamer.
Foreign SID Roamer. A mobile station operating in a system (SID) other than the one from which service was
subscribed. See also Foreign NID Roamer and Roamer.
Forward Analog Control Channel (FOCC). An analog voice channel used from a base station to a mobile station.
Forward Analog Voice Channel (FVC). An analog voice channel used from a base station to a mobile station.
Forward CDMA Channel. A CDMA Channel form a base station to mobile stations. The Forward CDMA Channel
contains one or more code channels that are transmitted on a CDMA frequency assignment using a Particular pilot
PN offset. The code channels are associated with the Pilot Channel, Sync Channel, Paging Channels, and Traffic
Channels. The Forward CDMA Channel always carries a Pilot Channel and may carry up to one Sync Channel, up to
seven Paging Channels, and up to 63 Traffic Channels, as long as the total number of channels, including the Pilot
Channel, is no greater than 64.
Forward Traffic Channel. A code channel used to transport user and signaling traffic from the base station to the
mobile station.
A basic timing interval in the system. For the Access Channel, Paging Channel, and Traffic Channel, a frame is 20
ms long. For the Sync Channel, a frame is 26.666…ms long.
Frame Category. A classification of a received Traffic Channel frame based upon transmission data rate, the Frame
contents (primary traffic, secondary traffic, or signaling traffic), and whether there are detected error in the frame.
Frame Offset. A time skewing of Traffic Channel frames from System Time in integer multiples of 1.25 ms. The
maximum frame offset is 18..75 ms..
Frame Quality Indicator. The CRC check applied to 9600 bps and 4800 bps Traffic Channel frames.
Global Positioning System (GPS). A US government satellite system that provides location and time Information to
users. See Navstar GPS Space segment / Navigation User interfaces ICD-GPS-200 for Specifications.
Half Frame. A 10 ms interval on the paging Channel. Two half frames comprise a frame, the first half frame begins
at the same time as the frame.
Handoff. The of transferring communication with a station mobile station from one base station to another.
Hard Handoff. A handoff characterized by a temporary disconnection of the Traffic Channel. Hard handoffs Occur
when the mobile station is transferred between disjoint Active Sets, the CDMA frequency assignment changes, the
frame offset changes, or the mobile station is directed from a CDMA Traffic Channel to an analog voice channel, See
also Soft Handoff.
Hash Function. A function used by the mobile station to select one out of N available resource. The hash function
distributes the available resources uniformly among a random sample of mobile stations.
HLR. See Home Location Register.
Home Location Register (HLR). The location register to which a MIN is assigned for record purposes such as
subscriber information.
Home System. The Cellular system in which the mobile station subscribes for service.
Idle Handoff. The act of transferring reception of the Paging Channel from one bass station to another, when the
mobile station is in the Mobile Station Idle State.
Implicit Registration. A registration achieved by a successful transmission of an origination or page response on the
Access Channel.
Interleaving. The process of permuting a sequence of symbols.
kHz. Kilohertz (103 Hertz).
ksps. Kilo-symbols per second (103 symbols per second).
Layer 1. See Physical Layer.
Layer 2. Layer 2 provides for the correct transmission and reception of signaling messages, including partial
duplicate detection. See also Layering and Layer 3.
Layer 3. Layer 3 provides the control of the Cellular telephone systems. Signaling messages originate and terminate
at layer 3. See also Layering and Layer 2.
Local Control. An optional mobile station feature used to perform manufacturer-specific functions.
A PN sequence with period 242-1 that is used for scrambling on the Forward CDMA Channel and spreading on the
Reverse CDMA Channel. The long code uniquely identifies a mobile station on both the Reverse Traffic Channel and
the Forward Traffic Channel. The long code provides limited privacy. The long code also separates multiple Access
Channels on the same CDMA channel. See also Public Long Code and Private Long Code.
Long Code Mask. A 42-bit binary number that creates the unique identity of the long code. See also Public Long
Code, Private Long Code, Public Long Code Mask, and Private Long Code Mask.
LSB. Least significant bit.
Maximal Length Sequence (m-Sequence). A binary sequence of period 2n-1, n a positive integer, with no internal
periodicities. A maximal length sequence can be generated by a tapped n-bit shift register with linear feedback.
Mcps. Megachips per second (106 chips per second).
Mean Input Power. The total received calorimetric power measured in a specified bandwidth at the antenna
connector, including all internal and external signal and noise sources.
Mean Output Power. The total transmitted calorimetric power measured in a specified bandwidth at the antenna
connector when the transmitter is active.
Message. A data structure that conveys control information or application information. A message consists of a
length field (MSG_LENGTH), a message body (the part conveying the information), and a CRC.
Message Body. The part of the message contained between the length field (MSG_LENGTH) and the CRC field.
Message Capsule. A sequence of bits comprising a single message and padding. The padding always follows the
message and may be of zero length.
Message CRC. The CRC associated with a message. See also Cyclic Redundancy Check.
Message Field. A basic named element in a message. A message field may consist of zero or more bits.
Message Record. An entry in a message consisting of one or more field that repeats in the message.
MHz. Megahertz.(106 Hertz)
MIN. See Mobile Station Identification Number.
Mobile Protocol Capability Indicator (MPCI). A 2-bit field used to indicate 속 mobile station’s capabilities.
Mobile Station. A station in the Domestic Public Cellular Radio Telecommunications Service intended to be used
while in motion or during halts at unspecified points. Mobile station include portable units (e.g., handheld personal
units) and units installed in vehicles.
Mobile Station Class. Mobile station classes define mobile station characteristics such as slotted operation and
transmission power.
Mobile Station Identification Number (MIN). The 34-bit number that is a digital representation of the 10-digit
directory telephone number assigned to a mobile station.
Mobile Station Originated Call. A call originating from a mobile station.
Mobile Station Terminated Call. A call received by a mobile station (not to be confused with a disconnect or call
release).
Mobile Switching Center (MSC). A configuration of equipment that provides Cellular radiotelephone service. Also
called the Mobile Telephone Switching Office (MTSO)
Modulation Symbol. The output of the data modulator before spreading. On the Reverse Traffic Channel, 64-ary
orthogonal modulation is used and six code symbol (when the data rate is 9600bps) or each repeated code symbol
(when the data rate is less than 9600bps) is one modulation symbol.
Ms. Millisecond.
MSB. Most significant bit.
MSC. See Mobile Switching Center.
Multiplex Option. The ability of the multiplex sublayer and lower layer to be tailored to provide special capabilities.
A multiplex option defines such characteristics as the frame format and the rate decision rules. See also Multiplex
Sublayer.
Multiplex Sublayer. One of the conceptual layers of the system that multiplexes and demultiplexes primary traffic,
secondary traffic, and signaling traffic.
NAM. See Number Assignment Module.
Narrow Analog. A type of voice channel that uses 10kHz channel spacing and subaudible signaling.
Neighbor Set. The set of pilots associated with the CDMA Channel that are probable candidates for handoff.
Normally, the Neighbor Set consists of the pilots associated with CDMA Channel that cover geographical areas near
the mobile station. See also Active Set, Candidate Set, and Remaining Set.
A network is a subset of a Cellular system, such as an area-wide Cellular network, a private group of base stations, or
a group of base stations set up to handle a special requirement. A network can be as small or as large as needed, as
long as it is fully contained within a system. See also System.
Network Identification (NID). A number that uniquely identifies a network within a Cellular system. See also
System Identification.
NID. See Network Identification.
Non-Autonomous Registration. A registration method in which the base station initiates registration. See also
Autonomous Registration.
Non-Slotted Mode. An operation mode of the mobile station in which the mobile station continuously monitors the
Paging Channel when in the Mobile Station Idle State.
Ns. Nanosecond.
NULL. Not having any value.
Null Traffic Channel Data. One or more frames of 16 ‘1’s followed by eight ‘0’s sent at the 1200bps rate. Null
Traffic Channel data is sent when no service option is active and no signaling message is being sent. Null Traffic
Channel data serves to maintain the connectivity between the mobile station and the base station.
Number Assignment Module (NAM). A set of MIN-related parameters stored in the mobile station.
Numeric Information. Numeric information consists of parameters that appear as numeric fields in message
exchanged by the base station and the mobile station and information used to describe the operation of the mobile
station.
OLC. See Overload Class (CDMA) or Overload Control (analog).
Optional Field. A field defined within a message structure that is optionally to the message recipient.
Order. A type of message that contains control codes for either the mobile station or the base station.
Ordered Registration. A registration method in which the base station orders the mobile station to send registration
related parameters.
Overhead Message. A message sent by the base station on the Paging Channel to communicate base-station-specific
and system-wide information to mobile station.
Overload Class. The means used to control system access by mobile stations, typically in emergency or other
overload conditions. Mobile station are assigned one (or more) of sixteen overload classed, Access to the CDMA
system can then be controlled on a per class basis by persistence values transmitted by the base station.
Overload Control (OLC). A means reverse analog control channel accesses by mobile stations. Mobile station are
assigned one(or more) of sixteen control levels. Access is selectively restricted by a base station setting one or more
OLC bits in the Overload Control Global Action Message.
Packet. The unit of information exchanged between the service option applications of the base station and the mobile
station.
Padding. A sequence of bits used to fill from the end of a message to the end of a message capsule, typically to the
end of the frame or half frame. All bits in the padding are '0'.
Paging. The act of seeking a mobile station when a call has been placed to that mobile station.
Paging Channel (Analog). See Analog Paging Channel.
Paging Channel (CDMA). A code channel in a Forward CDMA Channel used for transmission of control
information and pages from a base station to a mobile station.
Paging Channel Slot. An 80ms interval on the Paging Channel. Mobile station operating in the slotted mode are
assigned specific slots in which day monitor messages from the base station.
Parameter-Change Registration. A registration method in which the mobile station registers when certain of its
stored parameters change.
Parity Check Bits. Bits added to a sequence of information bits to provide error detection, correction, or both.
Persistence. A probability measure used by the mobile station to determine if it should transmit in a given Access
Channel Slot.
Physical Layer. The part of the communication protocol between the mobile station and the base station that is
responsible for the transmission and reception of data. The physical layer in the transmitting station is presented a
frame by the multiplex sublayer and transforms it into an over-the-air waveform. The physical layer in the receiving
station transforms the waveform back into a frame and presents it to the multiplex sublayer above it.
Pilot Channel. An unmodulated, direct-sequence spread spectrum signal transmitted continuously by each CDMA
base station. The Pilot Channel allows a mobile station to acquire the timing of the Forward CDMA Channel,
provides a phase reference for coherent demodulation, and provides a means for signal strength comparisons between
base station for determining when to handoff.
Pilot PN Sequence. A pair of modified maximal length PN sequences with period 215 used to spread the Forward
CDMA Channel and the Reserve CDMA Channel. Different base station are identified by different pilot PN sequence
offsets.
Pilot PN Sequence Offset Index. The PN offset in units of 64 PN chips of a pilot, relative to the zero offset pilot PN
sequence.
Soft Handoff. A handoff occurring while the mobile station is in the Mobile Station Control on the Traffic Channel
State. This handoff is characterized by commencing communications with a new base station on the same CDMA
frequency assignment before terminating communications with the old base station. See also Hard Handoff.
SOM. Start-of-Message Bit.
SPS. Symbols per second.
- An identification of certain characteristics of a mobile station. Classes are defined in Table 2.3.3-1.
Status Information. The following status information is used to describe mobile station operation when using the
analog system.
Serving-System Status. Indicates whether a mobile station is turned to channels associated with System A or
System B.
First Registration ID Status. A status variable used by the mobile station in association with its processing of
received Registration ID messages.
First Location Area ID Status. A status variable used by the mobile station in association with its processing of
received Location Area ID messages.
Location Registration ID Status. A status variable used by the mobile station in association with its processing of
power-up registration and location-based registration.
First Idle ID Status. A status variable used by the mobile station in association with its processing of the Idle Task.
Local Control Status. Indicates whether a mobile station must respond to local control messages.
Roam Status. Indicates whether a mobile station is in its home system.
Termination Status. Indicates whether a mobile station must terminate the call when it is on an analog voice
channel.
Supervisory Audio Tone (SAT). One of three tones in the 6 kHz region that is transmitted on the forward analog
voice channel by a base station and transponder on the reverse analog voice channel by as mobile station.
Supplementary Digital Color Code (SDCC1, SDCC2). Additional bits assigned to increase the number of color
codes from four to sixty four, transmitted on the forward analog control channel.
Symbol. See Code Symbol and Modulation Symbol.
Sync Channel. Code channel 32 in the Forward CDMA Channel which transports the synchronization message to the
mobile station.
Sync Channel Superframe. An 80ms interval consisting of three Sync Channel frames (each 26.666…ms in length).
System. A system is a Cellular telephone service that covers a geographic area such as a city. Metropolitan region,
country, or group of countries. See also Network.
System Time. The time reference used by the system. System Time is synchronous to UTC time (except for leap
seconds) and used the same time origin as GPS time. Offset by the propagation delay from the base station to the
mobile station. See also Universal coordinated Time.
Timer-Based Registration. A registration method in which the mobile station registers whenever a counter reaches
a predetermined value. The counter is incremented an average of once per 80 ms period.
Time Reference. A reference established by the mobile station that is synchronous with the earliest arriving
multipath component used for demodulation.
Appendix
Appendix
1. Block and Circuit Diagram
2. BGA Pin Map
3. Component Layout
4. Assembly and Disassembly diagram
5. Part List
LG Electronics Inc.
LGE Internal Use Only
BCM2070
BT
AX8575 Block Diagram
2.4~2.48G
[ U302 ]
ANT
[F300
BLUETOOTH
Module 32.768kHz
26M
Main ANT Dual PAM Daul
Dual-band Ant. (DCN, PCS) Tx RF BPF
Quad
LPF
Up- Baseband GPIOs w/TLMN
convert
Processor Memory support
Quad
LPF
Up-
[U109] [F102] convert
Interface with
Mobile Connectivity
Loop TX LO Other functions
S/W
coupler
Filter Circuit [U111]
Detector TX _ Gain
Control
RTR Air Interfaces Camera
VCTCXO [U103]
Quad- Loop Filter Buffer
6500 [U201]
Audio
ple xe r Pre- LNA
[U105] PRX LO
SBI Housekeeping MSM
Circuit
LPF ADC
ADC
6575
Quad
D’convert LPF ADC
[F101] General
N.C
GPIOs w/TLMN
LPF ADC Housekeeping
Quad
D’convert
LG Electronics Inc.
N.C LPF ADC Input Power
SRX LO PM Interfaces
[U112] Management
Circuit
[F103]
LPF LPF ADC
GPS Quad Output Voltage
GPS LO Regulation
BPF Circuit
D’convert LPF LPF ADC
GPS LNA
Module Loop Filter
AX8575
AX8575 LGE Internal Use Only
LG Electronics Inc.
F100
SIP4282 U110
TC7SH32FE
6 OUT2 VIN1 1
1 Vcc 5
PA_R0 +2.6V_MSMP2
5 OUT1 2 2
VIN2 +VPWR PA_R1
3 4
4 3 GND PA_R_OR
1608
ON/OFF GND
C143
2.2u
U_FL-R-SMT_10
PA_R1 MSM
2.2u
1608
C129
+2.1V_TX
+2.6V_MSMP2
U100
3
+VDD_TX_A
1u
C178
1u
C169
10n
C171
100p
C173
1u
C170
2
+2.1V_TX
C140
DNI
RF
1
C187
C146 +2.1V_TX
68p
100p +2.1V_RX1
HDET_CPL
+VDD_RX1_D
C147
C107 U109 100p PCS Tx RF SAW C157
1u +2.1V_RX1
DNI
C116
C123 ACPM-7353 C149 +2.1V_RX1
U107 100p 1n 56p L122
1005 LDC15874M19Q-360 14 1 F102 DNI
RFOUT_CELL RFIN_CELL C160
L127
1 4
1005
C108 OUT TER
DNI
12 3 6 4 +2.1V_RX0
L107
DNI C121
DNI
GND3 VBP PA_R0 P_IN/OUT P_OUT/IN
1005
2
IN COU
3 11
VCC2 VCC1
4 +2.1V_RX0
9 1
C166
10 5 D_IN/IOUT D_/OUT/IN +VDD_RX0_B
33p
GND2 VEN_CELL PA_ON0
+2.1V_RX0
GND3
GND4
GND5
GND1
GND2
GND6
C117 9 6
3.3n C122
2p
GND1 VEN_PCS PA_ON1
8 7 +VDD_RX0_D
59
68
38
44
29
30
47
48
64
54
61
35
27
37
11
12
14
RFOUT_PCS RFIN_PCS
4
5
C176
1u
C155
10n
C158
100p
C159
1u
C154
1u
G_SLUG
10
7
C115
8
5
2
3
1005
R109 15
DNI
VDDRX2
VDDRX4
VDDRX5
VDDRX10
VDDRX12
VDDTX7
VDDRX3
VDDRX6
VDDRX7
VDDRX8
VDDRX9
VDDTX2
VDDTX3
VDDTX4
VDDTX5
VDDTX6
VDDRX1
VDDRX11
100n
C118
VDDTX1
C142
100p
C145
100p
49.9
C148
1
+/-1%
A
56p
KMS-518
U108
LDC151G8620Q-359
U102
3
L124 22 6
1 4 DNI
VDDM DAC_REF DAC_REF
4
OUT TER
C
7
2
1005
L101 2 3 3 TX_QP TX_Q_P
100n IN COU TX_OUT_LB_A 8
1 TX_QM TX_Q_M
C164
TX_OUT_LB_B
DCN TX-BYPASS-OUT
12p
9
C100
0.5p
TX_IP TX_I_P
10
67 TX_IM TX_I_M
TX_OUT_HB_A
U105
ACFM-7107 65 13
TX_OUT_HB_B VCO_TUNE_TX
USPCS TX-BYPASS-OUT
R117
16
C185
220p
C186
3.3n
1 L116
39
63 TX_ON TX_ON
L100
4.7n
R114
R118
5 3 60 2
150
150
R132
5.1k
PA_R0
1005
ANT CELL_TX VCO_TUNE_PRX PA_R0
DNI
L117
5.6n
C139
4 66
PCS_TX L109
C128 53 RX_IN_HB_0
PA_R1 PA_R_OR
15n 100p
52
36
RX_IN_LB_0
U111 CHIPX16
17 C175
ANT103 ANT104 RX_IN_GPS 100p
33n
RTR6500 62
L108
TCXO
L111
TCXO
+2.85V_GPS
DNI
50
LNA_OUT_LB_0 19
1 1 49 SSBI0 SSBI0
LNA_OUT_HB_0 20
L110 C152 PULL_UP
C126 100p
12n 10p 46 21
MIX_INM_HB_0 PULL_DOWN
45 23
MIX_INP_HB_0 SSBI1 SSBI1
24
L112
DNC1
18n
43
R131
MIX_INM_LB_0
100n
L106
ICVL0505101V150FR 25
47k
L105
DNC2
DNI
R133 42
10
MIX_INP_LB_0
2
5
3 4
+2.6V_MSMP2
C150
0.5p
C114 R112 C131 26
GND6
GND2
GND1
40
GND3
100p 12p DNI C136 RX_IN_HB_1 JDET_INT JDET_INT
A 3.9n 100p D_OUT
C C167 9
1 2 +2.1V_RX0 C153 39
RX_IN_LB_1 RX for MRD
100p 100p
100p
C103
5.6n
28
6.8n
L121
C124
100p
C134
2.2p
L125
KMS-518
L102
B9416 VCO_TUNE_SRX
DNI
IN OUT 7 RX1_QM
41
DNC
RX1_Q_M
P_IN 34
G3 G2 G1 4 RX1_QP RX1_Q_P
RF_IN
P_OUT
C162
C165
6
51
82n
18n
L104
100n
5 3 2 2 5 L115 RBIAS_2
S_D VDD C141 R113 C137
10n B9318 15 55
C151
1.5p
3 4
100p 510 100p
F101 RBIAS_1 RX0_IP RX0_I_P
GND FIL_OUT +2.1V_RX0 56
RX0_IM RX0_I_M
C161
4.7n
C163
1.2n
R108
R119
R120
1.5k
R121
5.1k
R122
L119 57
L126
100n
560
12k
C125
100p
C135
U112
L114 3.9n RX0_QP RX0_Q_P
10
ALM-2412
5p
39n 58
RX0_QM RX0_Q_M
GPS_MODE G_SLUG
C180
0.1u
R130
0.1u
C111
6.8p
C113
47k
69
C109
DSA321SCA-19_20M +2.1V_TX
47p
4 3
C119
C127
C133
C138
R101
1u
1u
1u
1608
10n
C156
100n
C179
C182
C184
100p
10u
1u
R111
[PIN 14] 10 [PIN 12]
+2.1V_TX +VDD_TX_A
C120
C130
C132
L123
33p
TRK_LO
1u
1u
C172
C174
100p
D-F/F
10n
1608
C177
C181
C183
100p
10u
U104 +2.85V_TCXO 1u
NC7SZ74L8X
DNI
8
R105
VCC
7 1
MSM_TCXO CK PR
6 2 R107
TRK_LO_MSM D CLR
2k
5 3
Q Q TRK_LO_ADJ
GND
C101
C110
100n
C112
33p
33n
4
NAND_FLASH_CS/
+1.275V_MSMC
SDRAM_DQM[1]
SDRAM_DQM[0]
SDRAM_CLK_EN
100n
+1.8V_MSMP1
NAND_READY/
HS_UART_CS/
10n
10n
10n
HOST_WAKEUP
10n
0.1u
MOVI_SD_EN
SDRAM_RAS/
SDRAM_CAS/
SUB_PM_SCL
SUB_PM_SDA
LCD_RESET/
10n
SDRAM_CLK
SDRAM_WE/
SDRAM_CS/
NANDF_ALE
NANDF_CLE
NANDF_WP/
1u
1608
C227
LCD_CS/
TA_DET/
10u
D1[25]
D1[24]
D1[11]
D1[10]
D1[31]
D1[30]
D1[29]
D1[28]
D1[27]
D1[26]
D1[15]
D1[14]
D1[13]
D1[12]
SLEEP/
C211
C213
C209
C210
C212
D1[1]
A[14]
A[13]
A[12]
A[10]
D1[9]
D1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[0]
A[11]
C215
C216
A[4]
A[7]
A[6]
A[2]
A[1]
A[0]
A[8]
A[5]
A[3]
OE2/
WE2/
A[9]
C214
+2.6V_MSMP2
10n
10n
10n
100n
AD11
AB14
AE12
AD13
AD14
TP200
W14
AE4
V15
T18
AE6
H21
F22
E24
H19
J19
R21
AA1
AD8
B10
B13
AE8
AD5
AD9
VDD_C11 AB2
AD7
D24
F24
R24
A23
R4
R5
N8
T2
T1
P5
P4
M8
P7
N5
P2
P1
K4
K7
K5
J1
J5
J2
J4
N4
J7
V4
M4
G1
K8
R7
N1
N2
N7
M7
M5
L5
L8
L7
L1
V1
V5
E2
Y1
G2
H5
G4
H4
B4
Y5
L2
L4
R8
V2
W4
U5
Y4
D2
H2
W2
F2
K2
M2
R2
U2
XMEM2_CS_N[1]
XMEM2_CS_N[0]
BT_CLK/GPIO[25]
LCD2_EN/GPIO[37]
A1[14]
A1[13]
A1[12]
A1[11]
A1[10]
D1[15]
D1[14]
D1[13]
D1[12]
D1[11]
D1[10]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
GPIO[77]/XMEM1_CS_N[3]
GPIO[79]/SDRAM1_A[0]
SDRAM1_CS_N[0]/XMEM1_CS_N[2]
XMEM1_CS_N[0]/SDRAM_CS_N[2]
NAND2_FLASH_READY/GPIO[33]
NAND2_ALE/LB2_N/A2[0]
BT_SBST/GPIO[24]
BT_SBCK/GPIO[23]
BT_SBDT/GPIO[22]
GPIO[76]/XMEM1_CS_N[1]/SDRAM_CS_N[3]
OE1_N/SDRAM_CLK_EN[2]
A1[9]
A1[8]
A1[7]
A1[6]
A1[5]
A1[4]
A1[3]
A1[2]
A1[1]
D1[9]
D1[8]
D1[7]
LCD2_CS_N/GPIO[38]
BT_DATA/GPIO[20]
BT_TX_RX_N/GPIO[21]
A1[15]/SDRAM1_D[24]
SDRAM1_CLK_EN
VDD_C10
SDRAM1_DQM[0]/LB1_N
SDRAM1_DQM[1]/UB1_N
SDRAM1_WE_N/WE1_N
SDRAM1_CLK/ROM1_CLK
NAND2_CLE/UB2_N
SDRAM1_RAS_N/ROM1_ADV_N
SDRAM1_CAS_N/XMEM1_LWAIT_N
A1[16]/SDRAM1_S[25]
A1[17]/SDRAM1_D[26]
VDD_P1_1
VDD_P1_2
VDD_P1_3
VDD_P1_4
VDD_P1_5
A1[18]/SDRAM_D[27]
NAND2_RE_N/OE2_N
VDD_C12
VDD_C13
HROM1_WAIT_N
WE2_N
A1[21]/SDRAM1_D[30]
A1[20]/SDRAM1_D[29]
A1[19]/SDRAM1_D[28]
VDD_C1
VDD_C2
VDD_C3
VDD_C4
VDD_C5
VDD_C6
VDD_C7
VDD_C8
VDD_C9
VDD_P2_1
VDD_P2_2
VDD_P2_3
A1[22]/SDRAM1_D[31]
VDD_Qfuse
C218
C220
C224
C222
G25 SBST
SSBI1
TP201
H22 SBDT VDD_P3_1 B8
SSBI0
L21 SBCK VDD_P3_2 B14
H16 SBST1/GPIO[93] VDD_P3_3 J24
E25 SBDT1/GPIO[1] VDD_P3_4 P24
G24 B3
DSP_SD_DETECT WDOG_STB/SBCK1/GPIO[0] VDD_P3_5
H12
BAT_ID_CHK AUX_SBST/GPIO[8]
E12
VDD_A1 +2.6V_MSMA
PMIC_SDA
PMIC_SCL
A7
E9
AUX_SBDT/GPIO[4]
AUX_SBCK/GPIO[7]
VDD_A2 N22 <TEMP.DETECT>
0.1u
B17
100n
100n
VDD_A3
10n
AB24
RX0_I_P I_IP_CH0 AD21
VDD_A4
AA24 R208
RX0_I_M I_IM_CH0
AA16 22k
VDD_A5
W24
RX0_Q_P Q_IP_CH0 AD16 +2.85V_TCXO TEMP_ADC
VDD_A6
C221
C217
C219
C223
Y24
RX0_Q_M Q_IM_CH0
33n
C225
AD22
+/-1%
150k
R212
V24 VDD_A7
RX1_I_P I_IP_CH1 T24
U24 VDD_A8 R211
1
RX1_I_M I_IM_CH1 T25 1608
U22 VDD_A9
NCP18WD683E03RB
RX1_Q_P Q_IP_CH1 W25
V22 VDD_A10
RX1_Q_M Q_IM_CH1 Y25
VDD_A11
B11
TX_I_P I_OUT B20
B12
VDD_MDDI +1.8V_MSMP1
C202 TX_I_M I_OUT_N AA14
A12 A2[19]
10n
TX_Q_P Q_OUT V14
+2.6V_MSMA A11 A2[18]
TX_Q_M Q_OUT_N AB13
D12 A2[17] EBI2_AD
DAC_REF DAC_REF AD12
A2[16] A2[16]
U201
G11
PA_ON1 PA_ON1/GPIO[2] W13
E16 A2[15] A2[15]
PA_ON0 PA_ON0 AB12
E11 A2[14] A2[14]
TX_ON TX_ON
MSM6575-NSP
AA13
D17 A2[13]
PA_R1 PA_RANGE1 AE10
G17 A2[12]
PA_R0 PA_RANGE0 AD10
D20 A2[11]
TCXO_EN TCXO_EN/GPIO[94] AB11
H13 A2[10]
TRK_LO_MSM TRK_LO_ADJ AA12
E13 A2[9]
TX_AGC_ADJ TX_AGC_ADJ
N24
PA_POWER_CTL
A2[8]
A2[7]
W12
V13
<PCB Revison CHECK>
AA22
PA_DAC_EXT_REF AB10
Y22 A2[6]
BATT_ADC HKAIN[5] AA11
AA21
A2[5]
W21
V17
V18
ACC_ADC
N14
N15
P14
P15
U18
P11
P12
P13
V19
W19
AA5
HKAIN[4] AB9
V9
R210
U8
V8
W7
U19 A2[4]
VICHG HKAIN[3] V12
100k
AD23 A2[3] +2.85V_TCXO VER_ADC
TEMP_ADC HKAIN[2] AA9 +/-1%
W22 AB4 A2[2]
BATT_TEMP_ADC
C226
HKAIN[1] AA10
33n
R213
V21 AB22 A2[1]
75k
VER_ADC HKAIN[0] AA8
D18 A1 AC1 D2[15] D2[15]
MSM_TCXO TCXO
AB8
A9 A2 AC25 D2[14] D2[14]
USB_XTAL_48_IN W11
B9 A3 AD1 D2[13] D2[13]
USB_XTAL_48_OUT W10
C230 27p A15 A24 AD2 D2[12] D2[12]
SLEEP_XTAL_IN AD6
B15 A25 AD24 D2[11] D2[11]
1
SLEEP_XTAL_OUT AB7
R200
G13 B1 AD25 D2[10] D2[10]
1m X202 RESIN/ RESIN_N V11
G12 RESOUT_N B2 AE1 D2[9] D2[9]
W9
2
WDOG_EN
B25 VSS_THERMAL AE3 D2[7]
AA7
D2[7]
1 2 AD4
CM315_12_5PF R22 MODE2
C1 AE23 D2[6] D2[6] A 100K 5.6K 07,15
X201 V10
ICRT20S48M0X514CR 3 T22 MODE1
C25 AE24 D2[5] D2[5]
AB6
Y21 MODE0
D4 AE25 D2[4]
AB5
D2[4] B 100K 12K 16,25
R204 10k AC2 D22 R11 D2[3] D2[3]
+1.8V_MSMP1 BOOT_MODE_2 W8
R205 10k AD20
BOOT_MODE_1
E5 R12 D2[2]
AD3
D2[2] C 100K 19.1K 26,34
R206 10k AD19 E20 R13 D2[1] D2[1]
+2.6V_MSMP2 BOOT_MODE_0 AA6
SLEEP_CLK(32.768KHZ) MDDI_D+ B19
MDDIH_DATP
E21 R14 D2[0] D2[0] D 100K 27K 35,43
GND 3 L25
4 Y
B18 G7 R15
GPIO[101]/SDCC_DAT[3] AUDIO_I2C_SDA
MDDI_D- MDDIH_DATN L24
A19
GPIO[100]/SDCC_DAT[2] AUDIO_I2C_SCL E 100K 36K 44,53
A 2 MDDI_STB+ MDDIH_STBP K19
A18 GPIO[99] FMR_RESET/
+2.6V_MSMP2 5 VCC NC MDDI_STB- MDDIH_STBN T5
1
B21 GPIO[78]/A1[23]/SDRAM1_DQM[2] SDRAM_DQM[2] F 100K 47K 54,60
J8
G19
H8
H9
H17
H18
N11
N12
M13
L14
L15
M11
M12
N13
J18
L12
L13
M14
M15
MDDIC_DATP T8
NL17SZ16XV5T2G B22 GPIO[75]/SDRAM1_DQM[3] SDRAM_DQM[3]
MDDIC_DATN U4
U200
A21 MDDIC_STBP
GPIO[74]/SDRAM_CLK_EN[3]
U7
D1[23] H 100K 56K 61,70
A22
GPIO[73] D1[22]
MDDIC_STBN AA2
M25 GPIO[72] D1[21] 1.0 100K 75K 71,83
USB_DATA USB_DAT_VP Y2
N21 GPIO[71] D1[20]
USB_SE0 USB_SE0_VM E1
M24
USB_OE_TP_N
GPIO[70] D1[19] 1.1 100K 100K 84,97
USB_OE/ GPIO[69]
P8
D1[18]
P18
DSP_PWRON USB_RX_DATA/GPIO[29] T4
J25
USB_SUSPEND/GPIO[17]
GPIO[68] D1[17] 1.2 100K 130K 98,AC
CAM_RESET/ GPIO[67]
T7
D1[16]
H10
HS_UART_RES/ RX_VCO_SEL/GPIO[43]
G9
GPIO[66]
JDET_INT
A5 UHF_VCO_1_SEL/GPIO[28] H14
CAM_PWR_DOWN
AA17
CAMIF_FOCUS[1]/GPIO[64] FMR_RBDS_INT
HPH_R HPH_R D10
W17 GPIO[53] BT_RESET/
HPH_L HPH_L G10
GPIO[52]
E14 MMC_DATA/GPIO[32] PMIC_IRQ/
A6
GPIO[51] AUDIO_SW1_EN
3D & FMR I2C BAT_ID_PULL_UP L18
G14
MMC_CLK/GPIO[31]
GPIO[50]
B6
KYPD[11]
MMC_CMD/GPIO[30]
H11
E19
GPIO[49] KYPD[9]
CAM_D[7] CAMIF_DATA9/GPIO[61] D5
G16
GPIO[45] CP_RESET/
CAM_D[6] CAMIF_DATA8/GPIO[60] D8
D21 GPIO[44] LIN_PWM_FREQ
CAM_D[5] CAMIF_DATA7/GPIO[59]
E8
H15 GPIO[42] PS_HOLD
CAM_D[4] CAMIF_DATA6/GPIO[58]
G8
K18 GPIO[40] HS_UART_LOWPWR
CAM_D[3] CAMIF_DATA5/GPIO[57]
D7
D19
CAMIF_FOCUS[0]/GPIO[39] EAR_JACK_SENSE
CAM_D[2] CAMIF_DATA4/GPIO[56] AA15
G21 GPIO[36]/XMEM2_CS_N[3] DSP_INT/
CAM_D[1] CAMIF_DATA3/GPIO[55] W15
GPIO[35]/XMEM2_CS_N[2] DSP_CS/
AUX_PCM_SYNC/SDAC_L_R_N/TSIF_ERROR/[GPIO102]
E18
CAM_D[0] CAMIF_DATA2/GPIO[54] AE11
DSP_RESET/
AUX_PCM_DOUT/SDAC_DOUT/TSIF_INTR/GPIO[103]
H25 GPIO[34]/A2[20]
3D_FMR_I2C_SCL CAMIF_DATA1/GPIO[81] E22
GPIO[19] PROXI_SCL
AUX_PCM_CLK/SDAC_CLK/TSIF_NULL/GPIO[80]
H24
3D_FMR_I2C_SDA CAMIF_DATA0/GPIO[83] M18
E6 GPIO[18]/RINGER AUDIO_SW2_EN
CAM_VSYNC CAMIF_VSYNC/GPIO[16]
D6
F21 GPIO[12]/GRFC[9] TOUCH_I2C_SCL
CAM_HSYNC CAMIF_HSYNC/GPIO[15]
E7
J22 GPIO[11]/GRFC[8] TOUCH_I2C_SDA
CAMIF_PCLK/GPIO[82]
CAM_PCLK P22
PROXI_SDA
AUX_PCM_DIN/SDAC_MCLK/GPIO[14]
KEYSENSE3_N/GPIO[47]
KEYSENSE2_N/GPIO[46]
KEYSENSE1_N/GPIO[63]
KEYSENSE0_N/GPIO[62]
K22
PROXI_OUT
SYNTH2/GPIO[65]
SYNTH1/GPIO[41]
SYNTH0/GPIO[92]
UIM2_RESET/TSIF_ENABLE/GPIO[86] L22
M21 CAMIF_ZOOM[1]/UART1_DP_RX/GPIO[96] MKEY_BL_EN
3D_INT UIM2_PWR_EN/TSIF_DATA/GPIO[85] K25
CAMIF_ZOOM[0]/UART1_DP_TX/GPIO[95]
EAR_MIC_KEY M19
UIM2_DATA/TSIF_SYNC/GPIO[84] CHG_MODE/
LINE_R_IN
LINE_R_IP
LINE_L_IN
LINE_L_IP
RESERVED1
RESERVED2
GND_RET1
HPH_VREF
GND_RET2
V7
MICBIAS
LINE_OP
LINE_ON
AUX_OUT
LCD_VSYNC_OUT MDP_VSYNC_PRIMARY/GPIO[105]
EAR1OP
EAR1ON
TRST_N
MIC1P
MIC1N
MIC2P
MIC2N
AUXIP
AUXIN
CCOMP
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
AA4
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
SD_DETECT/ MDP_VSYNC_SCONDA/GPIO[104]
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
RCLK
TMS
TDI
TDO
TCK
CON200
JTAG_STD_2COLUMN_10P
H1
R25
W1
A4
A10
A13
AB1
AE7
AE14
U1
M22
F25
R1
M1
K1
F1
AE5
AE9
AE13
P25
A8
A14
AC24
B23
D1
D25
AA20
E15
G15
D14
A16
D16
D15
AE21
U25
V25
W16
W18
K21
N18
AE22
U21
P21
D13
P19
R19
V16
L19
E4
C24
AA19
AE15
B16
A20
A17
AA25
AB15
AB25
D11
E17
N25
T19
G22
G18
AB19
AE16
AB16
AB17
H7
B5
AE18
AE17
AE20
AE19
AD18
AD17
AB20
AB21
AB18
AA18
1
TCK TCK
2
RTCK RTCK
3
1u
TDO
1u
C208
TDO
1u
4
22n
22n
22n
22n
TDI TDI
RCV-
RCV+
C201
C200
5
TMS TMS
22n
TCK
22n
6
TRST_N TRST
LCD_ID_CHECK
KYPD[7]
KYPD[5]
KYPD[3]
KYPD[1]
C206
HS_UART_INT
ONO/
C204
C203
C205
BT_WAKEUP
RTCK 7
+2.6V_MSMP2 VCC
TDO 8
C229
RESIN/ RESIN
C228
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_SYNC
TDI 9
BT_PCM_CLK
FMR_ANALOG_R
FMR_ANALOG_L
PS_HOLD PS_HOLD
TMS 10
GND
TRST_N
MIX_L
MIX_R
MIC+
EAR_MIC
CAM_SDA
CAM_SCL
C207
0.1u
R207
2.2k
MIC_BIAS
MCP(2G NAND+1G SDRAM) <BLUETOOTH UART>
+2.6V_MSMP2
C311
2.2u
N10
N11
N12
N13
T13
U14
V13
V14
W11
W12
W13
W14
Y11
Y12
Y13
Y14
P7
P8
R2
R7
R9
T2
T3
T7
U1
U3
V1
V2
W1
W2
W3
W4
Y1
Y2
Y3
Y4
A1
D4
C2
C4
A2
A4
B2
B3
E2
NC96
NC97
NC98
NC99
NC100
NC101
NC102
NC103
NC104
NC105
NC106
NC107
NC108
NC109
NC110
NC111
NC112
NC113
NC114
NC115
NC116
NC117
NC118
NC119
NC120
NC121
NC122
NC123
NC124
NC125
NC126
NC127
NC128
NC129
NC130
NC131
VDD1
VDD2
VSS1
VSS2
NC1
NC2
NC3
NC4
NC5
DQ0 U4 D1[0] F4
D2[0] D0
A[0] C3 A0 DQ1 T4 D1[1] E4
D2[1] D1
A[1] D3 A1 DQ2 T5 D1[2] F5 C5
D2[2] D2 TX BT_MSM_DP_TXD
A[2] E3 A2 DQ3 V5 D1[3] E5
E2 U5 D2[3] D3
A[3] A3 DQ4 D1[4] F6
D12 T6 D2[4] D4
A[4] A4 DQ5 D1[5] E6
C12 V6 D2[5] D5
A[5] A5 DQ6 D1[6] D6
D11 U7 D2[6] D6
A[6] A6 DQ7 D1[7] D5
C11 T9 D2[7] D7
A[7] A7 DQ8 D1[8] A3 C6
D10 T10 OE2/ IOR RX BT_MSM_DP_RXD
A[8] A8 DQ9 D1[9] B4
U301
C10 V10 WE2/ IOW SC16C850IET
A[9] A9 DQ10 D1[10] F1 D2
E4 T11 HS_UART_RES/ RESET RTS BT_MSM_DP_RFR/
A[10] A10 DQ11 D1[11]
D9 U11
A[11] A11 DQ12 D1[12] C1 D3
C9 V11 A2[14] A0 CTS BT_MSM_DP_CTS/
A[12] A12 DQ13 D1[13] C3 E1
M11 T12 A2[15] A1 DTR
D2[0] I/O1 DQ14 D1[14] B1 R305
M13 U12 A2[16] A2
D2[1] I/O2 DQ15 D1[15] R301 B6 F2
10k
L10 P3 HS_UART_CS/ CS DSR +2.6V_MSMP2
D2[2] I/O3 DQ16
D1[16] 10k
L12 R3 +2.6V_MSMP2
D2[3] I/O4 DQ17 D1[17] B5 F3
J9 P4 HS_UART_LOWPWR LOWPWR RI
D2[4] I/O5 DQ18 D1[18]
H12 R4
D2[5] I/O6 DQ19 D1[19] D1 E3
XTAL1
XTAL2
H10 P5 HS_UART_INT INT CD
D2[6] I/O7 DQ20 D1[20]
G12 R5
D2[7] I/O8 DQ21 D1[21]
M12 P6
D2[8] I/O9 DQ22 D1[22]
A6
A5
L9 R6
D2[9] I/O10 DQ23
D1[23] X300
L11 P9
D2[10] I/O11 DQ24 D1[24] XF500G48003TEH00
K9 P10
D2[11] I/O12 DQ25
D1[25] 4 3
H13 R10 +2.6V_BT VDD OUT
D2[12] I/O13 DQ26 D1[26]
H11 I/O14 P11 1 2
D2[13] DQ27 D1[27] UART_EN SW GND
15p
C322
H9 R11
D2[14] I/O15 DQ28 D1[28]
G11 I/O16 P12
D2[15] DQ29 D1[29]
R12
C312
0.1u
NAND_FLASH_CS/ M9 CE
U300 DQ30
DQ31 R13
D1[30]
D1[31]
TYAB0A111081KC
M10 C4
OE2/ RE BA0 A[13]
K6 D4
WE2/ WEn BA1 A[14]
M4 C8
NANDF_CLE CLE CLK SDRAM_CLK
M3 D8
NANDF_ALE ALE CKE SDRAM_CLK_EN
L6 D7
NANDF_WP/ WP NC56
M2 E5
NAND_READY/ RY/BY CS2 SDRAM_CS/
C7 D5
+1.8V_MSMP1 VCCd1 RAS SDRAM_RAS/
D2 E6
VCCd2 CAS SDRAM_CAS/
C308
C300
C302
C305
10n
D13 D6
100n
120p
100n
V8 T8
VCCd5 DQM1 SDRAM_DQM[1]
V12 V7
C301
C304
C307
100n
120p
V4 U9
VCCQd1 DQM3 SDRAM_DQM[3] L301
V9 VCCQd2 VSS11 U10 BLM15AG601SN1
K12 U13 2
+2.6V_MSMP2 VCCn VSS12
C6 VSS1
C303
C306
100n
C321
2.2u
C323
C325
R303
J3
10n
10n
10p
F7 VSS2 NC62 0
G2 VSS3 NC63 J4 +2.6V_MSMP2
10n
J5 ANT300 ANT301
G13
C319
C320
VSS4 NC64
10n
L13 VSS5 NC65 J6
1 1 R304
P2 VSS6 NC66 J10 R308
0
DNI
P13 J11
VSS7 NC67 +2.6V_BT
R8 J12 1005
C324
C326
VSS8 NC68
10p
C318
1u
U2 J13 F300
VSS9 NC69 2.2u
LFB212G45SG8A166
U6 VSS10 NC70 K1
L300
1.5n C315
NC71 K2 10p
4 IN OUT 2
A3
G8
A6
G5
F8
A5
A1
G1
F1
E1
B1
A2
B8
C1
A1 NC1 NC72 K3
1005
G1 G2
DNI
A2 K4
C310
1005
NC2 NC73
DNI
VBAT
VDDO3
VDDO2
VDDO1
VDDC3
VDDC1
VREG
VDDPX
VDDRF
VDDLNA
VDDIF
VREGHV
VDDC2
L302
100n
VDDTF
C309
C316
A3 K5 1 3
NC3 NC74
1p
R302
A4 NC4 NC75 K10 15k
G4 RES
A11 K11 TP303
NC5 NC76
A12 NC6 NC77 K13
D1 B4
A13 NC7 K14
C314
100p
RFP RST_N BT_RESET/
NC78 B2
A14 NC8 L1 X301
REG_EN +2.6V_BT
NC79 SLEEP_CLK(32.768KHZ) F7 SCL TM0
C4
B1 L2 NX3225SA_EXS00A-CS00275
NC9 NC80
E7 F3
3 SDA TM2
B2 NC10 NC81 L3 4 TP304
B3 L4 A8 TP305
NC11 NC82 SPIM_CLK
1 C7
U302 PCM_IN
F6
BT_PCM_DOUT
B4 L5 2
C317
NC12 NC83 SPIM_CS_N
1005
BCM2070 G6
15p
B11 NC13 L14
PCM_OUT BT_PCM_DIN
NC86 A4 F4
C313
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NC52
NC53
NC54
NC55
NC61
E3
COEX_OUT0
COEX_OUT1
TCXO_OR_IN_GPIO6
B7
COEX_IN
TP300 TP301 GPIO_7
C14
D1
D14
E1
E7
E8
E9
E10
E11
E12
E13
F2
F3
F4
F5
F6
F8
F9
F10
F11
F12
F13
G3
G4
G5
G6
G7
G8
G9
G10
H2
H3
H4
H5
H6
J2
VSS4
VSS7
VSS6
VSS5
VSS3
VSS2
VSS1
TP302 TP308
E4
E5
G7
B6
A7
C6
F2
D2
C2
D3
<Power Management IC>
<FM Receiver>
+VPWR
C418
100n
1608
1608
C419
4.7u
C420
4.7u
C421
+V_CHAR
1u
C443
C1
C2
D1
D2
E1
H6
E7
B7
1608
22n
C413
L400
1u
MIP2520D2R2M
CHGINA
CHGINB
BATTA
BATTB
REFBP
IN4
IN2
IN1
C414
100p FMR_RBDS_INT +VPWR
F1 A7 1 2 1k
VBUSB LX1
C424 +1.275V_MSMC R440
C4 200p
VICHG FMR_ANALOG_L
1608
VICHG
C425
4.7u
R418
100k
C416
E2 A5 U402
VL PGND
SI4709-B-GMR FMR_ANALOG_R
16
GPO 15
VA 14
LOUT 13
100n C3 B4
+2.6V_MSMP2 ONO/ ONO_ FB1
TP401
1608
NC2
B6
C412
4.7u
R415
PWR_ON_SW
100k
PWRON
R419
68K
R412 B3 E6 L401
HFPWR RESET_
10k RESIN/ MIP2520D2R2M C415 1 NC1
B2 ROUT 12
R402
2.2k
R403
2.2k
PS_HOLD PWRHOLD 1n
2 FMI
F6 A6 1 2 FMR_ANT GND 11
PMIC_IRQ/ TP400
IRQ_ LX2 +2.3V_BUCK2 3 RFGND
300k
R426
F5 B5 VD 10
C442
3.3p
PMIC_SDA +VPWR
1608
DATA FB2 4 RST
C437
4.7u
E5 9
PMIC_SCL CLK C436 RCLK
C445
R422 0 82p
G7
22n
B1
+2.3V_BUCK2 IN5 OUT1 +2.6V_MSMP2
SCLK
SDIO
VIO
5 SEN
A1 A3
R439
100k
R427
OUT10 IN3
+2.1V_TX U400 +2.3V_BUCK2 R423 0
0
G4 MAX8675EWN_ A4 G_SLUG
+2.6V_BT OUT11 OUT2
+1.8V_MSMP1
7
8
R417 0
F4 D7 17
TP407 COMP1 OUT3 +2.6V_MSMA
C410
C411
F3 F7
C405
1u
R420 0
1u
E4 A2
COMP2 OUT5
R421 0 +2.1V_RX0 +2.6V_MSMP2
E3 C5 SLEEP_CLK(32.768KHZ)
INV2 ENO5 SLEEP/ +2.1V_RX1 3D_FMR_I2C_SCL
D6 G6
TCXO C404 R411 TCXOIN OUT6 +2.85V_GPS 3D_FMR_I2C_SDA
10n 51
C6 C7
MSM_TCXO TCXOOUT OUT7 +2.85V_TCXO
D3 TP402
H5
R437
4.7k
R438
4.7k
XIN ENO7 TCXO_EN
H4 H7
XOUT OUT8
R425 0
+3.0V_LIN_MOTOR +2.6V_MSMP2
D5 G5
32KHZ OUT9 +2.6V_TOUCH
F2
C444
100p
+V_CHAR C417
VBUSA
+2.6V_MSMP2
G3 H1 TP403
VTRM OE_
R404 24 1u H3 G2 TP404 USB_OE/
USB_D+ DP USBDAT USB_DATA
R405 24 H2 G1 TP405
2.2u 1608
USB_D- DM SE0 USB_SE0
GND
1608
C426
2.2u
C427
C428
C429
C430
2.2u
C431
C432
C433
C434
D4
1u
1u
1u
1u
1u
1u
TP406
F401
RP104K281D-TR-F
1 4
+2.8V_LCD VOUT VDD +VPWR
2 3
GND CE_NC +2.6V_MSMP2
C422
100n
C423
100n
G_SLUG
5
<Shield Can>
<MICRO USB CONNECTOR> SC400
CAN_AX8575
1
G1 29
CON400 G29
2
10
6
G2
8
HSMU-5SB-24DR2 28
G28
3
G3
GND1
GND3
27
GND5
G27
4
G4 26
G26
5
1 G5 25
+V_CHAR P1 <VBUS> 6
G25
2 G6 24
P2 <D->
1608
G24
10n
C401
47p
C406
7
C400
1608
G7 23
10n
R407 3
P3 <D+>
5 21
P5 <GND> 10
G21
ACC_ADC G10 20
TVS,5V,100W
G20
TVS,5V,100W
GND2
GND4
11 GND6
11 G11
SDB1040
19
G19
12 G12
D402
18
D401
R431
C408
D400
G18 ANT400
33n
13 G13
9
7
17
G17
14 G14
16
G16 1
15 G15
U401
UART-TP
USB_D-
NC3
C402
12
27p
NC2
11
NC1
10
USB_D+
9
USB_D-
8
+V_CHAR 7
USB-POWER
USB_D+ +VPWR 6
VBATT
PWR_ON_SW ON_SW
C403
F400 5
27p
DG2722
V_CHAR
4
<BATTERY CONTACT>
1 6 UART-TXD
D+ HSD1- 3
2 7 UART-RXD
D- HSD1+ 2
3 8 GND
GND _OE USB20_EN/ 1
4 9 R408 100
HSD2- V+ +VPWR
5 10 Q401
HSD2+ S USB20_SEL SI5441BDC-T1-E3
C407
100n
8 1 CON401
D6 D1
KQ03LE-4R_S
F402 7 2
D5 D2
NFM18PC104R1C3 6 1
D4 3 +
D3
USB20_D+ 1 3 5 4 R430 80.6k 2 THM/
+VPWR INPUT OUTPUT S G +2.6V_MSMA
+/-1% 3 -
GND1 GND2
R429 4.7k 4 TX
USB20_D- 2 4 +2.6V_MSMP2
251M1002336MR3S
+1
C435
R416
33u
DUMMY
TA_DET/ +2.6V_MSMP2 R413 DNI
22k - 2 BAT_ID_PULL_UP
Q402
R409 C3 KRX102E BAT_ID_CHK
PSD05-LF
470k
2 Q400
3
4
USB_D- +VPWR BATT_TEMP_ADC
2
B KTC4075E
C439
R410
150k
22p
+/-1% E1
D403
2
R428
CHG_MODE/
22k
R414
470k
R433
R432
C438
5
1
1
33n
100p
100p
0.1u
C409
<AUDIO SUBSYSTEM>
C531
<EARPHONE JACK>
+2.6V_MSMP2 1u R500 0
+VPWR
FMR_ANALOG_R
B1
B4
C502
C503
100n
LSVDD
VDD
1u
HPH_L
E1 A4
MIX_R INM+ LSOUT+ SPK+ +/-1% R515 R516 U507
NLAS3158MNR2G
16
15
14
13
1k 1k
NLAS3799BMNR2G
D1 A3 +2.6V_MSMA
U503
MIX_L INM- LSOUT- SPK- +/-1% C520 2 COM1 1
1608
COMA
NOA
VCC
NCD
NC1
C518
470p
10u
11
NO1 COM2 4
C500
220n 5 NC2 VCC2 9
1 12 C2 D2
AMP_R NCA COMD INR SET 8
2 11 NO2 VCC1 12 +2.6V_MSMP2
C501 R509
AUDIO_SW1_EN IN_A_B NOD
220n 24 10 S1 GND2 3
3 10 C1 E3 EAR_JACK_SENSE
C530
FMR_ANALOG_L NOB IN_C_D INL U500 HPL LHP_EJ 7 6
EAR_MIC_KEY S2 GND1
1u
4 9 LM49151
COMB NCC
+2.6V_MSMP2
R522
15k
C3
C510
100n
C512
100k
BYPASS
COMC
GND
NCB
NOC
R501
1.2k
R502
1.2k
A1 EAR_MIC
I2CVDD
B2
5
7
8
R503
AUDIO_I2C_SDA SDA
24 R530
B3 E2
AMP_L AUDIO_I2C_SCL RHP_EJ 200k
CPVSS
CPGND
SCL HPR
+2.6V_MSMP2
GND
C1N
C1P
C506
C513
27p
100n
ICVS0505500FR
ICVS0505500FR
A2
C4
D3
D4
E4
C504
2.2u
AUDIO_SW2_EN
HPH_R
C507
2.2u
C509
2.2u
10k
10k
3/4POLE DETECT
R531
R532
R507
R505
U506
NCS2200SQ2T2G
1 5
EAR_MIC_KEY OUT VCC
+2.6V_MSMP2
2 VEE R527
680k
3 4
EAR_MIC IN+ IN-
C524
1u
R526
39k
TOUCH VIBRATION
U508
DMJBRN1036BM
<3D ACCELATION SENSOR>
U501
SM100 1
1 8 U502
LIN_MOT_EN
+
EN V1
MOT+ BMA150
2 7
LIN_PWM_FREQ SIN VSS +2.6V_MSMP2
10k 3 6 1 10
+3.0V_LIN_MOTOR TYPE VCC +3.0V_LIN_MOTOR NC1 NC2
R506
4.7k
R508
4.7k
R529
ESD9X5_0ST5G
ESD9X5_0ST5G
4 5 2 9
OCT V2
MOT- +2.6V_MSMP2 VDD VDDIO
-
3 8
G_SLUG GND SDI 3D_FMR_I2C_SDA
2
4 7
C511
3.9n
C514
R504
240k
G_SLUG1
G_SLUG2
1u
5 6
3D_FMR_I2C_SCL
D500
D501
CSB SCK
TP500
TP502
11 12
C505
C508
22n
1u
TP504
LRA MOTOR
Vrms = 2.07V : 240K
LCD CHARGE PUMP & CAM LDO
C523
1u C522
1u
B5
A4
C5
C6
A5
R528 0
+2.6V_MSMP2 LED_VOUT
C2N
C1N
C1P
C2P
CPGND
<TOUCH DRIVER IC>
1608
C527
2.2u
B6 D6
C517
1608
1u
F4
C519
4.7u
VBAT1
F5 A2
VBAT2 LED1 LED1
2.2k
R513
2.2k
R514
TOUCH_I2C_SDA B1
LED2 LED2
D5 B2
TOUCH_I2C_SCL VIO LED3 LED3
B4 C2
U504 Y-_BOTTOM CP_RESET/ RESETB LED4 LED4
C4 D1
D3
D2
TP505
D1
R512
1.2k
D4 D2
CP_I2C_SDA LED6
Y-
GND
SCL
SBIAS
A0
Y+
2 9
X+_LEFT Y-_BOTTOM
3 8 R517 E1 E6
B1
B2
B3
PD_OUT +3.0V_MOVINAND
C516
SSENS LDO1O
100n
C515
2.2u
10k +/-1%
4 7 F2 E5
Y+_TOP X-_RIGHT SGND LDO2O +2.8V_CAM_ANALOG
5 6 D3 E4
G1 G2 G3 G4
PD_GAIN_CTRL1 GC2 LDO3O +2.6V_CAM_IO
E2 E3
PD_GAIN_CTRL2 GC1 LDO4O +1.8V_CAM_CORE
11 12 13 14
Y+_TOP
GND1
C521
C525
C526
C529
T2
T4
T3
T1
TOUCH_PENIRQ/
1u
1u
1u
1u
C528
1u
TP501
F1
F6
A6
A1
A3
DSP SIA417D
F601
7
MOVINAND 1GBytes
D5
1 6
D1 D4
2 5
D2 D3
3 4
G S1 +1.3V_DSP_CORE
S2
8
TP614
DSP_USB_PWR_EN/
TP615
TP616
+2.6V_MSMP2
TP618
+1.8V_DSP_IO
+3.3V_DSP_USB
+1.3V_DSP_CORE +3.0V_DSP_IO
2.2u
D4 A1_INDEX G10
NC58
1u
1u
1u
1u
2.2u
C600 1u
G12
1u
NC59
1u
C612 1u
1u
C611 10n
1u
1u
1u
1u
1u
1u
A3
C604
C605
G13
C601
C602
MOVI_D[0] DAT0 NC60
C603
C606
C607
A4
C614
G14
C613
C644
MOVI_D[1] DAT1
C618
C617
C610
C620
NC61
C615
A5 H1
MOVI_D[2] DAT2
E11
NC62
J2
A5
C1
C3
K6
D8
H3
K5
E5
G6
D5
B5
D3
H4
G3
L5
B2 H2
MOVI_D[3] DAT3 NC63
B3 H3
DAT4 NC64
VDDA33_USB
VDDAP_DAC
VDDAA_DAC
VDDD_CO1
VDDD_CO234
VDDD_CO567
VDDD12_USB
VDDD12_PLL
VDDQ
VDDD_GA
VDDD_MC
VDDD_GB
VDDD_GC
VDDD_GD
VDDA_OSC
VDDD_GE
VDDD_RTC
B4 DAT5 H5
TP608 NC65
B5 H12
DAT6 NC66
J7 B6 H13
D2[0] GPIO_A0 DAT7 NC67
J8 R630 H14
D2[1] GPIO_A1 TP617
30
NC68
H8 M6 J1
D2[2] GPIO_A2 MOVI_CLK CLK NC69
K10 J2
D2[3] GPIO_A3 J5 NC70
L9 PWRON DSP_PWRON M5 J3
D2[4] GPIO_A4 MOVI_CMD CMD NC71
K11 J5
D2[5] GPIO_A5 A6 NC72
K9 LHPOUT AMP_L R604 C633 1u C2 VDDI J12
D2[6] GPIO_A6
DNI
NC73
L10 C6 J13
D2[7] GPIO_A7 A7 +3.0V_DSP_SD VDD1 NC74
AMP_R
1u
J9 RHPOUT 1005 M4 J14
D2[8] GPIO_A8 VDD2 NC75
L11 N4 K1
D2[9] GPIO_A9 B6 VDD3 NC76
C634
H7 HVCOM P3 K2
D2[10] GPIO_A10 VDD4 NC77
J11 TP620 P5 K3
D2[11] GPIO_A11 A3 VDD5 NC78
H10 LOUT E6 K5
D2[12] GPIO_A12 A4 R638 0 VDDF1 NC79
1u
H11 ROUT F5 K6
D2[13] GPIO_A13 TP621 +3.0V_MOVINAND VDDF2 NC80
H9 J10 K7
D2[14] GPIO_A14 VDDF3 NC81
C635
B3
G11 BPLIN K9 K10
TP601 D2[15] GPIO_A15 B4 VDDF4 NC82
G7 BPRIN K12
TP602 DSP_INT/ GPIO_A16