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Lab Worksheet # 9

1. The document describes a lab experiment on 1-to-4 line and 1-to-8 line demultiplexers. The objectives are to design and understand the operation of these circuits and implement Boolean functions using them. 2. A 1-to-4 demultiplexer takes a single input and switches it to one of four output lines based on the values of two select lines. A 1-to-8 demultiplexer is developed by combining 1-to-4 demultiplexers and uses three select lines. 3. The procedure involves implementing the circuits using logic gates, applying various input combinations according to truth tables, and observing and recording the output readings. Boolean functions are written for the outputs

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MUNEEB SHAH
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0% found this document useful (0 votes)
163 views

Lab Worksheet # 9

1. The document describes a lab experiment on 1-to-4 line and 1-to-8 line demultiplexers. The objectives are to design and understand the operation of these circuits and implement Boolean functions using them. 2. A 1-to-4 demultiplexer takes a single input and switches it to one of four output lines based on the values of two select lines. A 1-to-8 demultiplexer is developed by combining 1-to-4 demultiplexers and uses three select lines. 3. The procedure involves implementing the circuits using logic gates, applying various input combinations according to truth tables, and observing and recording the output readings. Boolean functions are written for the outputs

Uploaded by

MUNEEB SHAH
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Digital Logic Design Lab Spring 2021

Title: 1 -to-4 Lines & 1-to-8-Line De-Multiplexer


Lab Worksheet #9
Name: SYED MUNEEB Semester: 2ND

Sapid#: 25420 Section: BS-CYB


INTRODUCTION & BASIC CONCEPTS:
The De-Multiplexer means “one to many. The demultiplexer takes one single input data line
and then switches it to any one of a number of individual output lines one at a time.
The demultiplexer converts a serial data signal at the input to a parallel data at its output
lines. It is also known as Data distributer .
Objectives
The objectives of this experiment
1. To design a 1 × 4 & 1 x 8 De- multiplexer using basic gates

2. To understand the operation of 1 × 4 & 1 x 8 De- multiplexer.

3. To implement the Boolean function using 1 × 4 & 1 x 8 De- multiplexer.

Equipment Required
IC 74LS08 Cutter
IC 74LS32 Single Core Wire
IC 74LS04 Tweezers
Multi-meter Pair of Pliers

Diagram

Figure 1. The block diagram of 1  4 De-multiplexer

1
Faculty of computing, Riphah International University, I-14, Islamabad
Digital Logic Design Lab Spring 2021

Logical Diagram of 1 X 4 De-Multiplexer:

Function table
Complete the table given below carefully by using circuit developed by you.

Data So S1 Io I1 I2 I3 F20
D 0 0 1 0 0 0 1
D 0 1 0 1 0 0 1
D 1 0 0 0 1 0 1
D 1 1 0 0 0 1 1

2
Faculty of computing, Riphah International University, I-14, Islamabad
Procedure
1) Firstly, we will open logic gate simulator.
2) Then we will add 4 inputs which will take inputs
3) And select 8 and gate
4) Implement the circuit using and gate which IC is 7400
5) Connect the inputs to the input switches .
6) Connect the outputs to the switches.
7) Apply various combinations of inputs according to the truth table and
observe the condition of LEDs.
8) Note down the corresponding output readings for various combinations of
inputs.
.

Write a Boolean function for output of 1x4 De-Multiplexer For Each Case
F(So, S1, Io,I1,I2,I3,I4)=
F1 = D S0’ S1’
F2 = D S0’ S1
F3 = D S0 S1’
F4 = D S0 S1
1 x 8 Line De-Multiplexer:

Develop 1 – To- 8 Line De- Multiplexer Using 1- To 4 Line De-Multiplexer


Function table
Complete the table given below carefully by using circuit developed by you.

Data Select lines Outputs Output


D S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 F
D 0 0 0 1 0 0 0 0 0 0 0 1
D 0 0 1 0 1 0 0 0 0 0 0 1
D 0 1 0 0 0 1 0 0 0 0 0 1
D 0 1 1 0 0 0 1 0 0 0 0 1
D 1 0 0 0 0 0 0 1 0 0 0 1
D 1 0 1 0 0 0 0 0 1 0 0 1
D 1 1 0 0 0 0 0 0 0 1 0 1
D 1 1 1 0 0 0 0 0 0 0 1 1

Write a Boolean function for output of 1x8 Line De-Multiplexer:

I0 S2’S1’S0’
I1 S2’S1’S0
I2 S2’S1 S0’
I3 S2’S1 S0
I4 S2 S1’S0’
I5 S2 S1’S0
I6 S2 S1 S0’
I7 S2 S1 S0
Lab Instructor
Mr. Umar Sultan
Faculty of Computing,
Riphah International University
Sector I-14, Islamabad.
Email: [email protected]

The End

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