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Describing a design:

In VHDL an entity is used to describe a hardware module. An entity can be

described using,
1. Entity declaration.
2. Architecture.
3. Configuration
4. Package declaration.
5. Package body.
Let’s see what are these?

Entity declaration:
It defines the names, input output signals and modes of a hardware module.
Syntax:
entity entity_name is
Port declaration;
end entity_name;

 An entity declaration should starts with ‘entity’ and ends with ‘end’ keywords.
 Ports are interfaces through which an entity can communicate with its environment.
 Each port must have a name, direction and a type. An entity may have no port
declaration also. The direction will be input, output or inout.
In Port can be read
Out Port can be written
Inout Port can be read and written
Buffer Port can be read and written, it
can have only one source.

Architecture:
 It describes the internal description of design or it tells what is there inside design.
Each entity has atleast one architecture and an entity can have many
architecture.

 Architecture can be described using structural, dataflow, behavioral or mixed

style.

 Architecture can be used to describe a design at different levels of abstraction like

gate level, register transfer level (RTL) or behavior level.
Syntax:
architecture architecture_name of entity_name
architecture_declarative_part;
begin
Statements;
end architecture_name;
 Here we should specify the entity name for which we are writing the architecture
body. The architecture statements should be inside the begin and end keyword.

 Architecture declarative part may contain variables, constants, or component

declaration.
Configuration:
 If an entity contains many architectures and any one of the possible architecture
binding with its entity is done using configuration.
 It is used to bind the architecture body to its entity and a component with an
entity.
Syntax:
configuration configuration_name of entity_name is
block_configuration;
end configuration_name.

Package declaration:
Package declaration is used to declare components, types, constants, functions and so
on.
Syntax:
package package_name is
Declarations;
end package_name;

Package body:
A package body is used to declare the definitions and procedures that are declared in
corresponding package. Values can be assigned to constants declared in package in package
body.
Syntax:
package body package_name is
Function_procedure definitions;
end package_name;

The internal working of an entity can be defined using different modeling styles inside
architcture body. They are
1. Dataflow modeling.
2. Behavioral modeling.
3. Structural modeling.

Structure of an entity:
 Let’s try to understand with the help of one example.

Dataflow modelling:
Data Flow Modelling
 In this modelling style, the flow of data through the entity is expressed using concurrent
(parallel) signal. i.e In this style of modelling, the internal working of an entity can be
implemented using concurrent signal assignment.

 The concurrent statements in VHDL are WHEN and GENERATE.

 Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be
used to construct code.

 Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of
code.
In concurrent code, the following can be used −
 Operators
 The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
 The GENERATE statement;
 The BLOCK statement
Let’s take half adder example which is having one XOR gate and a AND gate.

Library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ha_en is
port (A,B:in bit;S,C:out bit);
end ha_en;

architecture ha_ar of ha_en is

begin
S<=A xor B;
C<=A and B;

end ha_ar;

 Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic

type, called STD_ULOGIC.
 use is a keyword, which imports all the declarations from this package.
 The architecture body consists of concurrent signal assignments, which describes the
functionality of the design.
  Whenever there is a change in RHS, the expression is evaluated and the value is
assigned to LHS.

Behavioral modelling:

In this modelling style, the behavior of an entity as set of statements is executed

sequentially in the specified order. Only statements placed inside a PROCESS,
FUNCTION, or PROCEDURE are sequential.
PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that
are executed sequentially.
However, as a whole, any of these blocks is still concurrent with any other statements placed
outside it.
One important aspect of behavior code is that it is not limited to sequential logic. Indeed,
with it, we can build sequential circuits as well as combinational circuits.
The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted
and they are supposed to be used in sequential code only. VARIABLE can never be global,
so its value cannot be passed out directly.

In this style of modeling, the internal working of an entity can be implemented using set of
statements.
It contains:
 Process statements
 Sequential statements
 Signal assignment statements
 Wait statements
 Process statement is the primary mechanism used to model the behavior of an entity.
It contains sequential statements, variable assignment (:=) statements or signal
assignment (<=) statements etc..

 Inside the process the execution of statements will be sequential and if one entity
is having two processes the execution of these processes will be concurrent. At the
end it waits for another event to occur.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ha_beha_en is
port(
A : in BIT;
B : in BIT;
S : out BIT;
C : out BIT
);
end ha_beha_en;

architecture ha_beha_ar of ha_beha_en is

begin
process_beh:process(A,B)
begin
S<= A xor B;
C<=A and B;
end process process_beh;

end ha_beha_ar;

Here whenever there is a change in the value of a or b the process statements are executed.

Structural modeling:
 In this modeling, an entity is described as a set of interconnected components. A
component instantiation statement is a concurrent statement. Therefore, the order
of these statements is not important.

 The structural style of modeling describes only an interconnection of components

(viewed as black boxes), without implying any behavior of the components
themselves nor of the entity that they collectively represent.

 In Structural modeling, architecture body is composed of two parts − the

declarative part (before the keyword begin) and the statement part (after the
keyword begin).

The implementation of an entity is done through set of interconnected components.

It contains:
 Signal declaration.
 Component instances
 Port maps.
 Wait statements.
Component declaration:
Syntax:
component component_name [is]
List_of_interface ports;
end component component_name;

Before instantiating the component it should be declared using component declaration as

shown above. Component declaration declares the name of the entity and interface of a
component.
Let’s try to understand this by taking the example of full adder using 2 half adder and 1 OR
gate.
 library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity fa_en is
port(A,B,Cin:in bit; SUM, CARRY:out bit);
end fa_en;

architecture fa_ar of fa_en is

component ha_en
port(A,B:in bit;S,C:out bit);

end component;

signal C1,C2,S1:bit;

begin

HA1:ha_en port map(A,B,S1,C1);

HA2:ha_en port map(S1,Cin,SUM,C2);
CARRY <= C1 or C2;

end fa_ar;
 The program we have written for half adder in dataflow modeling is instantiated
as shown above.
o ha_en is the name of the entity in dataflow modeling. C1, C2, S1 are the
signals used for internal connections of the component which are declared
using the keyword signal.
o Port map is used to connect different components as well as connect
components to ports of the entity.

Component instantiation is done as follows.

Component_label: component_name port map (signal_list);

Signal_list is the architecture signals which we are connecting to component ports. This can
be done in different ways. What we declared above is positional binding. One more type is
the named binding. The above can be written as,

HA1:ha_en port map(A => A,B => B, S => S1 ,C => C1 );

HA2:ha_en port map(A => S1,B => Cin, S=> SUM, C => C2);
---------------------------------------------------------------------------------

VHDL Programming Examples

Logic Operation – AND GATE

X Y Z

0 0 0

0 1 0

1 0 0

1 1 1

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity and1 is
port(x,y:in bit ; z:out bit);
end and1;

architecture virat of and1 is

begin
z<=x and y;
end virat;

Logic Operation – OR Gate

X Y Z
0 0 0
0 1 1
1 0 1
1 1 1
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity or1 is
port(x,y:in bit ; z:out bit);
end or1;

architecture virat of or1 is

begin
z<=x or y;
end virat;

Logic Operation – NOT Gate

X Y
0 1
1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity not1 is
port(x:in bit ; y:out bit);
end not1;

architecture virat of not1 is

begin
y<=not x;
end virat;

Logic Operation – NAND Gate

X Y z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity nand1 is
port(a,b:in bit ; c:out bit);
end nand1;

architecture virat of nand1 is

begin
c<=a nand b;
end virat;

Logic Operation – NOR Gate

X Y z
0 0 1
0 1 0
1 0 0
1 1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity nor1 is
port(a,b:in bit ; c:out bit);
end nor1;
architecture virat of nor1 is
begin
c<=a nor b;
end virat;

Logic Operation – XOR Gate

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity xor1 is
port(a,b:in bit ; c:out bit);
end xor1;

architecture virat of xor1 is

begin
c<=a xor b;
end virat;
Waveforms

Logic Operation – X-NOR Gate

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity xnor1 is
port(a,b:in bit ; c:out bit);
end xnor1;

architecture virat of xnor1 is

begin
c<=not(a xor b);
end virat;
Waveforms

This chapter explains the VHDL programming for Combinational

Circuits.
VHDL Code for a Half-Adder
VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port(a,b:in bit; sum,carry:out bit);
end half_adder;

architecture data of half_adder is

begin
sum<= a xor b;
carry <= a and b;
end data;

VHDL Code for a Full Adder

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);

end full_adder;

architecture data of full_adder is

begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;

VHDL Code for a Half-Subtractor

Library ieee;
use ieee.std_logic_1164.all;
entity half_sub is
port(a,c:in bit; d,b:out bit);
end half_sub;
architecture data of half_sub is
begin
d<= a xor c;
b<= (a and (not c));
end data;

VHDL Code for a Full Subtractor

Library ieee;
use ieee.std_logic_1164.all;
entity full_sub is
port(a,b,c:in bit; sub,borrow:out bit);
end full_sub;
architecture data of full_sub is
begin
sub<= a xor b xor c;
borrow <= ((b xor c) and (not a)) or (b and c);
end data;

VHDL Code for 4 to 1 Mux (Multiplexer)

Multiplexer (MUX) select one input from the multiple inputs and forwarded to output line
through selection line. It consist of 2 power n input and 1 output. The input data lines are
controlled by n selection lines.

For Example, if n = 2 then the mux will be of 4 to 1 mux with 4 input, 2 selection line and 1
output as shown below.
Truth Table for Multiplexer 4 to 1

VHDL Code of 4:1 Mux using Different Modeling Styles :

Behavioral Modeling of 4:1 mux

library ieee;
use ieee.std_logic_1164.all;
entity MUX4_1 is
port ( Sel : in std_logic_vector(1 downto 0);
A, B, C, D : in std_logic;
Y : out std_logic );
end MUX4_1;

architecture behavior of MUX4_1 is

begin
process (Sel, A, B, C, D)
begin
if (Sel = "00") then
Y<= A;
elsif (Sel = "01") then
Y<= B;
elsif (Sel = "10") then
Y<= C;
else
Y<= D;
end if;
end process;
end behavior;

Structural modeling of 4:1 mux

library ieee;
use ieee.std_logic_1164.all;
entity MUX4_1 is
port ( Sel0,Sel1 : in std_logic;
A, B, C, D : in std_logic;
Y : out std_logic );
end MUX4_1;
architecture structural of MUX4_1 is
component inv
port (pin : in std_logic;
pout :out std_logic);
end component;
component and3
port (a0,a1,a2: in std_logic;
aout:out std_logic);
end component;
component or4
port (r0,r1,r2,r3:in std_logic;
rout:out std_logic);
end component;
signal selbar0,selbar1,t1,t2,t3,t4: std_logic;
begin
INV0: inv port map (Sel0, selbar0);
INV1: inv port map (Sel1, selbar1);
A1: and3 port map (A, selbar0, selbar1, t1);
A2: and3 port map (B, Sel0, selbar1, t2);
A3: and3 port map (C, selbar0, Sel1, t2);
A4: and3 port map (D, Sel0, Sel1, t4);
O1: or4 port map (t1, t2, t3, t4, Y);
end structural;

Dataflow modeling of 4:1 mux

architecture dataflow of MUX4_1 is

signal selbar0,selbar1,t1,t2,t3,t4: std_logic;
begin
selbar0<=not sel0;
selbar1<=not sel1;
t1<=A and selbar0 and selbar1;
t2<=B and sel0 and selbar1;
t3<=C and selbar0 and sel1;
t4<=D and sel0 and sel1;
Y<= t1 or t2 or t3 or t4;
end dataflow;

VHDL Code For 4 to 1 Multiplexer

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_4to1 is
port(

A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_4to1;

architecture bhv of mux_4to1 is

begin
process (A,B,C,D,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
 Z <= A;
elsif (S0 ='1' and S1 = '0') then
Z <= B;
elsif (S0 ='0' and S1 = '1') then
Z <= C;
else
Z <= D;
end if;
end process;
end bhv;

Following is the VHDL code for a 4-to-1 1-bit MUX using an If statement.

library ieee;
use ieee.std_logic_1164.all;

entity mux is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end mux;

architecture archi of mux is

begin
process (a, b, c, d, s)
begin
if (s = "00") then o <= a;
elsif (s = "01") then o <= b;
elsif (s = "10") then o <= c;
else o <= d;
end if;
end process;
end archi;

4-to-1 MUX Using CASE Statement

The following table shows pin definitions for a 4-to-1 1-bit MUX using a
Case statement.
IO Pins Description
a, b, c, d Data Inputs
s[1:0] MUX selector
 o Data Output

library ieee;
use ieee.std_logic_1164.all;

entity mux is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end mux;

architecture archi of mux is

begin
process (a, b, c, d, s)
begin
case s is
when "00" => o <= a;
when "01" => o <= b;
when "10" => o <= c;
when others => o <= d;
end case;
end process;
end archi;

VHDL Code for 2 to 1 Mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2_1 is
port(A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC);
end mux2_1;

architecture Behavioral of mux2_1 is

begin
process (A,B,S) is
begin
if (S ='0') then
Z <= A;
else
Z <= B;
end if;
end process;
end Behavioral;

What is Verilog ?

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for

describing a digital system like a network switch or a microprocessor or a memory or a
flip−flop. It means, by using a HDL we can describe any digital hardware at any level.
Designs, which are described in HDL are independent of technology, very easy for
designing and debugging, and are normally more useful than schematics, particularly for
large circuits.
Verilog supports a design at many levels of abstraction. The major three are –

 Behavioral level
 Register-transfer level
 Gate level

Behavioural Level (Architecture / Algorithmic )

This level describes a system by concurrent algorithms (Behavioural). Every algorithm is

sequential, which means it consists of a set of instructions that are executed one by one.
Functions, tasks and blocks are the main elements.

 A behavioral representation describes how a particular design

should responds to a given set of inputs

Register−Transfer Level

Designs using the Register−Transfer Level specify the characteristics of a circuit using
operations and the transfer of data between the registers.
 A model that describes the flow of data between registers and how a design process
these data Gate Level

Gate Level (Structure)

A model that describes the logic gates and the interconnections between them.

Switch Level

A model that describes the transistors and the interconnections between them

Comments
There are two forms to represent the comments
 1) Single line comments begin with the token // and end with carriage return.
Ex.: //this is single line syntax
 2) Multiline comments begins with the token /* and end with token */
Ex.: /* this is multiline Syntax*/

Verilog HDL Program for HALF ADDER

The half adder truth table and schematic (fig-1) is mentioned below. The boolean
expressions are:
S= A (EXOR) B
C=A.B
Input-A Input-B Output-S Output-C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Half Adder Schematic

Half Adder Verilog code

module ha ( a, b, s, c)
input a, b;
output s, c;
assign s= a ^ b;
assign c= a & b;
end module

Half Substractor

The half substractor truth table and schematic (fig-2) is mentioned below. The boolean
expressions are:
D= A (EXOR) B
Br=A'.B

Input-A Input-B Output-D Output-Br

0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Half substractor Schematic

Half Substractor Verilog code

module hs ( a, b, d, br)
input a, b;
output d, br;
assign d= a ^ b;
assign br= ~a & b;
end module
Full Substractor

The full substractor truth table and schematic (fig-3) is mentioned below. The boolean
expressions are:

D= A (EXOR) B (EXOR) C
Br=A'.B + B.Cin + A'.Cin

Input-A Input-B Input-Cin Output-D Output-Br

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Full substractor Schematic

Full Substractor Verilog code (Behavioural )

module fs ( a, b, c, d, br)
input a, b, c;
output d, br;
assign d= a ^ b ^ c;
assign br=(( ~a)& (b | c)) | (b & c);
end module
Verilog HDL Program for FULL ADDER

Full Adder (Dataflow Modeling):

module full adder ( input a, input b, input cin, output sum, output carry );
assign x=a ^ b;
assign sum=x^cin;
assign y=x & cin;
assign z=a & b;
assign carry= y | z;
endmodule

Verilog Code for 2:1 and 4:1

Verilog Code
Following is the Verilog code for a 4-to-1 1-bit MUX using an If Statement.
module mux (a, b, c, d, s, o);
input a,b,c,d;
input [1:0] s;
output o;
reg o;

always @(a or b or c or d or s)
begin
if (s == 2'b00) o = a;
else if (s == 2'b01) o = b;
else if (s == 2'b10) o = c;
else o = d;
end
endmodule

Verilog Code
Following is the Verilog Code for a 4-to-1 1-bit MUX using a Case statement.
module mux (a, b, c, d, s, o);
input a,b,c,d;
input [1:0] s;
output o;
reg o;

always @(a or b or c or d or s)
begin
case (s)
2'b00 : o = a;
2'b01 : o = b;
2'b10 : o = c;
 default : o = d;
endcase
end
endmodule

Difference between VHDL & VERILOG

a) VHDL stands for vhsic hardware description language and is mainly used for
modelling a digital circuit at higher level of abstraction and it's IEEE standard is 1076–
2008
While Verilog is also a HDL (Hardware Description Language) but can be used as HVL
(Hardware Verification Language) to some extent and it's IEEE standard is 1364–2005
and its IEEE standard is 1364–2005.

b) VHDL has its origin and syntax derived from Ada programming language while
Verilog has its syntax originated from C programming language.

c) VHDL has wide range of data types like scalar,composite,access and file type which
are further classified into wide range which makes it quite verbose while Verilog has
mainly two data type like wire and reg which makes it easy to use.

d) Library declaration is there in vhdl which are not there in Verilog.

e) VHDL has 9 valued logic primarily U,X,0,1,Z,W,L,H,- and Verilog is a 4 valued logic
0,1,X,Z.

f) VHDL is case in-sensitive language while Verilog is case sensitive.

g) VHDL is typecast language while Verilog is non type cast language.( Type casting is a
way to convert a variable from one data type to another data type )

h) VHDL has mainly 5 ports like in,out,input,buffer and linkage while Verilog has only
3 ports in,out,input.

I) Procedures and functions are placed in a package so that they can be available to any
design unit that wishes to use them in case of vhdl while in case of Verilog there is no
concept of package and to make functions and tasks accessible they are placed in a
separate file and can be included using 'include compiler directive.

J) VHDL uses constants & Verilog uses parameters

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