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Ejercicio1 1

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15 views8 pages

Ejercicio1 1

Uploaded by

Alan Longoria
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EJERCICIO_1

CODIGO:

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 10:36:52 09/11/2018

-- Design Name:

-- Module Name: EJERCICIO_1 - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.


--library UNISIM;

--use UNISIM.VComponents.all;

entity EJERCICIO_1 is

Port ( A : in STD_LOGIC_VECTOR (7 downto 0);

B : in STD_LOGIC_VECTOR (7 downto 0);

OP : in STD_LOGIC_VECTOR (2 downto 0);

SALIDA : out STD_LOGIC_VECTOR (7 downto 0));

end EJERCICIO_1;

architecture Behavioral of EJERCICIO_1 is

signal SAL : STD_LOGIC_VECTOR(7 downto 0);

begin

process (OP) begin

case OP is

when "000" => SAL <=

STD_LOGIC_VECTOR (signed (A) + signed (B));

when "001" => SAL <=

STD_LOGIC_VECTOR (signed (A) - signed (B));

when "010" => SAL <=


(A AND B);

when "011" => SAL <=

(A NAND B);

when "100" => SAL <=

(A OR B);

when "101" => SAL <=

(A NOR B);

when "110" => SAL <=

(A XOR B);

when others => SAL <=

(NOT A);

end case;

end process;

SALIDA <= SAL;

end Behavioral;
SIMULACION:

--------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 12:09:31 09/11/2018

-- Design Name:

-- Module Name:
C:/Users/Priscila/Desktop/PRACTICA_3/EJERCICIO_1/EJERCICIO_1/EJERCICIO_1/ALU.vhd

-- Project Name: EJERCICIO_1

-- Target Device:

-- Tool versions:

-- Description:

--

-- VHDL Test Bench Created by ISE for module: EJERCICIO_1

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes:

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test. Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation

-- simulation model.

--------------------------------------------------------------------------------
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY ALU IS

END ALU;

ARCHITECTURE behavior OF ALU IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT EJERCICIO_1

PORT(

A : IN std_logic_vector(7 downto 0);

B : IN std_logic_vector(7 downto 0);

OP : IN std_logic_vector(2 downto 0);

SALIDA : OUT std_logic_vector(7 downto 0)

);

END COMPONENT;

--Inputs

signal A : std_logic_vector(7 downto 0) := (others => '0');

signal B : std_logic_vector(7 downto 0) := (others => '0');

signal OP : std_logic_vector(2 downto 0) := (others => '0');


--Outputs

signal SALIDA : std_logic_vector(7 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

---constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: EJERCICIO_1 PORT MAP (

A => A,

B => B,

OP => OP,

SALIDA => SALIDA

);

-- Clock process definitions

--- <clock>_process :process

--- begin

---<clock> <= '0';

---wait for <clock>_period/2;

---<clock> <= '1';

---wait for <clock>_period/2;

---end process;

-- Stimulus process

stim_proc: process
begin

-- hold reset state for 100 ns.

A <= "00000000";

B <= "00000001";

OP <= "000";

wait for 100 ns;

A <= "00000000";

B <= "00000001";

OP <= "001";

wait for 100 ns;

A <= "00000000";

B <= "00000001";

OP <= "010";

wait for 100 ns;

A <= "00000000";

B <= "00000001";

OP <= "011";

wait for 100 ns;

A <= "00000000";

B <= "00000001";

OP <= "100";

wait for 100 ns;


A <= "00000000";

B <= "00000001";

OP <= "101";

wait for 100 ns;

A <= "00000000";

B <= "00000001";

OP <= "110";

wait for 100 ns;

A <= "00000000";

B <= "00000001";

OP <= "OTHERS";

wait for 100 ns;

-- wait for <clock>_period*10;

-- insert stimulus here

wait;

end process;

END;

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