UNIVERSITY OF THE WITWATERSRAND, JOHANNESBURG

ELEN2021 : Microprocessors
Digital Logic and Design

Chabalala Chabalala
2021
ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Digital Design Principles

Sections: 1.6 and 1.8

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

In the previous lecture …

• Binary logic,

• Digital abstraction,

• Logic gates and operations, and

• Logic levels.

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Summary of points from the previous lecture…

• In binary logic, we need discrete voltage levels to represent

1’s (HIGH) and 0’s (LOW).

• Due to noise and unpredictable voltage drops in circuit

elements, we cannot use exact voltages.

• Therefore we need a robust design methodology to deal with

the unpredictable noise voltage drops.

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

In this lecture …

• Noise

• Logic Levels,

• Noise Margin,

• DC Transfer Characteristics, and

• Power Consumption.

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

What is noise in digital circuits?

The gate (driver) outputs 5 V but, because of resistance in
a long wire, the receiver gets 4.5 V.

Noise
Driver Receiver

5V 4.5 V

• Anything that degrades the signal.

– For example: resistance, power supply voltage drops, magnetic and
electrical coupling to neighboring wires, RF interference, etc.

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Logic levels
• Digital circuits must be designed to be robust against noise.
• Define a range of voltage levels to represent 1’s and 0’s.
• Define different ranges between input and output voltage levels! WHY???

Driver Receiver
Output → Input → IN
OUT

Output Characteristics Input Characteristics

VDD
Logic High
Output Range Logic High
VO H Input Range
NMH
Forbidden VIH
Zone VIL
VO L NML
Logic Low
Logic Low Input Range
Output Range
GND
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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Noise Margin
• The amount of noise that could be added to a worst-case output such that
the signal is still be interpreted as a valid input.

Output Characteristics Input Characteristics

VDD
Logic High
Output Range Logic High
VO H Input Range
NMH
Forbidden VIH
Zone VIL
VO L NML
Logic Low
Logic Low Input Range
Output Range
GND

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Noise Margin
• The amount of noise that could be added to a worst-case output such that
the signal is still be interpreted as a valid input.

Output Characteristics Input Characteristics

VDD
Logic High
Output Range Logic High
VO H Input Range
NMH
Forbidden VIH
Zone VIL
VO L NML
Logic Low
Logic Low Input Range
Output Range
GND

High Noise Margin: NMH = VOH – VIH

Low Noise Margin: NML = VIL – VOL
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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Noise Margin
Example 2.1:
Consider the inverter circuit below with the following characteristics: VDD = 5 V,
VIL = 1.35 V, VIH = 3.15 V, VOL = 0.33 V and VOH = 3.84 V. What are the noise
margins? Can the circuit tolerate 1 V of noise?
Noise
Driver Receiver
V1 V2
1 2
5V 4.5 V
Solution:
• For logic LOW: NML = VIL – VOL = (1.35 V – 0.33 V) = 1.02 V
• For logic HIGH: NMH = VOH – VIH = (3.84 V – 3.15 V) = 0.69 V
• The circuit can tolerate 1 V of noise when the output is LOW (NML = 1.02 V), 
BUT not when the output is HIGH (NMH = 0.69 V). 
• Example: For the worst case HIGH: VOH = 3.84 V, if noise drops the voltage by 1 V, then
the input at the receiver becomes: V2 = (3.84 – 1V) = 2.84 V. This is less than acceptable
input HIGH value VIH = 3.15 V (i.e. V2 < VIH).

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

DC Transfer Characteristics
(a) Ideal Buffer: (b) Real Buffer:
V(Y) V(Y)
A Y

VOH VDD VDD

VOH

Unity Gain
Points
VOL Slope = 1

VOL 0 V(A) V(A)

0
VDD / 2 VDD VIL VIH VDD
VIL, VIH

NMH = NML = VDD/2 NMH, NML < VDD/2

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

DC Transfer Characteristics

A Y

(a) Transfer Characteristics Plot (b) Real Buffer:

V(Y)
Output Characteristics Input Characteristics
VDD VDD
VOH
VO H
NMH
Forbidden VIH
Zone VIL

Unity Gain NML

Points
VOL Slope = 1
VO L
V(A)
0
VIL VIH VDD GND

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

DC Transfer Characteristics
Ideal Inverter: Real Inverter:

NMH = NML = VDD/2 NMH, NML < VDD/2

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

DC Transfer Characteristics

VDD

GND

Source: Introduction to Digital Systems Laboratory - MIT

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Supply Voltage (VDD) Scaling

• In 1970’s and 1980’s, VDD = 5 V

• VDD has dropped

– Avoid frying tiny transistors

– Save power

• 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …

– Be careful connecting chips with different supply voltages

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Supply Voltage (VDD) Scaling

• In 1970’s and 1980’s, VDD = 5 V

• VDD has dropped

– Avoid frying tiny transistors

– Save power

• 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …

– Be careful connecting chips with different supply voltages

Chips operate because they contain magic smoke.

Proof: if the magic smoke is let out, the chip stops working
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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Logic Family Examples TTL: Transistor-Transistor Logic,

CMOS: Complementary Metal-Oxide-Semiconductor Logic
LVTTL: Low Voltage Transistor-Transistor Logic,
LVCMOS: Low Voltage Complementary Metal-Oxide-Semiconductor Logic

Logic Family VDD VIL VIH VOL VOH

TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4

CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84

LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4

LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7

• NOTE: Be careful about connecting different logic families. As an exercise find

out which of these logic families can be directly connected.

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Power consumption

• Energy: Electronic circuits

require energy to operate.

• Power = Energy consumed per unit time.

• Types: Static Power and Dynamic Power.

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Dynamic Power

• Power to charge transistor gate capacitances

– Charging and discharging of capacitors as signals switch between 1’s and 0’s
– Energy required to charge capacitance C, to VDD is CVDD2
– Circuit running at frequency f: transistors switch (from 1 to 0 or vice versa).
– Capacitor is charged f/2 times per second (discharging from 1 to 0 is free).

• Dynamic power consumption is therefore based on energy the

required to charge a capacitor:

Pdynamic = ½CVDD2f

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Static Power

• This is the power consumed when gates are not

switching, i.e. idle power consumption.

• Caused by the quiescent supply current, IDD (also

called the leakage current)

• Static power = (Quiescent supply current)

x (Supply voltage)

Pstatic = IDD x VDD

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Power Consumption
Example 2.2
• Estimate the power consumption of a mobile phone of a student who is playing a
game with the following characteristics:
– VDD = 0.8 V
– C = 5 nF
– f = 2 GHz
– IDD = 10 mA

Solution: Dynamic Static

Power = ½CVDD2f + IDDVDD

= ½(5 nF)(0.8 V)2(2 GHz) + (10 mA)(0.8 V)

= (3.2 + 0.008) W ≈ 3.2 W

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Power Consumption
Exercise 2.1

• Suppose a cellphone has a 6 watt-hour (W-hr) battery and operates at 1.2 V. When
it is in use, it operates at 300MHz and the average amount of capacitance in the
chip switching at any given time is 10 nF (10−8 Farads). When is use, it broadcasts 3
W of power out of its antenna. When not in use, the dynamic power drops to
almost zero because the signal processing is turned off. But the phone also draws 40
mA of quiescent current whether it is in use or not.

Determine the battery life of the phone

(a) if not in use and, (ANS: 152 hours)
(b) if continuously in use. (ANS: 1.15 hours)

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Summary
• Noise affects the operation of digital circuits, but noise
margin allows for reliable operation.

• Power consumption depends on static (constant) power

and dynamic (switching) power.

• Dynamic power depends on switching frequency, the

faster the switching, the more the power.

• Logic families are well defined and must be well

understood to build digital circuits.

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Next Lecture: Thursday 08 April 2021 @ 12h30

• Boolean Algebra:

[ Remember: Test 1 on Tuesday 05 April 2021 @ 14h15 ]

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ELEN2021 : Microprocessors
Digital Logic and Design
Introduction to Digital Logic

Thank you!

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