Group Members

• Shermeen Tajammal [FA17-BEE-025]

• Adeela Bashir [FA17-BEE-064]
• Sana Nasir [FA17-BEE-091]
Abstract
A digital clock system designed by using VHDL hardware description language is presented in
this paper. The proposed architecture fully utilizes the digital clock system available on FPGA
chips based top-down design method in the Quartus II development environment. The Clock
system is divided into four design modules: core module, frequency division module, and display
module. It not only can set time accurately and display time, but also can reset and adjust time.
The LED lights will flash will tell time. The architecture is implemented and verified
experimentally on a FPGA board. Because of the universality of digital clock and the portability
of VHDL language, it can be applied directly in various designs based on FPGA chip.
1. Introduction
EDA technology is the development direction of modem electronic design. Through programming
the large-scale programmable logic devices, it can design electronic products which have higher
performance, smaller size and less gown. FPGA is the English abbreviation for Field
Programmable Gate Array. It is a programable logic device with high density. Using FPGA and
the software of Quartus II [1]. electronic products with higher performance can be designed easily
in less time. Digital clock can be achieved by a variety of technology, such as discrete digital
devices or, single-chip computer, however. programmable Logic devices have many
characteristics that other methods don't have, such as smaller size, higher capacity. more I/O ports
and easy programming, etc. In this paper field programmable gate array (FPGA) devices as the
core to achieve the digital clock. Quartus II is for the development environment and VHDL is for
the design language [2]. Finally, the code is downloaded in FPGA to form the circuit to simulate
and verify experiment.

2. Objective
The main objective of the digital clock is to display the time digitally using 7-segment display on
FPGA Board The digital clock by default displays the run time and time can be set by using time
set assigned to switch on board. It displays the time in format of hours: minutes: seconds.

3. Objective Completed
Displaying the run time on 7-segment display and reset the time by pressing the reset key. To
display the time in format of hours: minutes: seconds.

4. Methodology
1. Design of code and Addition of Constrains: Design the system and derive the HDL (Hardware
description Language) file. To specify certain implementation constraints, we may need to add a
separate constraint file like XDC file.
2. Development of Testbench code for simulation: develop the testbench in HDL and perform RTL
simulation. The RTL term proves the fact that HDL code is done at the register transfer level.
3. Synthesis and Implementation: the synthesis process also known as logic synthesis in which the
software transforms the HDL constructs to generic gate-level components, such as simple logic
gates and flip flops. The implementation process includes translation, mapping, placing and
routing. The translate process merges multiple files into single netlist. The map process maps the
generic gates in the netlist to FPGA’s logic cells and 10BS. The place and route process derives
the physical layout inside the FPGA chip. It places the cell in various physical location and
determines the routes to connect various signals accordingly [3].
4. Generation of Bit stream and configuration of the file: in this procedure, an arrangement record
is created by the last netlist. This document is then downloaded to a FPGA gadget serially to design
the switches and rationale cells. The discretionary useful reproduction can be performed after
union, and the discretionary planning recreation can be performed after usage. To supplant the
RTL depiction and check the accuracy of the combination handle, utilitarian reenactment utilizes
an integrated netlist. Timing recreation utilizes the last netlist, alongside nitty gritty planning
information, to perform reproduction. Practical and timing recreation may require a huge sum of
time. After coding and great outline, the HDL code will be integrated and executed effectively [4].
5. FSM

6. VHDL Code

-- BCD to HEX For 7-segment LEDs display

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bin2hex is
port (
Bin: in std_logic_vector(3 downto 0);
Hout: out std_logic_vector(6 downto 0)
);
end bin2hex;
architecture Behavioral of bin2hex is
begin
process(Bin)
begin
case(Bin) is
when "0000" => Hout <= "1000000"; --0--
when "0001" => Hout <= "1111001"; --1--
when "0010" => Hout <= "0100100"; --2--
when "0011" => Hout <= "0110000"; --3--
when "0100" => Hout <= "0011001"; --4--
when "0101" => Hout <= "0010010"; --5--
when "0110" => Hout <= "0000010"; --6--
when "0111" => Hout <= "1111000"; --7--
when "1000" => Hout <= "0000000"; --8--
when "1001" => Hout <= "0010000"; --9--
when "1010" => Hout <= "0001000"; --a--
when "1011" => Hout <= "0000011"; --b--
when "1100" => Hout <= "1000110"; --c--
when "1101" => Hout <= "0100001"; --d--
when "1110" => Hout <= "0000110"; --e--
when others => Hout <= "0001110";
end case;
end process;
end Behavioral;
================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_digital_clock IS
END tb_digital_clock;
ARCHITECTURE behavior OF tb_digital_clock IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT digital_clock
PORT(
clk : IN std_logic;
rst_n : IN std_logic;
H_in1 : IN std_logic_vector(1 downto 0);
H_in0 : IN std_logic_vector(3 downto 0);
M_in1 : IN std_logic_vector(3 downto 0);
M_in0 : IN std_logic_vector(3 downto 0);
H_out1 : OUT std_logic_vector(6 downto 0);
H_out0 : OUT std_logic_vector(6 downto 0);
M_out1 : OUT std_logic_vector(6 downto 0);
M_out0 : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
================================================================
--Inputs
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal H_in1 : std_logic_vector(1 downto 0) := (others => '0');
signal H_in0 : std_logic_vector(3 downto 0) := (others => '0');
signal M_in1 : std_logic_vector(3 downto 0) := (others => '0');
signal M_in0 : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal H_out1 : std_logic_vector(6 downto 0);
signal H_out0 : std_logic_vector(6 downto 0);
signal M_out1 : std_logic_vector(6 downto 0);
signal M_out0 : std_logic_vector(6 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: digital_clock PORT MAP (
clk => clk,
rst_n => rst_n,
H_in1 => H_in1,
H_in0 => H_in0,
M_in1 => M_in1,
M_in0 => M_in0,
H_out1 => H_out1,
H_out0 => H_out0,
M_out1 => M_out1,
M_out0 => M_out0
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst_n <= '0';
H_in1 <= "01";
H_in0 <= x"0";
M_in1 <= x"2";
M_in0 <= x"0";
wait for 100 ns;
rst_n <= '1';
wait for clk_period*10;
wait;
end process;
END;
================================================================
-- Clock divider module to get 1 second clock
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clk_div is
port (
clk_50: in std_logic;
clk_1s: out std_logic
);
end clk_div;
architecture Behavioral of clk_div is
signal counter: std_logic_vector(27 downto 0):=(others =>'0');
begin
process(clk_50)
begin
if(rising_edge(clk_50)) then
counter <= counter + x"0000001";
if(counter>=x"2FAF080") then -- for running on FPGA -- comment
when running simulation
--if(counter_slow>=x"0000001") then -- for running simulation --
comment when running on FPGA
counter <= x"0000000";
end if;
end if;
end process;
clk_1s <= '0' when counter < x"17D7840" else '1';
end Behavioral;
================================================================
-- BCD to HEX For 7-segment LEDs display
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bin2hex is
port (
Bin: in std_logic_vector(3 downto 0);
Hout: out std_logic_vector(6 downto 0)
);
end bin2hex;
architecture Behavioral of bin2hex is
begin
process(Bin)
begin
case(Bin) is
when "0000" => Hout <= "1000000"; --0--
when "0001" => Hout <= "1111001"; --1--
when "0010" => Hout <= "0100100"; --2--
when "0011" => Hout <= "0110000"; --3--
when "0100" => Hout <= "0011001"; --4--
when "0101" => Hout <= "0010010"; --5--
when "0110" => Hout <= "0000010"; --6--
when "0111" => Hout <= "1111000"; --7--
when "1000" => Hout <= "0000000"; --8--
when "1001" => Hout <= "0010000"; --9--
when "1010" => Hout <= "0001000"; --a--
when "1011" => Hout <= "0000011"; --b--
when "1100" => Hout <= "1000110"; --c--
when "1101" => Hout <= "0100001"; --d--
when "1110" => Hout <= "0000110"; --e--
when others => Hout <= "0001110";
end case;
end process;
end Behavioral;

7. Vector Waveform
8. RTL Viewer

Explanation:
We can see from the RTL diagram there are 15 d-flipflops, 22 Muxes and 5 adders, 2 binary-to-hexa
converters and 3 comparators.

9. Contribution:
Shermeen Tajammal-FA17-BEE-025: Contributed to documentation and implementation and execution
of the VHDL code.
Adeela bashir-FA17-BEE-064: Created the FSM and helped in documentation and coding.
SANA NASIR- FA17-BEE-091: Helped in documentation Implemented the VHDL code.

8. References
[1] B. HOLDSWORTH, Programmable logic devices, 2002.

[2] Kumar MS, Inthiyaz S, Mounica J, Bhavani M, Adidela CN, Endreddy B. FPGA implementation by
using XBee Transceiver. Indian Journal of Science and Technology. 2016 May; 9(1):1–6. DOI:
10.17485/ijst/2016/v9i17/93032.
[3] Navamani JD, Vijayakumar K, Lavanya A. FPGA-based digitally controlled Isolated Full-Bridge DC-
DC Converter with Voltage Doubler (IFBVD). Indian Journal of Science and Technology. 2016 Apr;
9(16):1–7. DOI: 10.17485/ijst/2016/v9i16/76672.

[4] Huda S, Anderson J, Tamura H. Optimizing effective interconnect capacitance for FPGA power
reduction. Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable
Gate Arrays, ACM; 2014.