COA Assignment

Ques 1] Describe the principles of magnetic disk.

Solution1] All magnetic storage devices read and write data by using electromagnetism. This basic
principle of physics states that as a electric current flows through a conductor (wire), a magnetic field is
generated around the conductor. When applied to magnetic storage devices, this two-way operation of
electromagnetism makes it possible to record data on a disk and read that data back later. When
recording, the head changes electrical impulses to magnetic fields, and when reading, the head changes
magnetic fields back into electrical impulses. Magnetic disk contains a circular disc made of metal or
plastic. Both side of the disc is usually used for storing data. The disc is coated by magnetic oxide. The
disc is divided into multiple concentric circles known as tracks, which are further divided into small area
known as sectors. Data is stored in sectors.

Ques 2] With a block diagram, explain the direct and set associative mapping between cache
and main memory.
Solution 2]
Direct mapping -In direct mapping, A particular block of main memory can map only to a
particular line of the cache. This is explained by taking a specific example Consider a cache
consisting of 128 blocks of 16 words for a total of 2048 words and assume that the main
memory is 64K words Both main memory and cache memory is divided into blocks of size
equal to 16 words  Here block j of main memory maps to (block j mod 128) of cache.  Main
memory blocks 0, 128, 256 … loaded into cache block 0  Main memory blocks 1, 129, 257 …
loaded into cache block 1 and so on  Placement of a block in the cache is determined from
memory address  Memory address is divided into three fields as shown in figure  Lower order
4 bit select one of 16 words within a block  Next 7 bits select cache block  Next 5 bit decides
block from which segment is mapped to cache.  During processing higher order 5 bits are
compared with tag bits of cache block pointed by 7 bit cache block field If match – desired word
is in the block – Cache Hit, If not – desired word is brought from main memory and loaded to
cache – Cache Miss
Set associative mapping -This mapping is the combination of direct mapping and associative mapping
technique. The same cache size 2K words organized into two blocks per set. Block j of main block is
mapped into (j mod 64) of cache block - memory blocks 0, 64, 128 … mapped to cache set 0 and they
can occupy either of two blocks position within the set - memory blocks 1, 65, 129 … mapped to cache
set 1 and so on During operation 6 bit set field give the set which contain the data and 6 bit Tag of
address is associatively compared to the tags of the two blocks of the set to check the desired data is in
cache.
Ques 3] Draw a diagram and explain the working of 16 megabits DRAM chip configured as
2M×8. Also explain as at how it can be made to work in fast page mode.
Solution 3] The 4bit cells in each row are divided into 512 groups of 8. 21bit address is needed to access
a byte in the memory (12 bit to select a row, and 9 bits specify the group of 8 bits in the selected row). A
(0-8) → Row address of a byte. A (9-20) → Column address of a byte. During Read/ Write operation, the
row address is applied first. It is loaded into the row address latch in response to a signal pulse on Row
Address Strobe (RAS) input of the chip. When a Read operation is initiated, all cells on the selected row
are read and refreshed. Shortly after the row address is loaded, the column address is applied to the
address pins and loaded into Column Address Strobe (CAS). The information in this latch is decoded and
the appropriate group of 8 Sense/Write circuits is selected. R/W =1(read the output values of the
selected circuits are transferred to the data lines D0 - D7. R/W=0 (write operation). The information on
D0 - D7 is transferred to the selected circuits. RAS and CAS are active low so that they cause the latching
of address when they change from high to low. This is because they are indicated by RAS and CAS. To
ensure that the contents of a DRAM‘s are maintained, each row of cells must be accessed periodically.

Internal Organization of 2M X 8 Dynamic Memory Chip

– Total number of cells = 16M

- The cells are organized in = 4K X 4K array

- The number of row = 4K

- The number of cells in a row = 4K

- The number of address bits to select a row = 12

- The number of address bits to select a byte in a row = 9

- Total address bits = 21 - A9 – 20 (12)– to select a row - A0 – 8 (09) – to select a byte in a row of 4096
bits
Fast Page Mode: Transferring the bytes in sequential order is achieved by applying the consecutive
sequence of column address under the control of successive CAS signals. This scheme allows transferring
a block of data at a faster rate. The block of transfer capability is called as Fast Page Mode.

Ques 4] Briefly explain any 4 non-volatile memory concepts.

Solution 4] Non-volatile memory (NVM) is a type of memory that retains stored data after the power is
turned off. Examples of non-volatile memory include flash memory, read-only
memory (ROM), ferroelectric RAM, most types of magnetic computer storage devices (e.g. hard disk
drives, floppy disks, and magnetic tape), optical discs, and early computer storage methods such
as paper tape and punched cards.

1. Magnetic Disks
A magnetic disk is a circular plate constructed of metal or plastic coated with magnetized material. All
disks rotate together at high speed and are not stopped or started for access purposes. Bits are stored in
the magnetized surface in spots along concentric circles called tracks.

2. Magnetic Tape
A magnetic tape transport consists of the electrical, mechanical, and electronic components to provide
the parts and control mechanism for a magnetic-tape unit.
3. HARD DISK DRIVE (HDD)
The hard drive is what stores all your data. It houses the hard disk, where all your files and folders are
physically located. These disks spin extremely fast (typically at either 5400 or 7200 RPM) so that data
can be accessed immediately from anywhere on the drive. The data is stored on the hard drive
magnetically, so it stays on the drive even after the power supply is turned off.
4. Flash Drive
A flash drive is a small, ultra-portable storage device which, unlike an optical drive or a traditional hard
drive, has no moving parts. Flash drives are often referred to as pen drives, thumb drives, or jump
drives. The terms USB drive and solid-state drive (SSD) are also sometimes used but most of the time
those refer to larger, not-so-mobile USB-based storage devices like external hard drives.

Ques 5] With a neat diagram explain translation of a virtual address to a physical address .
Solution 5] The translation from the logical to the physical address is done by special hardware unit in
the CPU that is called the Memory Management Unit (MMU), in some systems it is also called as address
translator unit.

Virtual Memory space is divided into equal size pages. Main Memory space is divided into equal size
page frames each frame can hold any page from Virtual Memory. When CPU wants to access page, it
first looks into main memory. If it is found in main memory then it is called Hit and page is transfer from
main memory to CPU. If CPU needs page that is not present in main memory then it is called as page
fault. The page has to be loaded from Virtual Memory to main memory.
During page replacement, it the old page has been modified in the main memory, then it needs to be
first copied into the Virtual Memory and then replaced. CPU keeps track of such updated pages by
maintaining Dirty bit for each page. When page is updated in main memory dirty bit is set then this dirty
page first copied into Virtual Memory & then replaced. Pages are loaded into main memory only when
required by the CPU, then it is called demand paging. Thus, pages are loaded only after page faults.
Ques 6] Discuss in detail any one feature of memory design that leads to improved
performance of computer.

Solution6] In the Computer System Design, Memory Hierarchy is an enhancement to organize the
memory such that it can minimize the access time. Earlier when the computer system was designed
without Memory Hierarchy design, the speed gap increases between the CPU registers and Main
Memory due to large difference in access time. This results in lower performance of the system and
thus, enhancement was required. This enhancement was made in the form of Memory Hierarchy Design
because of which the performance of the system increases.

One feature of memory hierarchy design that lead to improved performance of computer is:.
 Access time

The access time in the memory hierarchy is the interval of the time among the data availability
as well as request to read or write. Because whenever we shift from top to bottom inside the
memory hierarchy, then the access time will increase. The total memory capacity of a computer
can be visualized by hierarchy of components. The memory hierarchy system consists of all
storage devices contained in a computer system from the slow Auxiliary Memory to fast Main
Memory and to smaller Cache memory. Auxillary memory access time is generally 1000
times that of the main memory, hence it is at the bottom of the hierarchy. So the access time
increases from top to bottom is memory hierarchy.

Ques 7] Draw for 1K×1 memory chip with neat figure .

Ques 8] Show with diagram the memory hierarchy with respect to speed, size and cost.
Solution 8]

Ques 9] Explain direct memory mapping technique.

Solution 9] In direct mapping, A particular block of main memory can map to only one particular
line of the cache. The following steps explain the working of direct mapped cache-
After CPU generates a memory request,

 The line number field of the address is used to access the particular line of the cache.
 The tag field of the CPU address is then compared with the tag of the line.
 If the two tags match, a cache hit occurs and the desired word is found in the cache.
 If the two tags do not match, a cache miss occurs.
 In case of a cache miss, the required word has to be brought from the main memory.
 It is then stored in the cache together with the new tag replacing the previous one.

Ques 10] Explain the working of 16-megabyte DRAM chip configured as 1M×6 memory chip.
Solution 10]

 A 16Mbit chip can be organised as 1M of 16 bit words

 A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on
 A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array
 4 bits are read and written at a time.
 Memory array is organized as 4 square arrays of 2048 x 2048 elements.
 Elements are connected by both horizontal (rows) and vertical (columns) lines.
 Each horizontal line connects to the Select terminal of each cell in its row.
 Each vertical line connects to the data in/sense terminal of each cell in its column.
 Address lines supply the address of the word to be selected.
 11 lines are needed to select one of 2048 rows.
 These lines are fed into a row decoder, which has 11 lines of input and 2048 lines for output.
 Similarly, additional 11 address lines select one of 2048 columns of 4 bits per column.
 Four data lines are used for the input and output of 4 bits to and from a data buffer.
 Data input buffer (4 bits) – data to be written
 Data output buffer (4 bits) – data to be sensed/read.
 Only 4 bits read/write🡪 must be multiple DRAM connected to the memory controller to
read/write a word of data to the bus.
 Only 11 address lines (A0-A10) used instead of 22 required address lines.
 First 11 address signals –row address.
 Other 11 address signals – column address.
 Timing and control signals
 RAS – row address select
 CAS – column address select
 WE – Write Enable (Write operation)
 OE - Output Enable (Read Operation)
 All DRAMs require refresh operation
 Refresh circuit included on chip
 Disable chip – while the data cells refreshed
 Count through rows
 Read & Write back into the same location.
 Takes time
 Slows down apparent performance