1. Write the general definition of MODULATION.

Define Amplitude, Frequency

and Phase modulation (A.M, F.M and P.M).

2. Define modulation index in relation to peak amplitudes of carrier and message

signals.

3. As related to AM, what is over modulation, under modulation and 100%

modulation?

4. Find the value of modulation index value if the peak amplitudes of carrier and
message are 5v and 3v.

5. A 1 MHz carrier is amplitude modulated by an audio signal which contains all

frequencies in the range 300 Hz to 5 kHz. What are the frequency bands which are
output? What is the output bandwidth?

6. A 1.5 MHz carrier is amplitude modulated by three sinusoidal signals of

frequency 500 Hz, 800 Hz and 1,400 Hz. What are the frequencies in the AM
spectrum?

7. An AM signal is represented by the equation

v= ( 15 + 3 Sin( 2 * 5 * 103 t) ) * Sin( 2 * 0.5 * 106 t) volts

(i) What are the values of the carrier and modulating frequencies?
(ii) What is the modulation index?
(iii) What is the bandwidth?
8. Identify the circuit shown below. If an Amplitude modulated wave is applied to
this circuit, then what are the three components in the output waveform?

9. Draw the output waveforms of the above circuit at points 1 and 2.

10. What are the limitations of diode detector?

 Answers

1. Modulation: It is the process of changing or altering the characteristics or

properties of a high frequency carrier signal in accordance with the characteristics
of the low frequency message signal.

Amplitude modulation (AM): It is the process of altering the amplitude of the high
frequency carrier signal in accordance with the amplitude of low frequency
message signal.

Frequency modulation (FM): It is the process of altering the frequency of the high
frequency carrier signal in accordance with the frequency of low frequency
message signal.

Phase modulation (PM): It is the process of altering the phase of the high
frequency carrier signal in accordance with the phase of low frequency message
signal.

2. Modulation Index: It is the ratio of peak amplitude of message and carrier

signal. It is expressed as,
peak amplitude of message signal Em
Modulation Index, m = peak amplitude of carrier signal = E
c

3. Over modulation: It occurs when the modulation index is greater than unity, that
is if m>1 which means that the peak amplitude of the message signal is more than
that of the carrier signal.

Under modulation: It occurs when the modulation index is less than unity, that is if
m<1 which means that the peak amplitude of the message signal is less than that of
the carrier signal.

100% modulation: It occurs when the modulation index is unity, that is if m=1
which means that the peak amplitude of the message signal equals that of the
carrier signal.

4. Given, Em = 3V and Ec = 5V
 Em 3
Modulation index, m = E = 5 = 0.6.
c

5. Answer: The carrier is 1 MHz

The Upper Side Band is all frequencies in the range 1,000,300 to 1,005,000 Hz

The Lower Side Band is all frequencies in the range 995,000 to 999, 700 Hz

The Bandwidth is 1,005,000 - 995,000 = 10,000 Hz = 10 kHz.

6. Answer: Convert all the frequencies to kHz. 1.5 MHz is 1500 kHz. 500 Hz is
0.5 kHz. 800 Hz is 0.800 kHz. 1400 Hz is 1.4 kHz.

The output frequencies are:

1500 kHz, 1500  0.5 kHz, 1500  0.8 kHz 1500  1.4 kHz

or

1500, 1500.5 , 1499.5, 1500.8, 1499.2, 1501.4 , 1498.6 kHz

7. Answer:

c (= 2 fc) = 2 * 0.5 * 106

m (= 2 fm) = 2 * 5 * 103

Vc =15 V

Vm =3 V

(i) Therefore the carrier frequency, fc is 0.5 * 106 = 0.5 MHz

and the modulating frequency , fm is 5 * 103 = 5 kHz

(ii) The modulation index is, m = Vm/Vc = 3/15 = 0.2

(iii) The bandwidth BW = 2 fm = 10 kHz

8. Answer:
1. The wanted demodulated message or audio signal
2. A DC component proportional to the peak amplitude of the RF signal. This is
removed by sending the signal through a capacitor C2 (high pass filter). It is also
used to provide an input into Automatic Gain Control.
3. An unwanted ripple at the carrier frequency and its harmonics. This is blocked
from later stages by using an RC low pass filter (R2 and C3 in this circuit)

9. Answer: the output waveform at point 1 (which is the output of the rectifier) and
at point 2 (which is the output of the detector output) are as shown below,

at point 1 at point 2

10. Answer:
If the time constant R1 *C1 in the envelope detector is too long relative to the
period of the highest frequency modulating signal it will not be able to follow the
peaks and troughs of the envelope giving rise to diagonal clipping. It is required
that R1*C1 < [(1 -m2)1/2] / (mm) where m is the highest frequency component of
the modulating signal and m is the modulation index. This is derived below.
 If R1*C1 is too short than there will excessive RF ripple and the output power
will be reduced.
 Because the diode is a non linear device there will be some distortion in the
demodulated signal.
Work sheet on oscillators and wave shaping circuits
1. The Wien bridge oscillator uses two capacitors (C 1and C2) of 0.001μF of each and two
resistors of R1 = 10kΩ while R2 is kept variable. The frequency is to be varied from 10 kHz to 50
kHz, by varying R2 . Find the minimum and maximum values of R2 .
2. Design a Wien bridge oscillator circuit as shown in the Figure 1. To oscillate at a frequency of
2 kHz. Choose appropriate values of the components.

Figure1.
3. Design a Schmitt trigger circuit for the photo detector switch circuit with the configuration
shown in Figure-2 is to be designed such that the switching voltage is VS = 2 V and the
hysteresis width is 0.5 V. Assume VH = 10 V and VL = −5 V. Assume R1 = 10kΩ.
4. For Fig3, what should be the value of RA, if the value of C = 0.01 μF. Consider the frequency
of the trigger signal to be 2 kHz. The circuit of Fig. 3 is for divide by 2. The tp should be
slightly greater than T. Let tp = 1.2T i.e. 20% extra to T.

Figure 3. Monostable multivibrator

5. In Fig. 4 RA = 2.2 K, RB = 3.9 K and C = 0.1 μF. Find out the pulse width of positive and
negative pulses. Also calculate the free running frequency
 Figure 4. Astable multivibrator

6. Calculate the frequency and duty cycle of the 555 astable multivibrator output for C =
0.01 μF, RA = 2.2 kΩ., RB =100 kΩ.

7. Calculate the values of R and C for Monostable operation of the IC555 timer with VCC = 12 V
and pulse width of 20 ms. Also find out the minimum threshold voltage required that would
produce the output pulse. How much will be the value of the capacitor? At what instant of time
the falling edge of the output starts?

8. What would be the duration of the pulse for Monostable operation of IC555 timer with R = 1
MΩ and C = 470 μF?

9. If an IC555 timer is used to generate a ramp voltage with constant collector current of 1
mA, VCC = 15 V, and C = 0.1 μF, what would be the slope of the ramp voltage generated?
Calculate the charging and discharging voltages. What is the duration of the ramp?
 Solutions:
1. The Wien bridge oscillator uses two capacitors (C 1and C2) of 0.001μF of each and two
resistors of R1 = 10kΩ while R2 is kept variable. The frequency is to be varied from 10 kHz to 50
kHz, by varying R2 . Find the minimum and maximum values of R2 .

Solution:

1
The frequency of Wien bridge oscillator is given by f =
2 π √ R 1∗R 2∗C 1∗C 2

For f = 10 kHz, 10*103 = 1/¿ → R2 = 25.33 kΩ

For f = 50 kHz, 10*103 = 1/¿ → R2 = 1.013 kΩ

So minimum value of R2 is 1.013 kΩ while the maximum value of R2 is 25.33 kΩ

2. Design a Wien bridge oscillator circuit as shown in the Figure 1. To oscillate at a frequency of
100 kHz. Choose appropriate values of the components.

Figure 1.

Solution: The frequency of oscillations is given by the Equation:

1 1 1
f o= RC = = =0.7961 x 10−6 or 796.1 x 10−9
2 πRC ⇒ 2 π f o 2 πx 100 x 103

Approximately an 8 kΩ resistor and 0.1 nF capacitor satisfy this requirement. Since the amplifier
resistor ratio must be R2/R1 = 2, we could, for example, have R2 = 20 kΩ and R1 = 10 kΩ which
would satisfy the requirement.

3. Design a Schmitt trigger circuit for the photo detector switch circuit with the configuration
shown in Figure-2 is to be designed such that the switching voltage is VS = 2 V and the
hysteresis width is 0.5 V. Assume VH = 10 V and VL = −5 V. Assume R1 = 10kΩ.
Solution:
The Schmitt trigger circuit is the Non-inverting type.
The higher cross over voltage is given by,
VTH = -( R1 / R2) VL = -( R1 / R2) (-5) = 5( R1 / R2)

The higher cross over voltage is given by,

VTL = -( R1 / R2) VH = -( R1 / R2) (10) = -10( R1 / R2)

The hysteresis width is given by

VTH - VTL = 5( R1 / R2) + 10( R1 / R2) or

0.5 = 15 ( R1 / R2) → R1 / R2 = 1/30 or R2 / R1 = 30

And given R1 = 10 kΩ then R2 = 300 kΩ

4. For Fig3, what should be the value of RA, if the value of C = 0.01 μF. Consider the frequency
of the trigger signal to be 2 kHz. The circuit of Fig. 3 is for divide by 2. The tp should be slightly
greater than T. Let tp = 1.2T i.e. 20% extra to T.

Solution:

The output pulse width (tp) = 1.2 T, where T is the total time = 1/f

Therefore, tp = 1.2/(2∗10¿¿ 3)¿ = 0.6 ms.

And the tp in terms of capacitor and resistor is given by, tp = 1.1 RC = 1.1* RA *0.01*10−6

Therefore RA = 54.5 kΩ

5. In Fig. 4 RA = 2.2 K, RB = 3.9 K and C = 0.1 μF. Find out the pulse width of positive and
negative pulses. Also calculate the free running frequency

.
 Figure 4. Astable multivibrator

Solution:

Charging time, Tc = T 1=0.693 ( R A + R B ) C1 =¿ 0.693 x 10−7 ( 6.1 k ) = 0.423 ms

Discharge time,Td = T2 = 0.693 ( R B ) C 1 = 0.693 x 10−7 ( 3.9 k ) = 0.2703 ms

1
Hence, the free running frequency, f = = 1.45 kHz
T 1 +T 2

6. Calculate the frequency and duty cycle of the 555 astable multivibrator output for C = 0.01 μF,
RA = 2.2 kΩ., RB =100 kΩ.

Solutin: T 1=0.693 ( R A + R B ) C1 =¿ 0.693 x (0.001) 10−6 ( 102.2 k ) = 70.7μs

T 2=0.693 ( RB ) C 1=¿ 0.693 x (0.001) 10−6 ( 100 k ) = 69.3μs

T = T 1 + T 2 = 140 μs and f = 1/140 μs = 7.29 kHz

on time (T 1 ) 70.7 μ s
Duty cycle(D%) = = = 50.5
total time(T 1+T 2 ) 140 μ s

Schmitt Trigger or Regenerative Comparator Circuit

A Schmitt trigger circuit is also called a regenerative comparator circuit. The circuit is
designed with a positive feedback and hence will have a regenerative action which will make
the output switch levels. Also, the use of positive voltage feedback instead of a negative
feedback, aids the feedback voltage to the input voltage, instead of opposing it. The use of a
regenerative circuit is to remove the difficulties in a zero-crossing detector circuit due
to low frequency signals and input noise voltages.
Shown below is the circuit diagram of a Schmitt trigger. It is basically an inverting
comparator circuit with a positive feedback. The purpose of the Schmitt trigger is to convert
any regular or irregular shaped input waveform into a square wave output voltage or pulse.
Thus, it can also be called a squaring circuit.

Schmitt Trigger Circuit Using Op-Amp uA741 IC

As shown in the circuit diagram, a voltage divider with resistors Rdiv1 and Rdiv2 is set in
the positive feedback of the 741 IC op-amp. The same values of Rdiv1 and Rdiv2 are used to
get the resistance value Rpar = Rdiv1||Rdiv2 which is connected in series with the input
voltage. Rpar is used to minimize the offset problems. The voltage across R1 is fedback to
the non-inverting input. The input voltage Vi triggers or changes the state of output Vout
every time it exceeds its voltage levels above a certain threshold value called Upper
Threshold Voltage (Vupt) and Lower Threshold Voltage (Vlpt).
Let us assume that the inverting input voltage has a slight positive value. This will cause a
negative value in the output. This negative voltage is fedback to the non-inverting terminal
(+) of the op-amp through the voltage divider. Thus, the value of the negative voltage that is
fedback to the positive terminal becomes higher. The value of the negative voltage becomes
again higher until the circuit is driven into negative saturation (-Vsat). Now, let us assume
that the  inverting input voltage has a slight negative value. This will cause a positive value
in the output. This positive voltage is fedback to the non-inverting terminal (+) of the op-
amp through the voltage divider. Thus, the value of the positive voltage that is fedback to the
positive terminal becomes higher. The value of the positive voltage becomes again higher
until the circuit is driven into positive saturation (+Vsat). This is why the circuit is also
named a regenerative comparator circuit.

Schmitt Trigger Input and Output Waveform

When Vout = +Vsat, the voltage across Rdiv1 is called Upper Threshold Voltage (Vupt). The
input voltage, Vin must be slightly more positive than Vupt inorder to cause the output Vo
to switch from +Vsat to -Vsat. When the input voltage is less than Vupt, the output voltage
Vout is at +Vsat.
Upper Threshold Voltage, Vupt = +Vsat (Rdiv1/[Rdiv1+Rdiv2])
When Vout = -Vsat, the voltage across Rdiv1 is called Lower Threshold Voltage (Vlpt). The
input voltage, Vin must be slightly more negaitive than Vlpt inorder to cause the output Vo
to switch from -Vsat to +Vsat. When the input voltage is less than Vlpt, the output voltage
Vout is at -Vsat.
Lower Threshold Voltage, Vlpt = -Vsat (Rdiv1/[Rdiv1+Rdiv2])
If the value of Vupt and Vlpt are higher than the input noise voltage, the positive feedback
will eliminate the false output transitions. With the help of positive feedback and its
regenerative behaviour, the output voltage will switch fast between the positive and negative
saturation voltages.
Hysteresis Characteristics
Since a comparator circuit with a positive feedback is used, a dead band condition hysteresis
can occur in the output. When the input of the comparator has a value higher than Vupt, its
output switches from +Vsat to -Vsat and reverts back to its original state, +Vsat, when the
input value goes below Vlpt. This is shown in the figure below. The hysteresis voltage can be
calculated as the difference between the upper and lower threshold voltages.
Vhysteresis = Vupt – Vlpt
Subsituting the values of Vupt and Vlpt from the above equations:
Vhysteresis = +Vsat (Rdiv1/Rdiv1+Rdiv2) – {-Vsat (Rdiv1/Rdiv1+Rdiv2)}
Vhysteresis = (Rdiv1/Rdiv1+Rdiv2) {+Vsat – (-Vsat)}

Schmitt-Trigger-Hysteresis Characteristics
 Applications of Schmitt Trigger
Schmitt trigger is mostly used to convert a very slowly varying input voltage into an output having abruptly
varying waveform occurring precisely at certain predetermined value of input voltage. Schmitt trigger may
be used for all applications for which a general comparator is used. Any type of input voltage can be
converted into its corresponding square signal wave. The only condition is that the input signal must have
large enough excursion to carry the input voltage beyond the limits of the hysteresis range. The amplitude
of the square wave is independent of the peak-to-peak value of the input waveform.

The output of an op amp can swing positive and negative to a

maximum voltage close to the supply rail potentials. For example, the
maximum output voltage for the popular 741 op amp, when connected
to a ±18V supply is ±15V.
Because the open loop gain of an op amp is extremely high however,
(typically 10,000 to one million) means that without negative feedback,
any input that creates a difference in voltage between the two input pins
greater than ±150µV may be amplified by, for example 100,000 or more
times, and drive the output into saturation; the output will then appear to
be ‘stuck’ either at its maximum or minimum value. in in this way can be
useful when either dealing with extremely small (and low frequency or
DC) inputs in instrumentation or medical applications, or for comparing
two voltages, using the op amp as a comparator. In this mode the output
will go to either a maximum high or minimum low level, depending on
whether one input is just a few micro volts higher or lower than a
reference voltage applied to the other input.
 The Op Amp as a Comparator

Fig. 6.6.1 Using an Op Amp as a Comparator

Basic op amp types such as the 741 will perform adequately as
comparators in simple circuits, such as a temperature controlled switch
that is required to switch on or off a circuit when the input voltage from a
temperature sensor is higher or lower than a preset reference value.

In Fig. 6.6.1 a reference voltage is applied to the non-inverting input,

whilst a variable voltage is applied to the inverting input. Whenever the
voltage applied to pin 2 is higher than the reference voltage on pin 3 the
output will be at a low voltage, only slightly higher than −Vs and if pin 2 is
at a lower voltage than pin 3, the output voltage will be high, slightly less
than +Vs.

However, standard op amps are designed for low power amplification

purposes and if they are driven into, then out of saturation, it takes some
time for the output voltage to recover and for the op amp to begin
operating in a linear manner once more.
Op amps designed as amplifiers are not particularly suited to use as
comparators especially where the input signals are changing rapidly in
such applications as audio level sensors or analogue to digital
converters. Another problem with the basic comparator arrangement
illustrated in Fig 6.6.1 that is addressed by op amps specially designed
as comparators rather than amplifiers, is that of noise. If there is a
significant amount of noise on the input signal, especially when the input
signal voltage is close to the reference voltage level, the high frequency
voltage variations caused by the random nature of the noise will make
the input signal voltage higher and lower than the reference voltage in
rapid succession, causing the output to momentarily oscillate between its
maximum and minimum voltage levels. However this problem is
overcome in many dedicated comparators by applying hysteresis.

Hysteresis
This refers, in comparators and switching circuits, to the property of the
output in switching to its high or low states at different input values. If a
comparator switched its output at a single input voltage level as
explained in the previous paragraph, or if the difference in the two levels
provided by the comparator’s hysteresis is not wide enough, the
switching from one of the two output conditions to the other could be
very uncertain. Hysteresis can be applied to the op amp comparator and
adjusted for a suitable hysteresis gap by using positive feedback in a
circuit arrangement called the Schmitt Trigger.
 The Schmitt Trigger

Fig. 6.6.2 The Op Amp Schmitt Trigger

The Schmitt Trigger circuit shown in Fig. 6.6.2 is an inverting comparator
based on the LM339 quad comparator IC from Texas Instruments, with
its reference value applied to the non-inverting input by the potential
divider R1 and R2. This sets the reference voltage at half of the 5V
single supply.X

R3 is a pull-up resistor, which is used on the LM339 as this comparator

has an open collector output, that is an output stage where the collector
does not have an internal load resistor connected to supply. The reason
for this is that it allows the output to have a wider range of DC voltages,
rather than just being able to vary between supply and ground.

Positive Feedback
The resistor R4, connected between output and pin 5 (the non-inverting
input) provides positive feedback to speed up output switching as
follows. Suppose the voltage Vin on pin 4 is rising towards the reference
voltage Vref on pin 5 and the output on pin 2 is high. Once Vin is slightly
higher than Vref the output will start to fall towards 0V. A proportion of this
fall in voltage is fed via R4 to pin 5 and so begins to reduce
Vref increasing the difference between Vref and Vin. This causes the output
to fall faster and because this fall is continually fed back to Vref the fall in
the output voltage accelerates, causing a very rapid fall to zero volts. A
similar action occurs when a high voltage on pin 4 falls to a lower value
than pin 5, ensuring very fast output switching.

There is however, another action taking place; it was mentioned in the

previous paragraph that a fall in the output voltage is fed back via R4
and causes a fall in Vref and likewise a rising output voltage will cause a
rise in Vref, changing the reference point Vref depending on whether the
output voltage is high or low. The difference between the high and low
values of Vref is called the hysteresis of the circuit, and is an important
property of the Schmitt Trigger.

Controlling the Hysteresis

Fig. 6.6.3 The Effect of R4 on Hysteresis

Vref controls the point at which the output of the LM339 IC changes from
low to high, or from high to low. By changing the value of Vref depending
on whether the output is low or high introduces some hysteresis (a
difference between the two switching points) into the circuit operation.
Vref is initially controlled by the choice of the potential divider values of
R1 and R2. As these resistors have equal values of 10K, Vref should be
at half the supply voltage (i.e. 2.5V). However the presence of the
feedback resistor R4 introduces hysteresis by changing the value of
Vref depending on whether the output is at its low or high state, as
illustrated in Fig. 6.6.3a and Fig. 6.6.3b.X

Fig 6.6.3a shows that when the output is low, pin 2 of the LM339 is at 0V
and R4 is effectively connected between between Vref on pin 5 of the
LM339 and 0V, effectively connecting R4 in parallel with R2, reducing
Vref to 2.175V.

However, Fig 6.6.3b shows that when the output is high, R4 connects
Vref on pin 5 of the LM339 to +5V, and so changes Vref to 2.82V as
because R4 is now effectively in parallel with R1.

By choosing an appropriate value for R4, the amount of hysteresis (the

change in Vref) can be varied to accommodate different anticipated levels
of noise.

Dedicated Comparator ICs

For high speed comparisons many dedicated comparator op amps are
available that will change their output state in less than 1µs. However, as
is general with most electronic circuits, the faster the outputs change, the
more power is consumed. Comparators of various speeds and different
power consumption figures are available so that the ideal IC for a given
application can be used, depending on whether power consumption or
speed is more important.

Using methods similar in effect to those described above, high speed

comparator integrated circuits with built in hysteresis are available, such
as theLTC1541 from Linear Technology that has a built in hysteresis
property of ±2.25mV to allow for noise on the input signal.X

Comparator ICs are also available that have variable hysteresis to cope
with different amounts of noise, and a built in precision reference
voltage. Some comparators, such as the LMP7300 from Texas
Instruments can also operate from very low single supply voltages and at
extremely low currents. This makes them ideal for such applications as
low battery voltage detectors in portable equipmentX

Using the maximum open loop gaFurther Electronics Tutorial

4 - Sequential Logic Systems
 

What is a sequential circuit?

We have looked at combinational logic systems in which the output was
determined by the combinations of one or more inputs.  The output state at
any time is dependent on the state of the inputs.  In a sequential circuit,
the output is dependent on:
 The current input to the circuit;
 The previous inputs to the circuit.
In effect the circuit has a memory.
 
Sequential circuits are the basic building blocks of:
 Counters;
 Shift registers;
 Memories.
In synchronous sequential circuits, changes in output do not occur
immediately there is a change in input, but the next time there is a clock
pulse.  In asynchronous circuits the next stage is triggered by the
completion of the previous stage without reference to a clock pulse.
 
Clock pulses are square wave oscillations that are produced by a pulse
generator that can be based on two kinds of circuit:
 Astable generators produce trains of square waves;
 Monostables produce single pulses.
 
Circuits are triggered in one of two ways:
 Level triggering in which the changes occur when the level of the
pulse is either at 0 or 1.
  Edge triggering in which the change occurs as the clock pulse rises
from 0 to 1(rising or positive edge) or from 1 to 0 (falling or negative
edge).
 
The diagram shows the idea.

 
Level sensitive devices are often referred to as latches, while edge triggered
devices are called flip-flops.  Pulses can be provided manually with switches,
but they can provide spurious pulses due to bounce.  They can be de-
bounced using a Schmitt trigger, which also can be used to clean up noisy
signals.
 
 ANSWER
 
What is the difference
between pulses
Question 1 produced by a
monostable and an
astable? 

What is the behaviour

you would expect from
Question 2 a synchronous falling
edge triggered flip-
flop? 

 
Here some important definitions to learn.
 
 
Term Definition
Combinational The output is determined by the combinations of one or more inputs.
circuit
Sequential circuit  Output is dependent on:
 
 The current input to the circuit;

 The previous inputs to the circuit.

Synchronous Changes in output do not occur immediately there is a change in input,

but the next time there is a clock pulse
Asynchronous The next stage is triggered by the completion of the previous stage
without reference to a clock pulse
Triggering Level triggering in which the changes occur when the level of the pulse is
either at 0 or 1.
 
Edge triggering in which the change occurs as the clock pulse rises from
  0 to 1(rising or positive edge) or from 1 to 0 (falling or negative edge).
Flip-Flop Edge triggered devices are called flip-flops.

 
Latch Level sensitive devices are often referred to as latches
 
Bistable Latches
Bistables have two stable states; one output remains high while the other
remains low.  These are complementary states.  The situation remains until
an external input signal such as a clock pulse switches the complimentary
states over.
 
We can use two NAND gates to produce an S-bar - R-bar latch.  The
circuit diagram is shown below.
 

 
There are two inputs to the latch, the set, S-bar, and the reset, R-bar. 
There are two output states, Q and Q-bar which are complementary to each
other.  This means that when Q = 0, Q-bar = 1, and vice versa.  The common
symbol for the latch is not the circuit diagram above, but either of the
alternatives shown.
 

 
This bistable is the industry standard, made from NAND gates.  We say that
its inputs are active-low which means that the state changes when the
inputs go low.
 
We can draw up a truth table, often called a transition table for the circuit. 
We can also show what is happening in a timing diagram, which is three
voltage-time graphs stacked one on top of the other.
 
S-bar R-bar Q Q-bar Notes
0 1 1 0 S-bar = 0 sets Q = 1 (SET)
1 1 1 0 Outputs remain in previous states
1 0 0 1 R-bar = 0 sets Q-bar = 1 and Q =
0 (RESET)
1 1 0 1 Outputs remain in previous states
0 0 0 0 Indeterminate state (not allowed)
 

 
When S-bar falls from 1 to 0, there is no effect until the R-bar falls from 1 to
0.  Then the output Q changes from 1 to 0.  Then R-bar goes to 1, but there
is no change in Q until S-bar goes to 1.
This  latch is a circuit that can be used to de-bounce a switch, cleaning its
action to get rid of unwanted pulses.  The layout is shown in the diagram:
 

 
Let us analyse the circuit as the switch is moved from B to A.
 
     
Switch Position S-bar R-bar Q
     
1 0 0
 
       
1 1 0

  
       
0 1 1
  
       
1 1 1
  
       
0 1 1
   
 
 
Notice how the output does not change as the switch bounces.
 
There is one disadvantage about the S – R bistable circuit, and that is what
happens when both the inputs are 0.  This is an indeterminate state and the
output is not predictable.  We cannot say if the bistable will return to the SET
or the RESET state.  We can avoid this by ensuring that the inputs are
changed alternately.
 
What is the problem
Question 3 with there being an
indeterminate state?

 
 
The D-type Flop-Flip
Latches can be used to act as memories, but have a major problem.  They
can be what is called transparent.  If one of the inputs is high, and the other
is connected to a clock impulse, the output will change as the clock pulses
pass through.  Let us think about this more using the S – R latch (made from
NOR gates).  Data is put in through the S input while the R input is connected
to a square wave pulse generator as below.
 

 
 
This latch is active high, which means that it changes state when S or R goes
high.  We start off with R low and S changing from low to high and back
again.  The output Q is low.  Then we change R to high and this should give
us a high at the output Q.  We get that initially, but when the input S goes
low, the output goes low.  When it goes high, the output goes high as
well.  This situation lasts as long as R stays high.  So we get the clock pulse
passing through the latch, which is why we call it transparent.  This can be a
nuisance in computers and other systems where data changes rapidly.
 
We can overcome this problem by using edge-triggering.  Bistables that use
edge triggering are called flip-flops.  Flip-flops do not have this problem with
being transparent.  The D-type flip-flop is the basic design unit
for sequential circuits, which are circuits whose outputs change with
time.  The symbol with the D-type flop-flip is shown.

  
We should note the following about the flip-flop:
 The outputs are complimentary.  When Q is 1, Q-bar is 0 and vice versa.
 Terminal S and R are there to set and reset the flip-flop.  Signals at
these inputs take priority over the other two inputs
 The data input takes in the data, while the clock input takes in the
clock pulses.  The triangle indicates edge triggering.  An upward
pointing arrow indicates positive edge triggering, while a downward
arrow shows negative edge triggering.
 CMOS flip-flops are active high, while many TTL flip-flops are active low.
  The behaviour of the flip-flop is shown.
 
When we send a pulse down the SET or RESET lines, the results can be
shown in the truth table:
 
S R Q Q-bar
0 0 1/0 0/1
0 1 0 1
1 0 1 0
1 1 1 1
 
 

 
 
Question 4 What is meant by a
 circuit being
transparent?

Using D-type Flip-flops to Make a Shift Register

Shift registers are important components in computers.  They act as

memories for binary numbers, and are important in shifting data about the
computer.  Data may be received in serial form, i.e. one digit after another,
but is sent in whole words through the computer.  Each bit of a word needs
its own wire to travel in, therefore for a 4-byte word (1 byte = 8 bits,
therefore 32 bits) needs 32 parallel connectors.  This is calledparallel data
transmission.

Very high speeds are possible because of the parallel connectors, buses, that
form the highways between computer components.  The diagramshows the
difference between serial and parallel data transmission.

Question 5 Why is the printer

cable that comes from
a parallel port on a
computer is so thick
 and heavy?

D type flip-flops are used to enable this in these ways:

 Serial input serial output (SISO)

 Parallel input parallel output (PIPO)

 Serial input parallel output (SIPO)

  Parallel input serial output (PISO)

We will look at a four-bit serial input parallel output shift register.

 The resets are all connected so that the circuit can be cleared to 0
at the same time.

 At the rising edge of the clock input, the output takes on the
value of the data input.

 The set inputs are not connected.

 The Q-bar outputs are not used.

 The Q subscripts refer to the power of 2.  Q2 carries the 22 (4) bit.

We are going to put the number 1101 into the register to see how this works
and the table below shows the sequence of events.

Clock Q3 Q2 Q1 Q0 Notes
pulse
0 0 0 0 0  
1 1 0 0 0  
2 0 1 0 0  
3 1 0 1 0  
4 1 1 0 1 Data
loaded
5 0 1 1 0  
6 0 0 1 1  
7 0 0 0 1  
8 0 0 0 0 Data out

 The timing diagram is shown here:

We can use the timing diagram to explain what is happening:

 On the clock pulse F1 changes Q3 from 0 to 1.

 This sets F2 to change Q2 at the second rising edge from 0 to 1.

 Which in turn changes F3 and so on.

 F1 changes back from 1 to 0 on the second rising edge.

 followed by F2 and F3 in turn.

 The Table shows the data being loaded by the 4th clock pulse.
 Can you use the
timing diagram to
Question 6 explain how a SIPO
shift register works?

 
 
Monostable Circuits based on NAND gates
Here is a monostable circuit based on a NAND gate:
 

 
 
What is meant by the
Question 7 term monostable?

 
How does the circuit work?  At first the circuit is stable.
 When switch S is open, the point L is at 1.
 The capacitor C is not charged and the voltage at M is 0.
 Therefore the output of Y is 1, and both inputs of X are 1.
 The output of X is 0.
  Since the inputs of Z are 1, and the output of Z is 0.
Now let us momentarily close the switch S.
 T becomes 0.
 Therefore the input L into gate X becomes 0.
 The output of X becomes 1.
 The flow of charge onto the capacitor C causes there to be a current
through the resistor R.  This makes the voltage at M high.
 Therefore gate Y gives out a 0.
  Since the voltage at N is a zero, the output of gate Z is 1, and the LED
lights up.
What does gate Z do
Question 8 and why?

 
This lasts a short time, determined by the RC time constant.
 The current through R decays exponentially as the capacitor charges
up.  So the voltage at M decays exponentially as well.
 As the voltage at M drops, it passes below the threshold at which Y is
triggered to change state.
 Gate Y gives out a 0 until the voltage passes below the threshold.
 Now gate Y changes to 1.
 Since L is at 1, this makes the output of X low again.
  If the switch is held closed, the output of X remains 1, but no current flows
onto the plates of the capacitor, so the voltage at M remains low. Therefore
holding the switch has no effect on the behaviour of the circuit. We can show
the behaviour of the circuit with timing diagrams for each of the points.
 

 
Depending on the threshold at which the gate triggers, it can be shown that
the time period T at for which the output of Z is high is approximatelyRC.  
If the gate triggers at 0.5 Vs, then T   is approximately 0.7 RC.
 
 Why does the voltage
Question 9 at M show the shape
shown?
 
 
NAND gate Astable
We can make an astable circuit the output of which oscillates at a frequency
determined by the value of the time constant of a capacitor and a resistor. 
 

 
If you look carefully at the arrangements of the NAND gates, it does not take
a genius to see that the two NAND gates are wired as NOT gates, so this set
up is also called a NOT gate astable.  Let’s have a look at how the circuit
works:
 Suppose the output of Y is high.
 This means that the input to Y is low.
 The capacitor will charge up.
  A current flows through the resistor R which means there will be a
voltage across it.
 This raises the input to Y to high and it will trigger to the output being
low.
 Since X is connected to the feedback loop, its output will be low.
 The low output of X will cause the capacitor to discharge.
 This makes the input to Y low, hence the output to go to high.
 And so on…
  We can summarise this in the timing diagram:
  
We can show that the mark time is given by the relationship:
 tH =1.1 RC
 
Similarly the space time is given by:
 tL 1.1 RC
 
Therefore the period:
 T = tH + tL = 2.2 RC
 
So the frequency:
f = 1/T = 1/2.2 RC