Problem

What is a clock gating check? How is clock gating check done and reported in Tempus, Innovus and Genus?

Solution
Clock Gating Definition
A gated clock signal occurs when the clock network contains logic other than inverters and buffers as shown in following
example:

In this case:

When the data signal EN=0, the output clock, GCK, will always be 0, irrespective of clock CK state.
When the data signal EN=1, the output clock, GCK, will be equal to CK.
To obtain a proper gated clock signal at the output, the following condition must be satisfied:

The control input, EN, must satisfy a setup check and a hold check.
The clock input, CK, must have a dominant phase or the controlling state.

Controlling or Dominant State

The clock will be in the controlling state when the output is controlled only by the clock signal and is not affected by the
state of EN.

For AND/NAND gate, the CK’s controlling state is ‘0’ (because the output will always be 0 during this time,
irrespective of the state of EN ).
For OR/NOR gate, the CK’s controlling state is ‘1’.
For example, in the case shown in above diagram, where CG1 is an AND gate, the clock, CK, will be controlling low as
shown in the following diagram:

When the CK is in control, the EN signal can change. Otherwise, it will result in the setup or hold violation.

Clock Gating Setup and Hold Checks

The setup check is performed with respect to the edge of the clock signal that changes the state of the clock pin from
controlling to non-controlling. The clock gating setup check is used to ensure the data signals are stable before the clock
is active.

A clock gating setup failure can cause either a glitch at the leading edge of the clock pulse, or a clipped clock pulse.

The hold check is performed with respect to the edge of the clock signal that changes the state of the clock pin from non-
controlling to controlling. The clock gating hold check is used to ensure that the data signals are stable while the clock is
active.

A clock gating hold violation causes either a glitch at the trailing edge of the clock pulse, or a clipped clock pulse.
The following diagram shows the controlling and non-controlling state of the clock along with the setup and hold values:

In the following diagram, assume the setup and hold values for clock gating checks to be zero. If EN changes in the non-
controlling state, it will cause either setup or hold violation.

Specifying Clock Gating Setup and Hold values

Clock gating checks can be inferred by the tool or picked from library for ICG (integrated clock gating) cells.

The setup and hold values for inferred clock gating checks, for the logical cells such as AND gates that do not have setup
or hold constraints defined in the timing library, can be specified using the set_clock_gating_check command else
tool will consider clock gates with zero setup and hold value.

For ICG cells, the setup and hold values are already specified in the library. Because the ICG cells are characterized with
the setup and hold values, it is not recommended to change the internal characterization using
set_clock_gating_check command. However, if the set_clock_gating_check is applied, it will override
only the internal values if applied to the specific pins. It will not override the internal values if applied to the clock
waveform.

Reporting Clock Gating Check

You can use clock_gating_setup and clock_gating_hold with report_timing -check_type to report the
clock gating setup and hold report, respectively.
In the example below, the following is the setup and hold constraints defined in the SDC:

set_clock_gating_check -setup 1.5 [get_cells A1]

set_clock_gating_check -hold 1.0 [get_cells A1]

You can generate the clock gating setup report using the following command:

> report_timing -check_type clock_gating_setup

Path 1: MET Clock Gating Setup Check with Pin A1/B

Endpoint:   A1/A  (^) checked with  leading edge of 'ck2'
Beginpoint: FF1/Q (^) triggered by  leading edge of 'ck1'
Path Groups: {clock_gating_default}
Other End Arrival Time          0.000
- Clock Gating Setup            1.500
+ Phase Shift                  10.000
= Required Time                 8.500
- Arrival Time                  0.131
= Slack Time                    8.369
     Clock Rise Edge                 0.000
     + Clock Network Latency (Prop)  0.000
     = Beginpoint Arrival Time       0.000
      --------------------------------------------------------
      Instance  Arc          Cell     Delay  Arrival  Required  
                                             Time     Time  
      --------------------------------------------------------
      FF1       CK ^         -        -      0.000    8.369  
      FF1       CK ^ -> Q ^  DFFHQX1  0.131  0.131    8.500  
      A1        A ^          AND2X1   0.000  0.131    8.500  
      --------------------------------------------------------

You can generate the clock gating hold report using the following command:

> report_timing -check_type clock_gating_hold

Path 1: VIOLATED Clock Gating Hold Check with Pin A1/B

Endpoint:   A1/A  (v) checked with trailing edge of 'ck2'
Beginpoint: FF1/Q (v) triggered by  leading edge of 'ck1'
Path Groups: {clock_gating_default}
Other End Arrival Time          5.000
+ Clock Gating Hold             1.000
+ Phase Shift                   0.000
= Required Time                 6.000
  Arrival Time                  0.113
  Slack Time                   -5.887
     Clock Rise Edge                 0.000
     + Clock Network Latency (Prop)  0.000
     = Beginpoint Arrival Time       0.000
      --------------------------------------------------------
      Instance  Arc          Cell     Delay  Arrival  Required  
                                              Time     Time  
      --------------------------------------------------------
      FF1       CK ^         -        -      0.000    5.887  
      FF1       CK ^ -> Q v  DFFHQX1  0.113  0.113    6.000  
      A1        A v          AND2X1   0.000  0.113    6.000  
      --------------------------------------------------------

You can use the report_clock_gating_check command to report information of all or specific clock gating checks
as follows:

> report_clock_gating_check
      ------------------------------------------------------------------------------
-------------------  
       Clock Gating Check
Report                                                                         
      ------------------------------------------------------------------------------
-------------------  
       Instance                         Enable   Clock   Type    Level   Setup  
Setup   Hold    Hold    
                                                                         Rise   
Fall    Rise    Fall    
      ------------------------------------------------------------------------------
-------------------  
      A1                               A        B       I       H       1.500  
1.500   1.000   1.000
      ------------------------------------------------------------------------------
-------------------

Specifying Non-Controlling State

If the tool is unable to determine the needed clock gating check for the gate such as MUX or AOI, you can explicitly
specify a non-controlling state by using the following command:

set_clock_gating_check –high | –low [get_pins U0/S0]

Clock Gating Checks for MUX / Complex Cells

A clock gating check at MUX inputs ensure that the MUX select signal arrives at the right time while switching from one
input to another.

By default, the clock gating check is not inferred for complex combinational cells such as MUX, AND-OR, XOR because the
clock is never in the controlling state. However, you can force clock gating on MUX by specifying explicitly either -high or
-low option with set_clock_gating_check command. The -high/-low option will force non-controlling state of
the clock as logic high or logic low respectively. For a MUX, the select signal acts as the gating signal and -high option
implies that the select signal should switch only before the input clock goes to high logic level (logic 1). It is worthwhile to
note a few essential points regarding -high/-low option:

The -high/-low option sets the attribute only on the specified pin or the cell and does not affect the transitive
fanout of it.
Specifying object list is mandatory with -high/-low option.
A clock or port cannot be specified in the object list, if you are using -high/-low option.
Example:
  

> set_clock_gating_check -high [get_cells MUX0]

The above clock gating setup and hold checks will apply for both clock inputs to the multiplexer cell. If you want to
disable clock gating check for one of clock inputs, you can turn off the clock gating check for that multiplexer input pin as
follows:     

> set_disable_clock_gating_check MUX0/A

For the clock gating check to be recognized, it is a necessary condition that the output of the MUX is used as a clock
signal downstream. The downstream clock usage can be either of the following:

A clock pin of a flip-flop

An output port
A generated clock that refers to the output of the gating cell as its master
Therefore, ensure that the clock(s) leaving the MUX is not prevented from propagating downstream by any constraints
such as set_disable_timing or set_clock_sense. In the above example, either of the following constraints would
inhibit propagation of clock CK1 from the input to the output of the MUX.

> set_disable_timing -from A -to Y [get_cells MUX0]

                 OR
> set_clock_sense [get_pins MUX0/A] -stop_propagation

Use report_clock_propagation command in Tempus/Innovus at MUX output pin or

report_cell_instance_timing on the MUX's instance to crosscheck that the clock propagation through the MUX is
successful.

Example:

> report_clock_propagation -clock CK1 -to MUX0/Y

Clock: CLK
Point: MUX0/Y
The clock 'CLK' propagates to the pin 'MUX0/Y'

To confirm whether or not the clock gating check is successfully asserted on the cell/pin, use
report_clock_gating_check command to get a report as shown below:

> report_clock_gating_check
------------------------------------------------------------------------------------
-------------  
Clock Gating Check
Report                                                                         
------------------------------------------------------------------------------------
-------------  
Instance                         Enable   Clock   Type    Level   Setup   Setup  
Hold    Hold    
                                                                   Rise    Fall   
Rise    Fall    
------------------------------------------------------------------------------------
-------------  
MUX0                             S0       B       I       H       0.230   0.230  
0.000   0.000
 MUX0                             S0       A       I       H       0.230   0.230  
0.000   0.000
------------------------------------------------------------------------------------
-------------

Clock gating check can also be applied on a MUX cell that samples data signals and has a clock as select pin driver. A
typical example is frequently seen in case of DDR MUX interface and MUX based frequency divider.

Note that output of the MUX reaches an output port, thus making it a valid downstream clock usage.The clock phase
reaches through the select pin S to the MUX output pin Y and through the buffer to the output port.

Clock gating check can be declared as:

set_clock_gating_check -low -hold 0.2  -setup 0.2 [get_pins UMUX0/A]

set_clock_gating_check -high -hold 0.2 -setup 0.2 [get_pins UMUX0/B]

Note:  If one of the MUX inputs is a clock signal and the other (for 2x1 MUX) is constrained to a logic 1/0 value, in that
case the MUX select pin will act like a clock-gating enable signal, because the MUX function will reduce to a simple OR-
type or AND-type clock-gating cell as shown below:

The functionality of a 2X1 MUX can be expressed as: 

Y = B*!S0 + A*S0

When A pin is driven by CLK and B pin is set to logic 0 or logic 1, the MUX output function becomes: 

When B=logic 1, Y=!S0 + CLK*S0 = (!S0 + CLK)

When B=logic 0, Y= (A*S0) 

In that scenario, no explicit set_clock_gating_check command is required for the MUX cell anymore. Clock
gating check will be automatically inferred for it.

Disabling Clock Gating Checks

By default, the tool performs the clock gating checks during timing analysis. This is controlled by the following command:

setAnalysisMode -clockGatingCheck true|false   #Use setAnalysisMode command in Innovus

set_analysis_mode -clockGatingCheck true|false   #Use set_analysis_mode command in
Tempus

Disabling Inferred Clock Gating Checks

If the clock gating checks are specified using the set_clock_gating_check command, it is called inferred clock
gating and can be disabled using the following command:

set timing_disable_inferred_clock_gating_checks true

If you want to disable a particular inferred clock gating check, use the following command:

set_disable_clock_gating_check <object_list> 
 Here, <object_list> specifies a list of pins or instances for which the clock gating check should be disabled.

Note: To disable clock gating checks for a specific view, the above constraint can be used in the constraints file for that
view. 

Disabling Integrated Clock Gating (ICG) Checks

The set_disable_clock_gating_check command does not work to disable any timing to the data/enable pin for
the ICG cells. To disable timing on the ICG cells, you need to set a false path to the data/enable pins of these cells:

set_false_path -to icg_cell/en

Clock Gating Checks in Genus

Genus performs only clock gating setup check and does not perform clock gating hold check. However, it preserves the
constraints when saved with write_sdc command.

Sample clock gating setup report in Genus:

genus:root:> report_timing -through UMUX0/A

Path 1: MET (7660 ps) Clock Gating Setup Check at pin UMUX0/A
          Group: CLK
     Startpoint: (R) UFF1/CK
          Clock: (F) CLK
       Endpoint: (F) UMUX0/A
          Clock: (F) CLK

                     Capture       Launch     

        Clock Edge:+   12000         4000     
       Src Latency:+       0            0     
       Net Latency:+       0 (I)        0 (I)
           Arrival:=   12000         4000     
                                              
      Output Delay:-     200                  
     Required Time:=   11800                  
      Launch Clock:-    4000                  
         Data Path:-     140                  
             Slack:=    7660                  

Exceptions/Constraints:
  output_delay             200             clk_gating_check_2

#------------------------------------
# Timing Point   Arc   Delay Arrival
#                       (ps)   (ps)  
#------------------------------------
  UFF1/CK        -         -    4000
  UFF1/Q         CK->Q   140    4140
  UMUX0/A        -         0    4140
#------------------------------------

(b) : Timing paths are broken.

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