M48Z129V

3.3 V, 1 Mbit (128 Kb x 8) ZEROPOWER® SRAM

Not recommended for new design

Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ Conventional SRAM operation; unlimited
WRITE cycles
( s )
■ 10 years of data retention in the absence of
power
u ct
■ Microprocessor power-on reset (reset valid
o d
■
even during battery backup mode)
Battery low pin - provides warning of battery
32

P
1
r
end-of-life
e t e
■ Automatic power-fail chip deselect and WRITE
o l
bs
protection PMDIP32 module
■ WRITE protect voltages
– VCC = 3.0 to 3.6 V; 2.7 V ≤ VPFD ≤ 3.0 V
- O
■
(VPFD = power-fail deselect voltage)
Self-contained battery in the CAPHAT™ DIP
( s )
package
c t
■
u
Pin and function compatible with JEDEC
d
■
standard 128 K x 8 SRAMs
RoHS compliant r o
P
– Lead-free second level interconnect
e
l e t
s o
O b

September 2011 Doc ID 5716 Rev 8 1/20

This is information on a product still in production but not recommended for new designs. www.st.com 1
 Contents M48Z129V

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
( s )
3
u ct
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

o d
4 r
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
P
5 t e
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
e
o l
6 s
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
b
7 - O
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

(s )
8
c t
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

d u
r o
e P
l e t
s o
O b

2/20 Doc ID 5716 Rev 8

 M48Z129V List of tables

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10.
Table 11.
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic DIP, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 16
( s )
Table 12.
Table 13.
u ct
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

o d
P r
e t e
o l
b s
- O
(s )
c t
d u
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e P
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Doc ID 5716 Rev 8 3/20

 List of figures M48Z129V

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Figure 6. WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10.
Figure 11.
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic module DIP, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 16
( s )
Figure 12.
ct
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

u
o d
P r
e t e
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

4/20 Doc ID 5716 Rev 8

M48Z129V Description

1 Description

The M48Z129V ZEROPOWER® SRAM is a 1,048,576 bit non-volatile static RAM organized
as 131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM
and a control circuit in a plastic 32-pin DIP module. The M48Z129V directly replaces
industry standard 128 K x 8 SRAM. It also provides the non-volatility of FLASH without any
requirement for special WRITE timing or limitations on the number of WRITEs that can be
performed.

Figure 1. Logic diagram

VCC

( s )
A0-A16
17 8
DQ0-DQ7
u ct
o d
r
W RST
M48Z129V
E BL

e P
G

l e t
s o
O b
VSS
AI02309

Table 1. Signal names

) -
A0-A16

DQ0-DQ7
c t (s
Address inputs

Data inputs / outputs

u
od
E Chip enable

Pr
G Output enable

ete
W WRITE enable

ol
RST Reset output (open drain)

bs
BL Battery low output (open drain)

VCC Supply voltage

O VSS Ground

Doc ID 5716 Rev 8 5/20

 Description M48Z129V

Figure 2. DIP connections

RST 1 32 VCC
A16 2 31 A15
A14 3 30 BL
A12 4 29 W
A7 5 28 A13
A6 6 27 A8
A5 7 26 A9
A4 8 M48Z129V 25 A11
A3 9 24 G
A2 10 23 A10
A1 11 22 E
A0 12 21 DQ7
DQ0 13 20 DQ6
DQ1 14 19 DQ5

( s )
ct
DQ2 15 18 DQ4
VSS 16 17 DQ3
AI02310

d u
Figure 3. Block diagram
r o
e P
let
VCC A0-A16

E
VOLTAGE SENSE
b
POWER
so 131,072 x 8
SRAM ARRAY
DQ0-DQ7

AND
SWITCHING
O
)-
E
CIRCUITRY W

INTERNAL
t ( s G

u c
BATTERY

o d
Pr
RST BL VSS
AI03608

e t e
s ol
O b

6/20 Doc ID 5716 Rev 8

 M48Z129V Operation modes

2 Operation modes

The M48Z129V also has its own power-fail detect circuit. This control circuitry constantly
monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance,
the circuit write protects the SRAM, providing data security in the midst of unpredictable
system operation. As VCC falls, the control circuitry automatically switches to the battery,
maintaining data until valid power is restored.

Table 2. Operating modes

Mode VCC E G W DQ0-DQ7 Power
Deselect VIH X X High Z Standby
WRITE
4.5 to 5.5 V
VIL X VIL DIN
(
Active
s )
ct
or
READ VIL VIL VIH DOUT Active
3.0 to 3.6 V

du
READ VIL VIH VIH High Z Active

ro
Deselect VSO to VPFD (min)(1) X X X High Z CMOS standby
Deselect ≤ VSO(1) X X X

e PHigh Z Battery backup mode

Note:
1. See Table 10 for details.

X = VIH or VIL; VSO = battery backup switchover voltage

l e t
s o
2.1 READ mode
O b
) -
The M48Z129V is in the READ mode whenever W (WRITE enable) is high and E (chip

(s
enable) is low. The unique address specified by the 17 address inputs defines which one of

c t
the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within tAVQV (address access time) after the last address input signal is stable, providing the

d u
E and G access times are also satisfied. If the E and G access times are not met, valid data

r
access time (tGLQV). o
will be available after the latter of the chip enable access times (tELQV) or output enable

e P
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are

l e t
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the address inputs are changed while E and G remain active, output data will remain valid

s o for tAXQX (output data hold time) but will go indeterminate until the next address access.

O b Figure 4. Address controlled, READ mode AC waveforms

tAVAV

A0-A16 VALID

tAVQV
tAXQX

DQ0-DQ7 DATA VALID DATA VALID

AI02324

Note: Chip enable (E) and output enable (G) = low, WRITE enable (W) = high

Doc ID 5716 Rev 8 7/20

 Operation modes M48Z129V

Figure 5. Chip enable or output enable controlled, READ mode AC waveforms

tAVAV

A0-A16 VALID

tAVQV tAXQX

tELQV tEHQZ

tELQX

tGLQV tGHQZ

)
tGLQX
DQ0-DQ7 DATA OUT

( s
ct
AI01197

Table 3. READ mode AC characteristics

d u
o
Pr
Symbol Parameter(1) Min Max Unit
tAVAV READ cycle time 85 ns
tAVQV Address valid to output valid

e t e 85 ns

ol
tELQV Chip enable low to output valid 85 ns

bs
tGLQV Output enable low to output valid 45 ns
(2)
tELQX Chip enable low to output transition 5 ns
tGLQX(2)
- O
Output enable low to output transition 5 ns
tEHQZ(2)

( s )
Chip enable high to output Hi-Z 40 ns
tGHQZ(2)

c t
Output enable high to output Hi-Z 25 ns

du
tAXQX Address transition to output transition 5 ns
1.

o
Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).

2.
r
CL = 5pF (see Figure 9).

P
e t e
s ol
O b

8/20 Doc ID 5716 Rev 8

M48Z129V Operation modes

2.2 WRITE mode

The M48Z129V is in the WRITE mode whenever W (WRITE enable) and E (chip enable) are
active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A
WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or
tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in
must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid bus contention; although, if the output
bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after
W falls.

Figure 6. WRITE enable controlled, WRITE mode AC waveform

( s )
ct
tAVAV

A0-A16 VALID

tAVWH

d u
tAVEL

r otWHAX

tWLWH

e P
tAVWL

l e t
W

o
bs
tWLQZ tWHQX

tWHDX

-O
DQ0-DQ7 DATA INPUT

(s)
tDVWH
AI02382

Figure 7.
c t
Chip enable controlled, WRITE mode AC waveforms

d u
r o tAVAV

e P A0-A16 VALID

t
tAVEH

o l e E
tAVEL tELEH tEHAX

bs
tWLWH

O
tAVWL

tDVEH tEHDX

DQ0-DQ7 DATA INPUT

AI03611

Doc ID 5716 Rev 8 9/20

 Operation modes M48Z129V

Table 4. WRITE mode AC characteristics

Symbol Parameter(1) Min Max Unit
tAVAV WRITE cycle time 85 ns
tAVWL Address valid to WRITE enable low 0 ns
tAVEL Address valid to chip enable low 0 ns
tWLWH WRITE enable pulse width 65 ns
tELEH Chip enable low to chip enable high 75 ns
tWHAX WRITE enable high to address transition 5 ns
tEHAX Chip enable high to address transition 15 ns
tDVWH Input valid to WRITE enable high 35 ns
tDVEH Input valid to chip enable high 35

( s )
ns
tWHDX WRITE enable high to input transition 0
c t ns
tEHDX
tWLQZ(2)(3)
Chip enable high to input transition 15

d u ns

tAVWH
WRITE enable low to output Hi-Z
Address valid to WRITE enable high r o
75
30 ns
ns
tAVEH Address valid to chip enable high
e P 75 ns
tWHQX (2)(3) WRITE enable high to output transition
e t 5 ns
1.
ol
Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).

s
2.
3.
CL = 5 pF (see Figure 9).

O b
If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

) -
2.3 Data retention mode
c t (s
d u
With valid VCC applied, the M48Z129V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting

r o
itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high
impedance and all inputs are treated as “Don’t care”.
Note:
e P
A power failure during a WRITE cycle may corrupt data at the current addressed location,

l e t
but does not jeopardize the rest of the RAM’s content. At voltages below VPFD(min), the
memory will be in a write protected state, provided the VCC fall time is not less than tF. The

s o M48Z129V may respond to transient noise spikes on VCC that cross into the deselect

O b window during the time the device is sampling VCC. Therefore, decoupling of the power
supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery,
preserving data. The internal energy source will maintain data in the M48Z129V for an
accumulated period of at least 10 years at room temperature. As system power rises above
VSO, the battery is disconnected, and the power supply is switched to external VCC.
Deselect continues for tREC after VCC reaches VPFD(max).
For more information on battery storage life refer to the application note AN1012.

10/20 Doc ID 5716 Rev 8

 M48Z129V Operation modes

2.4 VCC noise and negative going transients

ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 8) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a

1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
( s )
Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode

ct
mount.

Figure 8. Supply voltage protection

d u
r o
VCC

e P
t
VCC

0.1µF

o l e
DEVICE

b s VSS

O
)-
AI02169

t ( s
u c
o d
P r
e t e
o l
b s
O

Doc ID 5716 Rev 8 11/20

 Maximum ratings M48Z129V

3 Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Table 5. Absolute maximum ratings

Symbol Parameter Value Unit
TA Ambient operating temperature 0 to 70 °C
TSTG Storage temperature (VCC off, oscillator off) –40 to 85
( s )
°C
TSLD(1) Lead solder temperature for 10 seconds 260
ct °C

du
VIO Input or output voltages –0.3 to 7 V

ro
VCC Supply voltage –0.3 to 7 V
IO
PD
Output current
Power dissipation
e P 20
1
mA
W

l e t
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices

s o
shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST
recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.

Caution:
b
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
O
) -
c t (s
d u
r o
e P
l e t
s o
O b

12/20 Doc ID 5716 Rev 8

 M48Z129V DC and AC parameters

4 DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.

Table 6. Operating and AC measurement conditions

Parameter Unit
Supply voltage (VCC) 3.0 to 3.6 V
Ambient operating temperature (TA) 0 to 70
( s
°C)
Load capacitance (CL) 50
ct pF

du
Input rise and fall times ≤5 ns

ro
Input pulse voltages 0 to 3 V
Input and output timing ref. voltages

e P 1.5 V

Note: Output Hi-Z is defined as the point where data is no longer driven.

l e t
Figure 9. AC testing load circuit
s o
DEVICE

O b 650Ω

-
UNDER
TEST

(s )
ct
CL = 100pF 1.75V
or 50pF(1)

d u
r o
e P CL includes JIG capacitance
AI03630

l e t
1. 50 pF for M48Z129V (3.3 V).

s o Table 7. Capacitance

O b Symbol
CIN
Parameter(1)(2)
Input capacitance
Min
-
Max
10
Unit
pF
CIO (3) Input / output capacitance - 10 pF
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.

Doc ID 5716 Rev 8 13/20

 DC and AC parameters M48Z129V

Table 8. DC characteristics
Sym Parameter Test condition(1) Min Max Unit
ILI Input leakage current 0 V ≤ VIN ≤ VCC ±1 µA
(2)
ILO Output leakage current 0 V ≤ VOUT ≤ VCC ±1 µA
ICC Supply current Outputs open 50 mA
ICC1 Supply current (standby) TTL E = VIH 4 mA
ICC2 Supply current (standby) CMOS E = VCC – 0.2 V 3 mA
VIL Input low voltage –0.3 0.6 V
VIH Input high voltage 2.2 VCC + 0.3 V
VOL Output low voltage IOL = 2.1 mA 0.4 V
VOH Output high voltage IOH = –1 mA 2.2

( sV)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
c t
2. Outputs deselected.

d u
r o
e P
e t
s ol
O b
) -
c t (s
d u
r o
e P
l e t
s o
O b

14/20 Doc ID 5716 Rev 8

 M48Z129V DC and AC parameters

Figure 10. Power down/up mode AC waveforms

VCC
VPFD (max)

VPFD (min)

VSO

tF tDR tR

tFB tRB tREC

tWPT

E RECOGNIZED DON'T CARE RECOGNIZED

HIGH-Z
OUTPUTS VALID VALID
(PER CONTROL INPUT) (PER CONTROL INPUT)

( s )
ct
RST
AI03610

d u
r o
Table 9.
Symbol
Power down/up AC characteristics
Parameter(1)
e P Min Max Unit

tF(2) VPFD (max) to VPFD (min) VCC fall time

l e t 300 µs

o
bs
tFB(3) VPFD (min) to VSS VCC fall time 150 µs
tR VPFD (min) to VPFD (max) VCC rise time 10 µs
tRB VSS to VPFD (min) VCC rise time
- O 1 µs

)
t(s
tWPT Write protect time 40 250 µs
tREC VPFD (max) to RST high

u c 40
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
200 ms

o d
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).

P r
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

e t e
Table 10.
s ol Power down/up trip points DC characteristics

O b Symbol

VPFD
Parameter(1)(2)

Power-fail deselect voltage

Min

2.7
Typ

2.9
Max

3.0
Unit

V
VSO Battery backup switchover voltage 2.45 V
(3)
tDR Expected data retention time 10 Years
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
3. At 25 °C, VCC = 0 V.

Doc ID 5716 Rev 8 15/20

 Package mechanical data M48Z129V

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 11. PMDIP32 – 32-pin plastic module DIP, package outline

( s )
ct
A1 L C
S
e3
B e1 eA

d u
D
r o
e P
N

l e t
s
E
o
1

O b PMDIP

Note: Drawing is not to scale.

) -
Table 11.
t (s
PMDIP32 – 32-pin plastic DIP, package mechanical data
c
Symb
d u mm inches

r o Typ Min Max Typ Min Max

e P A
A1
9.27
0.38
9.52
–
0.365
0.015
0.375
–

l e t B 0.43 0.59 0.017 0.023

s o C 0.20 0.33 0.008 0.013

O b D
E
42.42
18.03
43.18
18.80
1.670
0.710
1.700
0.740
e1 2.29 2.79 0.090 0.110
e3 38.1 1.5
eA 14.99 16.00 0.590 0.630
L 3.05 3.81 0.120 0.150
S 1.91 2.79 0.075 0.110
N 32 32

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 M48Z129V Part numbering

6 Part numbering

Table 12. Ordering information scheme

Example: M48Z 129Y –70 PM 1

Device Type
M48Z

Supply voltage and write protect voltage

129V(1) = VCC = 3.0 to 3.6 V; 2.7 V ≤ VPFD ≤ 3.0 V

( s )
Speed
u ct
–85 = 85 ns
o d
P r
Package

e t e
PM = PMDIP32

o l
Temperature range
b s
1 = 0 to 70 °C
- O
(s )
Shipping method
c t
u
blank = ECOPACK® package, tubes

d
r o
e P
1. Device is not recommended for new design. Contact local ST sales office for availability.

For other options, or for more information on any aspect of this device, please contact the

l e t
ST sales office nearest you.

s o
O b

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 Environmental information M48Z129V

7 Environmental information

Figure 12. Recycling symbols

( s )
u ct
o d
P r
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)

te
button cell battery fully encapsulated in the final product.

e
o l
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.

b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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 M48Z129V Revision history

8 Revision history

Table 13. Document revision history

Date Revision Changes
Dec-1999 1 First issue
30-Mar-2000 2 From preliminary data to datasheet
20-Jun-2000 2.1 tGLQX changed for M48Z129Y (Table 3)
Reformatted; temperature information added to tables (Table 7, 8, 3, 4, 9,
14-Sep-2001 3
10)
29-May-2002
02-Apr-2003
3.1
4
Add countries to disclaimer
v2.2 template applied; test condition updated (Table 10)
( s )
18-Feb-2005 5 Reformatted; IR reflow update (Table 5)

u ct
Updated Table 11, 12, footnote 1 of Table 5; added Ecopack® text to
22-Apr-2010 6
Section 5; reformatted document.
o d
23-Jun-2010 7
minor textual changes.
r
Updated Features, Table 11; added Section 7: Environmental information;
P
t e
Devices are not recommended for new design (updated cover page,
e
26-Sep-2011 8
l
Table 12); updated footnote of Table 5: Absolute maximum ratings;

o
updated Section 7: Environmental information; removed M48Z129Y.

b s
- O
(s )
c t
d u
r o
e P
l e t
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 M48Z129V

Please Read Carefully:

( s )
u ct
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

time, without notice.

o d
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

All ST products are sold pursuant to ST’s terms and conditions of sale.
P r
t e
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

e
o l
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

b s
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

- O
(s )
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

c t
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

d u
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

r o
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

P
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

e t e
o l
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

s
liability of ST.

b
O ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

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20/20 Doc ID 5716 Rev 8