A High Performance 180 nm Generation Logic Technology

S. Yang, S. Ahmed, B. Arcot, R.Arghavani, P. Bai, S. Chambers, P. Charvat, R.Cotner,

R. Gasser, T. Ghani, M. Hussein, C. Jan, C. Kardas, J. Maiz', P. McGregor, B. McIntyre, P. Nguyen,
P. Packan*,I. Post, S. Sivakumar, J. Steigerwald, M. Taylor, B. Tufts, S. Tyagi, M. Bohr

Portland Technology Development, ITCAD, 'QRE, Intel Corporation, Hillsboro, OR 97 124

Abstract 560 nm due to the optimized well and trench structure and
low 1.5 V supply voltage. The electrical gate oxide
A 180 nm generation logic technology has been thickness is 3.0 nm as measured at 1.5 V under inversion
developed with high performance 140 nm L G A transistors,
~ conditions. As shown in Figure 3, the dielectric time to fail
six layers of aluminum interconnects and low-& SiOF of the 3.0 nm gate oxide exceeds the requirement for 1.5V
dielectrics. The transistors are optimized for a reduced 1.3- operation with allowed tolerances. Complementary-doped
1.5 V operation to provide high performance and low power. polysilicon is used to form surface-channelN-MOSFETs and
The interconnects feature high aspect ratio metal lines for P-MOSFETs. D W lithography is used to pattern the
low resistance and fluorine doped SiOz inter-level dielectrics polysilicon gate layer down to LGATE dimensions of -140
for reduced capacitance. 16 Mbit SRAMs with a 5.59 pm2 nm. Shallow source-drain extension regions are formed with
6-T cell size have been built on this technology as a yield arsenic for NMOS and boron for PMOS. Halo implants
and reliability test vehicle. (boron and arsenic) are used in both cases for improved short
channel characteristics. Low N+ and P+ junction
Introduction capacitance values of 0.65 and 0.95 fF/pm2 at 0 V are
provided to improve performance and reduce active power.
Advanced logic technologies now lead the industry in Sidewall spacers are formed with CVD Si3N4 deposition
requirements for transistor performance, interconnects and followed by etchback. TiSi2 is selectively formed on
lithographic resolution. Transistor performance still polysilicon and source-drain regions with a nominal sheet
dominates overall microprocessor speed and aggressive gate resistance of 3 Wsq. Worse case sheet resistance of 5 Wsq
oxide and gate length scaling are needed to meet is maintained for poly-Si line widths down to 110 nm as
performance requirements. Power consumption is a growing shown in Figure 4 for poly-Si lines with alternating N+ and
consideration for microprocessors and continued supply P+ doping.
voltage scaling is needed to meet power requirements. High
performance microprocessors are also placing greater
demands on interconnects. Interconnect density
requirements can be met by scaling pitch and adding
additional layers. Interconnect performance and power
needs can be met by using mature aluminum technology with
- __
high aspect ratio metal lines for low resistance and low-e
dielectrics for reduced capacitance. Increases in the amount P-well
,e
, .'.._.__.._______________
, I
,, II
N-well
of on-die cache memory on microprocessors is increasing the
demand for small memory cells while not compromising the
performance of logic circuits.
20
Transistors P+IPW N+/NW

15 -
Figure 1 illustrates the structure of the MOS
transistors and isolations used in this technology. The F lrlri 8.
.
v 0.

transistor process flow starts with P-/P+ epitaxial silicon

wafers followed by the formation of shallow trench isolation. 2 lo
f 0

.
!
0

N-wells are formed with deep phosphorous and shallow 5 - *. 0

arsenic implants, while P-wells are formed with boron t-

implants. The trench isolation is 530 nm deep to provide o ."'.!'.
good intra- and inter-well isolation. The minimum N+ to P+ -400 -300 -200 -100 0 100 200 300 400
spacing is conservatively set at 560 nm, as demonstrated in Spacing (nm)
Figure 2. Latchup is not observed even at spacings less than Fig. 2 P+/Pwell and N+iNwell isolation

8.1.I
0-7803-4774-9/98/$10.00 0 1998 IEEE IEDM 98-197
 1.2
PMOS NMOS

-;U
L0=150nm LO= 130 nm
1 .o 1.5V

n 1E+7 SRAM data h

E 0.8
0
a)
2 1E+6
0.6
m I
n 1E+5
v

n - 0.4
I- 1E+4
Worse 0.2
1 E+3 Case
Field
0.0
1E+2 1 I
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
5 6 7 8 9 1 0 1 1 1 2
VDS (v)
E (MVkm)
Fig. 5 MOSFET I-V curves
Fig. 3 3.0 nm gate oxide TDDB at 125C
1E-02

8 , 1 1E-04
N+/P+ Polysilicon h

5 1E-06
x 5 c I
3
1E-08
-VI

1 E-10

IE-12
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
VGS (v)
100 120 140 160 180 200 Fig. 6 MOSFET subthreshold curves
LGATE
(nm) 0.5
Fig. 4 TiSiz sheet resistance vs. polysilicon line width
0.4 -
MOSFET short channel characteristics are well
n 0.3 -
controlled down to physical gate lengths ( L G A E ) of 130 nm >
v
0-

for NMOS and 150 nm for PMOS due to the use of a thin 3.0 >' 0.2 -
nm gate oxide and careful optimization of source-drain ?
extensions and halo implants. Saturation drive currents at
1.5 V are 0.94 mA/pm for NMOS and 0.42 mA/pm for
PMOS at these LGATEtargets (Figure 5). Saturation
transconductances are 860 and 430 m S / m for NMOS and
O'I
0.0 :
50 100 150
LGATE(nm)
200 250 300

PMOS devices respectively. Subthreshold slopes for both

NMOS and PMOS devices are less than 90 mV/decade at an Fig. 7 NMOS threshold voltage vs. gate length
IOWvalue of 3 nNpm (Figure 6). Short channel threshold
voltage roll-off characteristics are shown in Figures 7 and 8.
0.0

-0.1 -
o
*
w

Threshold voltages at 1.5 V drain bias are 0.30 V for NMOS

at 130 nm LoAm and -0.24 V for PMOS at 150 nm L G A z .
NMOS and PMOS drive current vs. off current
-5 -0.2 -
characteristics are shown in Figure 9. These results are
better than any previously published bulk [1-31 or SO1 [4-51
' -0.3 -
devices. Figure 10 shows inverter gate delay vs. gate length -0.4 r
for unloaded ring oscillators (fan out = 1) operating at 1.3 V
and 1.5 V and at room temperature. The delay per stage at
I
-0.5 ~ ' " " " ' " ' ' " ' " ' " '
Vm = -0.05V
I
minimum gate lengths is <13 psec at 1.3 V and <11 psec at 50 100 150 200 250 300
1.5 V. These fast delays are obtained even with a LGATE(nm)
conservative IOWvalue of 3 nNpm. Fig. 8 PMOS threshold voltage vs. gate length

8.1.2
198-IEDM 98
 1E-07
J LAYER PITCH THICK A.R.
t o o 0%
g- Isolation 520 530
h

E
Polysilicon 480 250
Metal 1 500 480 1.9
;i" 1E-09
Y
Metal 2 , 3 640 700 2.2
U
-k Metal 4 1080 1080 2.0
1E-10 This Work. 1.5V
I Metal 5 1600 1600 2.0
4
pMo/
0

0
Ref p-21.Bulk. 1.5V
A Ref [3]. Bulk. 1.8V
. .
Ref 14-51. Sol. 1.8V
Metal 6 1720 1720 2.0
1E-11 ' ' . ' * ' ' ' . * I nm nm
0.0 0.2 0.4 0.6 0.8 1.0 1.2
IDSAT( m N p m ) Table 1 Layer pitch, thickness and aspect ratio
Fig. 9 MOSFET drive current vs. off current

25 1 I a100 - +AI, 0.18um, this work

c
E -
80
vE
o 60 -
E
iii 40 -
c
20 -

5 !0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
120 130 140 150 160 170 180 190 200 Pitch ( pm)
LGATE(nm)
Fig. 11 Interconnect sheet resistance vs. pitch
Fig. 10 Inverter gate delay per stage vs. L G ~ ~FO=1
E,
The inter-level dielectric between polysilicon and
Interconnects metal 1 is PSG planarized by chemical-mechanical polish.
The inter-level dielectric between the metal layers is HDP
Six metal layers are used to address the increasing
oxide doped with 5.5% fluorine and planarized by chemical-
importance of interconnects to microprocessor performance mechanical polish. Fluorine is added to SiOz to reduce
and density. Contacts and vias are all filled with tungsten dielectric constant and improve interconnect performance
plugs formed with PVD Ti/CVD TiN adhesion layers and
[8, 91. The use of SiOF as an inter-level dielectric reduces
blanket tungsten deposition followed by chemical- the dielectric constant to 3.55 compared to 4.10 for undoped
mechanical polish. The metal stack is Ti/Al-Cu/Ti/TiN HDP and PTEOS oxides. Metal interconnect intensive ring
which provides low line resistance, good electromigration oscillators were used to quantify the speed benefit of SiOF
and low via resistance. The pitches and thicknesses of the ILD. A M2/M3/M4 sandwich structure with interdigitated
interconnect layers are summarized in Table 1. Aggressive M3 lines sandwiched between planes of M2 and M4 was
metal aspect ratios (thicknedwidth) are used to provide low used to test total M3 line capacitance. A M3 isolated
interconnect resistance at tight pitches. Figure 11 structure with interdigitated M3 lines and no M2 or M4
summarizes a study that compares the metal sheet resistance planes was used to test lateral M3-M3 line capacitance. As
vs. pitch for this technology to Intel's previous 0.25 pm shown in Table 2, ring oscillator frequencies showed an
technology [6] and to a recent copper interconnect increase of 16% for the sandwich structure and 14% for the
technology [7]. For a given pitch, this aluminum technology isolated structure with the use of SiOF. The fact that SiOF
has a lower sheet rho than any reported to date. M1 pitch is improves the performance of both isolated and sandwich
tight for optimal density as a local interconnect and for a structures indicates that it is effective in improving both in-
small 6-T SRAM cell size. M2 and M3 use an intermediate plane and out-of-plane capacitance. The ILD capacitance
pitch to optimize both density and performance. M4, M5 reduction is important for both improving interconnect
and M6 use increased pitches and thicknesses to optimize performance and for reducing chip active power. A cross-
for low resistance and for fast signal propagation. The section of the interconnects used on this process is shown in
process uses a total of 21 masking layers, combining DUV Figure 12.
for critical layers and I-line for non-critical layers.

8.1.3
IEDM 98-199
 Dielectric M 2 N 3 N 4 M3
Constant Sandwich Isolated

HDP Si% 4.10 -- -_

PTEOS 4.10 +0% +5%
HDPSiOF 3.55 +16% +14%
& RO incr. RO incr.

Table 2 ILD effects on E and ring oscillator frequency

Fig. 13 5.59 pm2 6-T SRAM cell at poly gate layer (left)
M6 and metal 1 (right)

M5

M4

M3

M2 Fig. 14 16 Mbit SRAM die photo, 14.25 x 14.55 mm

M1
Conclusion

A 180 nm generation logic technology has been

developed and demonstrated with high performance,
reduced power transistors. Aluminum interconnects with
Fig. 12 Process cross-section IOW-ESiOF dielectrics are used to meet interconnect density
and performance requirements. The technology yield and
16 Mbit SRAM performance capabilities have been demonstrated on a 16
Mbit SRAM which operates at >900 MHz..
A 16 Mbit CMOS SRAM has been designed and
fabricated on this technology with high yields. This SRAM Acknowledgment
is used as a yield and reliability test vehicle during process
development and to test and refine the SRAM cell and The authors would like to acknowledge the hundreds
support circuitry to be used in logic products. A 6-T of people in Intel who contributed to this technology
memory cell is used with dimensions of 2.22 x 2.52 pm and development effort.
an area of 5.59 pm2. Figure 13 shows top views of the cell
after polysilicon and metal 1 layer processing. Three layers References
of metal are needed to make the SRAM cell functional: MI
for internal hook-ups and VDD strapping, M2 for bitlines 111 M. Rodder, et al., IEDM Tech. Digest (1997) p. 223.
and VSS strapping, and M3 for wordline strapping. M4, 121 I. Yang, et al., Symposium VLSI Technology (1998) p. 148.
M5 and M6 are added to the cell as redundant VDD,Vss and 131 L. Su, et al., Symposium VLSI Technology (1996) p. 12.
wordline straps to make the 16 Mbit SRAM an appropriate [41 F. Assaderaghi, et al., IEDM Tech. Digest (1997) p. 415.
process development vehicle for a 6-layer logic technology. 151 D. Schepis, et al., IEDM Tech. Digest (1997) p. 587.
The 16 Mbit SRAM die size is 207 mm2 and a die photo is 161 M. Bohr, et al., IEDM Tech. Digest (1996) p. 847.
shown in Figure 14. The SRAM operates at >900 MHz at 171 D. Edelstein, et al., ZEDM Tech. Digest (1997) p. 773.
1.5 V. P I H. Oyamatsu, et al., IEDM Tech. Digest (1995) p. 705.
P I G. Lucovsky and H. Yang,Mat. Res. Soc. Symp. Proc., vol.
443 (1997)~.111.

8.1.4
200-IEDM 98