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HDL Design Lec1 1613730817095

This document provides an overview of Verilog HDL design in 3 sessions. It defines Verilog HDL as a hardware description language used to model and design digital circuits. It describes that Verilog allows modeling at different levels of abstraction from behavioral/procedural to gate level. It also explains that Verilog allows concurrency and mixed abstraction levels in a single design. It provides an example to demonstrate structural, dataflow, and behavioral modeling in Verilog.

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Shashwat Kanhaiya
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40 views

HDL Design Lec1 1613730817095

This document provides an overview of Verilog HDL design in 3 sessions. It defines Verilog HDL as a hardware description language used to model and design digital circuits. It describes that Verilog allows modeling at different levels of abstraction from behavioral/procedural to gate level. It also explains that Verilog allows concurrency and mixed abstraction levels in a single design. It provides an example to demonstrate structural, dataflow, and behavioral modeling in Verilog.

Uploaded by

Shashwat Kanhaiya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Overview of Verilog HDL Design

Session 1
BITS Pilani Pawan Sharma
Pilani Campus [email protected]
WHAT IS VERILOG HDL??
 Verilog is a Hardware Description Language
and NOT a software programming language
(Language which can be translated into
machine instructions and then executed on
a computer)
 Its HDL (Language with syntactic and
semantic support for modeling the
temporal behavior and spatial structure of
hardware)
Why an HDL is not a Programming Language

• In a program, we start at the beginning (e.g. “main”), and we proceed


sequentially through the code as directed
• The program represents an algorithm, a step-by-step sequence of actions to
solve some problem
for (i = 0; i<10; i=i+1) {
if (newPattern == oldPattern[i]) match = i;
}
• Hardware is all active at once; there is no starting point
Pitfalls of trying to “program” in Verilog
• If you program sequentially, the synthesizer may add a lot of
hardware to try to do what you say
– In last example, need a priority encoder
• If you program in parallel (multiple “always” blocks), you can get
non-deterministic execution
– Which “always” happens first?
• You create lots of state that you didn’t intend
if (x == 1) out = 0;
if (y == 1) out = 1; // else out retains previous state? R-S latch!
• You don’t realize how much hardware you’re specifying
– x = x + 1 can be a LOT of hardware
• Slight changes may suddenly make your code “blow up”
– A chip that previously fit suddenly is too large or slow
WHAT IS VERILOG HDL??
– Developed by Gateway Design Automation, 1986. Acquired by
Cadence in 1990.
– One formal language for all aspects of logic design. Familiar
language conventions similar to C.
– Describe digital electronic systems at multiple levels of abstraction
• Behavioral/Procedural: Module’s high-level algorithm is
implemented with little concern for the actual hardware
• Dataflow/Functional: Module is implemented by specifying how
data flows between registers
• Structural/Gate Level: Module is implemented in terms of
concrete logic gates (AND, OR, NOT) and their interconnections
• Switch/Transistor Level: This is the lowest level of abstraction
provided by Verilog. A module can be implemented in terms of
switches, storage nodes, and the interconnections between
them.

5
WHAT IS VERILOG HDL??
• Verilog allows the designer to mix and match all four levels of
abstractions in a design
• Model the simulation, synthesis and timing of the systems
• Designers can create lower-level models from the higher-level
models either manually or automatically
• The process of automatically generating a gate-level model from
either a dataflow or a behavioral model is called Logic Synthesis
• Express the concurrency of the system operation, Test the
systems, Case sensitive, Design documentation
• Allows designers to talk about what the hardware should do
without actually designing the hardware itself,
• HDLs allow designers to separate behavior from implementation
at various levels of abstraction

6
WHAT IS VERILOG HDL??
• Designers can develop an executable functional
specification that documents the exact behavior
of all the components and their interfaces
• Designers can make decisions about cost,
performance, power, and area earlier in the
design process
• Designers can create tools which automatically
manipulate the design for verification, synthesis,
optimization, etc.
7
WHAT IS VERILOG HDL??
• Verilog 2001, standard IEEE 1364-2001 fixed many
shortcomings Verilog 95 had
• System Verilog is a super-set of Verilog 2001
• System Verilog born from the need to unify design and
verification
• Adds VHDL features and design verification
improvements
• Both Verilog and VHDL have analog extensions VHDL-A
and Verilog-AMS

8
Simulator
• Verilog simulators –
– Cadence NC Verilog-XL
– Verilog Compiled Simulator (VCS) from Chronologic:
very successful. VCS eventually bought by
Synopsys
– Modelsim (Mentor), a very good mixed language
simulator
– Icarus Verilog [open source] (not fully 1356-2001
compliant)
– Vivado from Xilinx for complete FPGA design flow,
ISE webpack (open source)
9
Example
F = (in1 AND in2) OR (in3 AND in4)

//Structural //Behavioral
module and_or (out,in1, in2, in3, in4); module and_or (out,in1, in2, in3, in4);
input in1, in2, in3, in4; input in1, in2, in3, in4;
output out; output out;
wire tmp,tmp1; reg out;
and #10 u1 (tmp, in1, in2), u2 (tmp1, in3, in4);
or #20 (out, tmp, tmp1); always @(in1 or in2 or in3 or in4)
endmodule begin
if (in1 & in2)
//Data flow out = #30 1;
module and_or (out,in1, in2, in3, in4); else
input in1, in2, in3, in4; out = #30 (in3 & in4);
output out; end
wire tmp; endmodule
assign #10 tmp = in1 & in2;
wire #10 tmp1= in3 & in4;
assign #20 out = tmp | tmp1;
/*The three statements could be condensed
into one*/
//assign #30 out = (in1 & in2) | (in3 & in4);
endmodule

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