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Digital Lab Cs 6211 VHDL Programs

The document contains VHDL code for several basic combinational and sequential logic circuits including half adders, full adders, multiplexers, demultiplexers, encoders, decoders, parallel adders, parity checkers, flip flops, counters, and more. Each code example is accompanied by its corresponding waveform diagram.

Uploaded by

Murugan G
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
130 views

Digital Lab Cs 6211 VHDL Programs

The document contains VHDL code for several basic combinational and sequential logic circuits including half adders, full adders, multiplexers, demultiplexers, encoders, decoders, parallel adders, parity checkers, flip flops, counters, and more. Each code example is accompanied by its corresponding waveform diagram.

Uploaded by

Murugan G
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL Code for a Half-Adder

VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port(a,b:in bit; sum,carry:out bit);
end half_adder;

architecture data of half_adder is


begin
sum<= a xor b;
carry <= a and b;
end data;

Waveforms

VHDL Code for a Full Adder


Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);


end full_adder;

architecture data of full_adder is


begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;

Waveforms
VHDL Code for a Half-Subtractor
Library ieee;
use ieee.std_logic_1164.all;

entity half_sub is
port(a,c:in bit; d,b:out bit);
end half_sub;

architecture data of half_sub is


begin
d<= a xor c;
b<= (a and (not c));
end data;

Waveforms

VHDL Code for a Full Subtractor


Library ieee;
use ieee.std_logic_1164.all;

entity full_sub is
port(a,b,c:in bit; sub,borrow:out bit);
end full_sub;

architecture data of full_sub is


begin
sub<= a xor b xor c;
borrow <= ((b xor c) and (not a)) or (b and c);
end data;
Waveforms

VHDL Code for a Multiplexer


Library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(S1,S0,D0,D1,D2,D3:in bit; Y:out bit);
end mux;

architecture data of mux is


begin
Y<= (not S0 and not S1 and D0) or
(S0 and not S1 and D1) or
(not S0 and S1 and D2) or
(S0 and S1 and D3);
end data;

Waveforms

VHDL Code for a Demultiplexer


Library ieee;
use ieee.std_logic_1164.all;

entity demux is
port(S1,S0,D:in bit; Y0,Y1,Y2,Y3:out bit);
end demux;
architecture data of demux is
begin
Y0<= ((Not S0) and (Not S1) and D);
Y1<= ((Not S0) and S1 and D);
Y2<= (S0 and (Not S1) and D);
Y3<= (S0 and S1 and D);
end data;

Waveforms

VHDL Code for a 8 x 3 Encoder


library ieee;
use ieee.std_logic_1164.all;

entity enc is
port(i0,i1,i2,i3,i4,i5,i6,i7:in bit; o0,o1,o2: out bit);
end enc;

architecture vcgandhi of enc is


begin
o0<=i4 or i5 or i6 or i7;
o1<=i2 or i3 or i6 or i7;
o2<=i1 or i3 or i5 or i7;
end vcgandhi;

Waveforms
VHDL Code for a 3 x 8 Decoder
library ieee;
use ieee.std_logic_1164.all;

entity dec is
port(i0,i1,i2:in bit; o0,o1,o2,o3,o4,o5,o6,o7: out bit);
end dec;

architecture vcgandhi of dec is


begin
o0<=(not i0) and (not i1) and (not i2);
o1<=(not i0) and (not i1) and i2;
o2<=(not i0) and i1 and (not i2);
o3<=(not i0) and i1 and i2;
o4<=i0 and (not i1) and (not i2);
o5<=i0 and (not i1) and i2;
o6<=i0 and i1 and (not i2);
o7<=i0 and i1 and i2;
end vcgandhi;

Waveforms

VHDL Code – 4 bit Parallel adder


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity pa is
port(a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
ca : out STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0)
);
end pa;

architecture vcgandhi of pa is
Component fa is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
ca : out STD_LOGIC
);
end component;
signal s : std_logic_vector (2 downto 0);
signal temp: std_logic;
begin
temp<='0';
u0 : fa port map (a(0),b(0),temp,sum(0),s(0));
u1 : fa port map (a(1),b(1),s(0),sum(1),s(1));
u2 : fa port map (a(2),b(2),s(1),sum(2),s(2));
ue : fa port map (a(3),b(3),s(2),sum(3),ca);
end vcgandhi;

Waveforms

VHDL Code – 4 bit Parity Checker


library ieee;
use ieee.std_logic_1164.all;

entity parity_checker is
port (a0,a1,a2,a3 : in std_logic;
p : out std_logic);
end parity_checker;

architecture vcgandhi of parity_checker is


begin
p <= (((a0 xor a1) xor a2) xor a3);
end vcgandhi;

Waveforms
VHDL Code – 4 bit Parity Generator
library ieee;
use ieee.std_logic_1164.all;

entity paritygen is
port (a0, a1, a2, a3: in std_logic; p_odd, p_even: out std_logic);
end paritygen;

architecture vcgandhi of paritygen is


begin
process (a0, a1, a2, a3)

if (a0 ='0' and a1 ='0' and a2 ='0' and a3 =’0’)


then odd_out <= "0";
even_out <= "0";
else
p_odd <= (((a0 xor a1) xor a2) xor a3);
p_even <= not(((a0 xor a1) xor a2) xor a3);
end vcgandhi

Waveforms
This chapter explains how to do VHDL programming for Sequential Circuits.

VHDL Code for an SR Latch


library ieee;
use ieee.std_logic_1164.all;

entity srl is
port(r,s:in bit; q,qbar:buffer bit);
end srl;

architecture virat of srl is


signal s1,r1:bit;
begin
q<= s nand qbar;
qbar<= r nand q;
end virat;

Waveforms

VHDL Code for a D Latch


library ieee;
use ieee.std_logic_1164.all;

entity Dl is
port(d:in bit; q,qbar:buffer bit);
end Dl;

architecture virat of Dl is
signal s1,r1:bit;
begin
q<= d nand qbar;
qbar<= d nand q;
end virat;

Waveforms
VHDL Code for an SR Flip Flop
library ieee;
use ieee.std_logic_1164.all;

entity srflip is
port(r,s,clk:in bit; q,qbar:buffer bit);
end srflip;

architecture virat of srflip is


signal s1,r1:bit;
begin
s1<=s nand clk;
r1<=r nand clk;
q<= s1 nand qbar;
qbar<= r1 nand q;
end virat;

Waveforms

VHDL code for a JK Flip Flop


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity jk is
port(
j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC
);
end jk;

architecture virat of jk is
begin
jkff : process (j,k,clk,reset) is
variable m : std_logic := '0';

begin
if (reset = '1') then
m : = '0';
elsif (rising_edge (clk)) then
if (j/ = k) then
m : = j;
elsif (j = '1' and k = '1') then
m : = not m;
end if;
end if;

q <= m;
qb <= not m;
end process jkff;
end virat;

Waveforms

VHDL Code for a D Flip Flop


Library ieee;
use ieee.std_logic_1164.all;

entity dflip is
port(d,clk:in bit; q,qbar:buffer bit);
end dflip;

architecture virat of dflip is


signal d1,d2:bit;
begin
d1<=d nand clk;
d2<=(not d) nand clk;
q<= d1 nand qbar;
qbar<= d2 nand q;
end virat;
Waveforms

VHDL Code for a T Flip Flop


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Toggle_flip_flop is
port(
t : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end Toggle_flip_flop;

architecture virat of Toggle_flip_flop is


begin
tff : process (t,clk,reset) is
variable m : std_logic : = '0';

begin
if (reset = '1') then
m : = '0';
elsif (rising_edge (clk)) then
if (t = '1') then
m : = not m;
end if;
end if;
dout < = m;
end process tff;
end virat;
Waveforms

VHDL Code for a 4 - bit Up Counter


library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end counter;

architecture virat of counter is


signal tmp: std_logic_vector(3 downto 0);
begin
process (Clock, CLR)

begin
if (CLR = '1') then
tmp < = "0000";
elsif (Clock'event and Clock = '1') then
mp <= tmp + 1;
end if;
end process;
Q <= tmp;
end virat;

Waveforms

VHDL Code for a 4-bit Down Counter


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dcounter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end dcounter;

architecture virat of dcounter is


signal tmp: std_logic_vector(3 downto 0);

begin
process (Clock, CLR)
begin
if (CLR = '1') then
tmp <= "1111";
elsif (Clock'event and Clock = '1') then
tmp <= tmp - 1;
end if;
end process;
Q <= tmp;
end virat;

Waveforms

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