Power Consumption and Chip Area Reduction Techniques For Mb-Ofdm Uwb Rfics
Power Consumption and Chip Area Reduction Techniques For Mb-Ofdm Uwb Rfics
specifications call for a moderate (-106dBc/Hz at 1MHz the tank frequency. At power-up for each sub-band a control
offset) phase noise performance, while the transmit PSD mask word is searched and stored such that the oscillation frequency
requires the spur level to be less than -20dBc in adjacent sub- matches the sub-band. This makes the system a DILO. The
bands [6]. divide-by-2 circuit is a conventional CML divider. Output
The required ability of hopping from one channel frequency buffers are included for measurement purposes. Prototypes of
to the other within 9ns prevents the use of a conventional the designed circuit are implemented in a digital 90nm CMOS
approach based on a single wideband PLL. Single-sideband technology and assembled in chip-on-board fashion for
(SSB) mixers can be used to offset a fixed frequency to testing. A micrograph of the chip is shown in Fig.2. Within the
simultaneously generate the required carriers which are same pad ring two versions of the circuit are laid out. Wider
dynamically selected by a multiplexer [2, 3]. This approach, injection devices, namely W=120μm, are used in DILO-L,
however, in CMOS requires a huge power consumption to while 80μm wide transistors are employed in DILO-S. In any
achieve low spurious [3]. Another possibility is to use an array case, the active area is only 0.074 mm2.
of PLLs [1, 4], leading to a large area.
For PCCAR, we have selected the system concept based on
sub-harmonic injection locking [5]. A simplified schematic of
the implemented circuit is shown in Fig.1. An LC oscillator,
operated at twice the desired frequency to avoid TX frequency
pulling, is injection locked to the k-th harmonic of a 528MHz
reference. This basically allows generating all 14 LO
frequencies required by WiMedia. The oscillator is followed
by a divide-by-2 circuit to generate the desired frequency as
well as quadrature phases. The locking range is narrower than
the reference frequency to guarantee a unique locking
condition. Changing the natural frequency of the LC tank, the
oscillator locks to another harmonic, corresponding to a
different UWB channel frequency, thus all band groups can be
covered with only one oscillator.
70
PROCEEDINGS OF THE 2008 IEEE INTERNATIONAL CONFERENCE ON ULTRA-WIDEBAND (ICUWB2008), VOL. 2
III. PCCAR ON TRANSISTOR LEVEL which is not for the bandgroup1 PHY implementations,
because the LO buffer should have small input capacitance
A. Proposals for PCCAR on Transistor Level (small transistor), on the other hand it should have 6dB
Innovations on transistor level can also have significant voltage gain to provide sufficient LO swing to drive the IQ
contributions in PCCAR. For MB-OFDM UWB RFICs, the modulator.
main causes for high power consumption and big chip area are
the following: CTRL
a) High operating frequency; circuits with resistive load 3-WIRE BUS REG
operated at higher frequency draw considerably more DC
current; BBI
PA
DIV
voltage mode signal processing, many redundant V-to-I
and I-to-V conversions are used. QLO
RFN
To tackle with these problems, we have the following QMIX
proposals:
BBQ RF TX
1) Use active inductor load to replace resistive load, if
feasible; Fig. 3. UWB RF transmitter block diagram.
2) Use stacked inductor to replace single-layer inductor;
3) Use low-voltage low-power V-to-I converter and current- In this design, a wide band LO buffer using differential pair
mode circuits for analog baseband signal processing; with active inductor load is used for the first LO buffer to
Based on these proposals, a low-power UWB RF transmitter is provide 6dB gain while having relatively small input
designed and fabricated in a 90nm digital CMOS technology transistors (40um/90nm in this design). The active inductor
[11]. The detailed implementation is presented in the boosts signal at high frequency by more than 4dB compared to
following subsection. the resistive load and it saves chip area significantly compared
B. PCCAR in UWB RF Transmitter to the passive inductor. In addition to this, the LO buffer with
active inductor load is robust in gain and frequency behavior
The block diagram of the UWB RF transmitter is shown in
because both its input and load FETs are the same type of
Fig.3. It consists of IQ divider, LO buffers, IQ modulator and
transistors. By using this type of LO buffer, power
RF power amplifier and 3-wire bus control logic. The IQ
consumption and chip area is reduced significantly in this
divider divides the input clock (12-18GHz) by 2 and generates
UWB transmitter.
In-phase (I) and Quadrature (Q) LO signals, then the IQ LO
For low-voltage operation and to get relatively high
signal is amplified and buffered to the IQ modulator. The IQ
conversion gain at high frequencies, passive inductor load has
modulator consists of I and Q path Gilbert-type up-conversion
to be used in this mixer. In order to save chip area, stacked
mixers which get IQ analog baseband signal from external
inductors are used. The 0.8nH stacked inductor has a
signal source. Outputs of the mixers are combined to a
dimension of 50um*30um, which is only 15% percent of a
differential RF signal and fed to the RF power amplifier,
non-stacked inductor with the same inductance. To get 3GHz
whose differential outputs are connected to RF measurement
bandwidth, Q of the inductor is further reduced by a parallel
equipments via an external BALUN. A 3-wire bus control
resistor R1. For calibration of LO leakage, artificial DC offset
logic is implemented to control gain settings in the power
current is added to the converted baseband current by using 6
amplifier, power down and sleep mode in all of the blocks.
bits programmable current sources.
The IQ divider is a CML latch with resistive load. Main
In the up-conversion mixer a low-power low-voltage V-to-I
design challenge is to meet stringent IQ phase matching
converter is used. This mixer is very robust in linearity
requirement of less than 1°, which is derived from the system
because of the feedback loop used in the V-to-I converter; and
requirement on the image rejection ratio. The matching
it is also very robust in conversion gain which is mainly
requirement leads to relatively large devices in the divider,
determined by the dimension ratio of the same type NMOS
consequently big parasitics; furthermore the high operating
transistors (assuming LO swing is fixed).
frequency makes the IQ divider sensitive to the capacitive load
The fabricated transmitter chip is bonded to a PCB for RF
and parasitic capacitances at internal nodes. So special
measurements. The differential LO inputs are connected to an
attentions are paid in both design and layout to get good
RF signal generator via a BALUN. The differential RF outputs
matching and minimize parasitics. The low-pass poles at the
are combined to RF measurement equipments via another
IQ divider output nodes are designed to above 12GHz to avoid
BALUN. After de-embedding, the measurement results show
sharp roll-off at 9GHz, thus the resistor value is rather small
a maximum output power of -5.7dBm, which is sufficient for
(100 Ohms), and this leads to small LO swing. With these
short-range applications. At the maximum output power, this
constraints, design of the LO buffers becomes a challenge
RF transmitter has -33.8dBc sideband rejection; without
71
PROCEEDINGS OF THE 2008 IEEE INTERNATIONAL CONFERENCE ON ULTRA-WIDEBAND (ICUWB2008), VOL. 2
calibration, it has -35.2dBc LO leakage, after calibration, the in 90nm CMOS technology, we demonstrate that significant
LO leakage is suppressed to -47.07dBc. Two-tone test was power consumption and chip area reduction can be achieved
done at 7.5GHz LO signal, with 33MHz and 30MHz two-tone by using innovative system concept and transistor level design
baseband signals, the measured OIP3 value is -1.41dBm. The techniques.
in-band ripple at maximum output power is less than 1dB
from 6GHz to 8GHz, however it drops by another 2dB from ACKNOWLEDGMENT
8GHz to 9GHz. The main reason for the roll-off at high The authors would like to thank Michael Wassermann,
frequency is the parasitics from the bonding wires and PCB. Sylvia Michaelis, Dietrich Michaelis, Sven Derksen and
1mm
Florian Michl for their assistances and supports.
REFERENCES
[1] B. Razavi et al., “A 0.13m CMOS UWB Transceiver, ” in Proc.
International Solid-State Circuit Conf., 2005, pp. 216-217.
[2] C. Liang et al., “A 14-band Frequency Synthesizer for MB-OFDM
UWB Application, ” in Proc International Solid-State Circuit Conf.
0.75mm
Zisan Zhang received the B.Sc., M.Sc., and Ph.D degrees in electrical
engineering from Jilin University China, Changchun, China, in 1995, 1998,
IV. CONCLUSION and 2001, respectively. In 2005, he received his second Ph.D. degree in
electrical engineering from the University of Duisburg-Essen, Duisburg,
To be successful in the marketplace, next-generation MB- Germany.
OFDM UWB chips with world-wide interoperability must be From 2001 to 2004, he worked in Fraunhofer Institute of Microelectronic
Circuits and Systems in Duisburg, Germany. Since September 2004, he has
optimized for low power consumption and small chip area. been with Infineon Technologies Austria AG in Villach, Austria
Using the latest deep submicron CMOS technology can reduce Dr. Zhang holds 2 US patents, 2 outstanding awards in "Science &
power consumption and chip area in digital circuits, but it is Technology advances" in 2002 and 2004 respectively in China, and 18 Journal
and conference papers. His research interests include Analog and RF circuit
not in favor of RF and analog performance. In this paper, with design, RF wireless transceiver design, CAD for analog and RF circuits.
some low-power high performance MB-OFDM UWB RF ICs
72