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Lab Assignment 10 Sequential Circuits and 7 Segment Displays

Lab assignment digital systems

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61 views

Lab Assignment 10 Sequential Circuits and 7 Segment Displays

Lab assignment digital systems

Uploaded by

Sa
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Lab Assignment 10

Sequential Circuits and


7-Segment Displays

A seven-segment display is a form of electronic display device for display-


ing decimal numerals that is an alternative to the more complex dot matrix
displays. Seven-segment displays are widely used in digital clocks, electronic
meters, basic calculators, and other electronic devices that display numerical
information [https://en.wikipedia.org/wiki/Seven-segment_display].

Figure 1: A block diagram of the circuit.

1 Lab Tasks
a) The customer asks you to build a circuit to display different numbers (0 to
7) on a seven-segment display. The circuit has the modular diagram shown in
Figure 1. The user stores the number to display on first seven-segment display
The lab manual is exclusively for the students of the University of Engineering and Tech-
nology, Lahore.
©2020 UET Lahore.

1
by choosing sel = 2’b00, num in = desired number and turning the switch
wr ON and then OFF. Similarly, the user stores the numbers to display on other
three seven-segment display by following the same method except choosing a
different memory location with the help of sel signal. At the end of the writing
process, with WR=0, all the seven-segment displays should show all the stored
numbers at the same time.
Table 1 explains the operations in the circuit in more detail. We will first use
the write operation to store the four values corresponding to different seven-
segment displays. After the write operation, we will read the stored numbers
using WR=0 only.

Table 1: Input/Output Truth Table


OPERATION RESET SEL WR DATA D1 D2 D3 D4
RESET OPERATION 1 XX 0 X 0 0 0 0
0 00 1 1 1 OFF OFF OFF
0 01 1 2 OFF 2 OFF OFF
WITE OPERATION
0 10 1 3 OFF OFF 3 OFF
0 11 1 4 OFF OFF OFF 4
READ OPERATION 0 XX 0 X 1 2 3 4

All the seven-segment displays share the same data wires. Therefore, at any
point in time, we are limited to display only one number on a single display.
However, if we enable different seven-segment displays fast enough, it can create
an illusion that all seven-segment displays are turned ON. Human eyes cannot
perceive that a display is turning ON and OFF if this switching happens for
more than 24 times a second. To be on the safe side, you can switch different
displays ON and OFF at a rate of 100 times per second (100 Hz).
The lab requires that the circuit should have a time reference in it. The FPGA
board provides an on board clock signal of 50 MHz. However, if you make a
circuit that switches different seven-segment displays at a rate of 50M times per
second, the seven-segment display drivers may not be able to respond to such
a high frequency change. Therefore, you will need to bring the clock down to
approximately 100 Hz as discussed above (Hint: To bring the clock down to 100
Hz from 50 MHz, you may be able to use a toggle flip-flop in a clever way. Look
at the output of a toggle flip-flop carefully.).
b) Design a test-bench for the circuit of part (a). The test bench should simulate
every possible input combination. For example, in the start of the test bench,
try writing to all memory locations and then start the read operation instead
of iterating through all the possible input data patterns.
c) Develop a proper “layout” and “format” for the simulated waveform. If
needed, use multiple screen captures to make the 6-bit output patterns visible.
To get full credits, the input and output signals should be properly arranged
and represented in a proper format so that the simulation result can be easily
understood.

2
2 Instructions
a) Prepare a report for everything that you have done in “Lab Tasks”. The
report should include the following:
• A hand-sketched design partition of the system. The design partition
should include multiplexers, demultiplexers, encoders, decoders, flip-flops,
and should avoid gates as much as possible.

• Verilog code for the main module named as lab10 seq 7seg.
• Verilog code for the test-bench tb lab10 seq 7seg.
• Screen captures of ModelSim simulation waveform (you must include your
registration number on the top right side of every capture).

b) The collaboration between students is encouraged, but blind copying or shar-


ing the simulation and report is not allowed. I can randomly ask a student during
the teams meeting session to explain about his/her work. If you are unable to
explain anything in your work, it will be assumed you have copied it and you
may be awarded a zero grade for the lab. So make sure you know everything
that you have done. I am least concerned about how you have learnt something
as long as you have learnt it well.

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