PIC18F2458/2553/4458/4553

Data Sheet
28/40/44-Pin High-Performance,
Enhanced Flash, USB Microcontrollers
with 12-Bit A/D and nanoWatt Technology

© 2007 Microchip Technology Inc. Preliminary DS39887B

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
ensure that your application meets with your specifications.
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
MICROCHIP MAKES NO REPRESENTATIONS OR
registered trademarks of Microchip Technology Incorporated
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
QUALITY, PERFORMANCE, MERCHANTABILITY OR Embedded Control Solutions Company are registered
FITNESS FOR PURPOSE. Microchip disclaims all liability trademarks of Microchip Technology Incorporated in the
arising from this information and its use. Use of Microchip U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS39887B-page ii Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
28/40/44-Pin High-Performance, Enhanced Flash, USB
Microcontrollers with 12-Bit A/D and nanoWatt Technology
Universal Serial Bus Features: Flexible Oscillator Structure:
• USB V2.0 Compliant • Four Crystal modes, Including High-Precision PLL
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) for USB
• Supports Control, Interrupt, Isochronous and Bulk • Two External Clock modes, up to 48 MHz
Transfers • Internal Oscillator Block:
• Supports up to 32 Endpoints (16 bidirectional) - 8 user-selectable frequencies, from 31 kHz
• 1-Kbyte Dual Access RAM for USB to 8 MHz
• On-Chip USB Transceiver with On-Chip Voltage - User-tunable to compensate for frequency drift
Regulator • Secondary Oscillator using Timer1 @ 32 kHz
• Interface for Off-Chip USB Transceiver • Dual Oscillator Options allow Microcontroller and
• Streaming Parallel Port (SPP) for USB Streaming USB module to Run at Different Clock Speeds
Transfers (40/44-pin devices only) • Fail-Safe Clock Monitor:
Power-Managed Modes: - Allows for safe shutdown if any clock stops
• Run: CPU On, Peripherals On Peripheral Highlights:
• Idle: CPU Off, Peripherals On • High-Current Sink/Source: 25 mA/25 mA
• Sleep: CPU Off, Peripherals Off • Three External Interrupts
• Idle mode Currents Down to 5.8 μA Typical • Four Timer modules (Timer0 to Timer3)
• Sleep mode Currents Down to 0.1 μA Typical • Up to 2 Capture/Compare/PWM (CCP) modules:
• Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V - Capture is 16-bit, max. resolution 5.2 ns (TCY/16)
• Watchdog Timer: 2.1 μA Typical - Compare is 16-bit, max. resolution 83.3 ns (TCY)
• Two-Speed Oscillator Start-up - PWM output: PWM resolution is 1 to 10-bits
Special Microcontroller Features: • Enhanced Capture/Compare/PWM (ECCP) module:
• C Compiler Optimized Architecture with Optional - Multiple output modes
Extended Instruction Set - Selectable polarity
• 100,000 Erase/Write Cycle Enhanced Flash - Programmable dead time
Program Memory Typical - Auto-shutdown and auto-restart
• 1,000,000 Erase/Write Cycle Data EEPROM • Enhanced USART module:
Memory Typical - LIN bus support
• Flash/Data EEPROM Retention: > 40 Years • Master Synchronous Serial Port (MSSP) module
• Self-Programmable under Software Control supporting 3-wire SPI (all 4 modes) and I2C™
• Priority Levels for Interrupts Master and Slave modes
• 8 x 8 Single-Cycle Hardware Multiplier • 12-Bit, up to 13-Channel Analog-to-Digital Converter
• Extended Watchdog Timer (WDT): module (A/D) with Programmable Acquisition Time
- Programmable period from 41 ms to 131s • Dual Analog Comparators with Input Multiplexing
• Programmable Code Protection Note: This document is supplemented by
• Single-Supply 5V In-Circuit Serial the “PIC18F2455/2550/4455/4550 Data
Programming™ (ICSP™) via Two Pins Sheet” (DS39632). See Section 1.0
• In-Circuit Debug (ICD) via Two Pins
“Device Overview”.
• Optional Dedicated ICD/ICSP Port (44-pin TQFP
package only)
• Wide Operating Voltage Range (2.0V to 5.5V)
EUSART

Program Memory Data Memory MSSP

Comp.

12-Bit CCP/ECCP Timers

Device Flash # Single-Word SRAM EEPROM I/O A/D (ch) SPP Master
(PWM) SPI 8/16-Bit
(bytes) Instructions (bytes) (bytes) I2C™
PIC18F2458 24K 12288
24 10 2/0 No
PIC18F2553 32K 16384
2048 256 Y Y 1 2 1/3
PIC18F4458 24K 12288
35 13 1/1 Yes
PIC18F4553 32K 16384

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 1

PIC18F2458/2553/4458/4553
Pin Diagrams

28-Pin SPDIP, SOIC

MCLR/VPP/RE3 1 28 RB7/KBI3/PGD
RA0/AN0 2 27 RB6/KBI2/PGC
RA1/AN1 3 26 RB5/KBI1/PGM
RA2/AN2/VREF-/CVREF 4 25 RB4/AN11/KBI0
RA3/AN3/VREF+ 5 RB3/AN9/CCP2(1)/VPO

PIC18F2553
24

PIC18F2458
RA4/T0CKI/C1OUT/RCV 6 23 RB2/AN8/INT2/VMO
RA5/AN4/SS/HLVDIN/C2OUT 7 22 RB1/AN10/INT1/SCK/SCL
VSS 8 21 RB0/AN12/INT0/FLT0/SDI/SDA
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RA6 10 19 VSS
RC0/T1OSO/T13CKI 11 18 RC7/RX/DT/SDO
RC1/T1OSI/CCP2(1)/UOE 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/D+/VP
VUSB 14 15 RC4/D-/VM

40-Pin PDIP

MCLR/VPP/RE3 1 40 RB7/KBI3/PGD
RA0/AN0 2 39 RB6/KBI2/PGC
RA1/AN1 3 38 RB5/KBI1/PGM
RA2/AN2/VREF-/CVREF 4 37 RB4/AN11/KBI0/CSSPP
RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2(1)/VPO
RA4/T0CKI/C1OUT/RCV 6 35 RB2/AN8/INT2/VMO
RA5/AN4/SS/HLVDIN/C2OUT 7 34 RB1/AN10/INT1/SCK/SCL
33 RB0/AN12/INT0/FLT0/SDI/SDA
PIC18F4458
PIC18F4553

RE0/AN5/CK1SPP 8
RE1/AN6/CK2SPP 9 32 VDD
RE2/AN7/OESPP 10 31 VSS
VDD 11 30 RD7/SPP7/P1D
VSS 12 29 RD6/SPP6/P1C
OSC1/CLKI 13 28 RD5/SPP5/P1B
OSC2/CLKO/RA6 14 27 RD4/SPP4
RC0/T1OSO/T13CKI 15 26 RC7/RX/DT/SDO
RC1/T1OSI/CCP2(1)/UOE 16 25 RC6/TX/CK
RC2/CCP1/P1A 17 24 RC5/D+/VP
VUSB 18 23 RC4/D-/VM
RD0/SPP0 19 22 RD3/SPP3
RD1/SPP1 20 21 RD2/SPP2

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

DS39887B-page 2 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
Pin Diagrams (Continued)

RC1/T1OSI/CCP2(1)/UOE
44-Pin TQFP

NC/ICPORTS(2)
RC2/CCP1/P1A
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
44
43
42
41
40
39

37
36
35
34
38
RC7/RX/DT/SDO 1 33 NC/ICRST(2)/ICVPP(2)
RD4/SPP4 2 32 RC0/T1OSO/T13CKI
RD5/SPP5/P1B 3 31 OSC2/CLKO/RA6
RD6/SPP6/P1C 4 30 OSC1/CLKI
RD7/SPP7/P1D 5 29 VSS
PIC18F4458 28 VDD
VSS 6
VDD 7 PIC18F4553 27 RE2/AN7/OESPP
RB0/AN12/INT0/FLT0/SDI/SDA 8 26 RE1/AN6/CK2SPP
RB1/AN10/INT1/SCK/SCL 9 25 RE0/AN5/CK1SPP
RB2/AN8/INT2/VMO 10 24 RA5/AN4/SS/HLVDIN/C2OUT
RB3/AN9/CCP2(1)/VPO 11 23 RA4/T0CKI/C1OUT/RCV
12
13
14
15
16
17
18
19
20
21
22
RA2/AN2/VREF-/CVREF
RB4/AN11/KBI0/CSSPP
NC/ICCK(2)/ICPGC(2)
NC/ICDT(2)/ICPGD(2)
RB5/KBI1/PGM

MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RB6/KBI2/PGC
RB7/KBI3/PGD

RA3/AN3/VREF+

RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI
RC2/CCP1/P1A
RC6/TX/CK

44-Pin QFN
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
44
43
42
41
40
39

37
36
35
34
38

RC7/RX/DT/SDO 1 33 OSC2/CLKO/RA6
RD4/SPP4 2 32 OSC1/CLKI
RD5/SPP5/P1B 3 31 VSS
RD6/SPP6/P1C 4 30 VSS
RD7/SPP7/P1D 5 PIC18F4458 29 VDD
VSS 6 28 VDD
VDD 7
PIC18F4553 27 RE2/AN7/OESPP
VDD 8 26 RE1/AN6/CK2SPP
RB0/AN12/INT0/FLT0/SDI/SDA 9 25 RE0/AN5/CK1SPP
RB1/AN10/INT1/SCK/SCL 10 24 RA5/AN4/SS/HLVDIN/C2OUT
RB2/AN8/INT2/VMO 11 23 RA4/T0CKI/C1OUT/RCV
12
13
14
15
16
17
18
19
20
21
22
RB3/AN9/CCP2(1)/VPO

RA2/AN2/VREF-/CVREF
RB5/KBI1/PGM

MCLR/VPP/RE3
RA0/AN0
RA1/AN1
NC

RB6/KBI2/PGC
RB7/KBI3/PGD

RA3/AN3/VREF+
RB4/AN11/KBI0/CSSPP

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: Special ICPORT features are available only in 44-pin TQFP packages. See Section 25.9 “Special ICPORT Features” in
the “PIC18F2455/2550/4455/4550 Data Sheet”’.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 3

PIC18F2458/2553/4458/4553
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 19
3.0 Special Features of the CPU ...................................................................................................................................................... 29
4.0 Electrical Characteristics ............................................................................................................................................................ 31
5.0 Packaging Information................................................................................................................................................................ 35
Appendix A: Revision History............................................................................................................................................................... 37
Appendix B: Device Differences........................................................................................................................................................... 37
Appendix C: Migration From Mid-Range to Enhanced Devices........................................................................................................... 38
Appendix D: Migration From High-End to Enhanced Devices ............................................................................................................. 38
Index .................................................................................................................................................................................................... 39
The Microchip Web Site ....................................................................................................................................................................... 41
Customer Change Notification Service ................................................................................................................................................ 41
Customer Support ................................................................................................................................................................................ 41
Reader Response ................................................................................................................................................................................ 42
Product Identification System............................................................................................................................................................... 43

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

DS39887B-page 4 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
1.0 DEVICE OVERVIEW 1.2 Details on Individual Family
Members
This document contains device-specific information for
the following devices: The PIC18F2458/2553/4458/4553 devices are
available in 28-pin and 40/44-pin packages. Block
• PIC18F2458 • PIC18F4458
diagrams for the two groups are shown in Figure 1-1
• PIC18F2553 • PIC18F4553 and Figure 1-2.
The devices are differentiated from each other in the
Note: This data sheet documents only the following ways:
devices’ features and specifications that are
1. Flash program memory (24 Kbytes for
in addition to the features and specifica-
PIC18FX458 devices, 32 Kbytes for
tions of the PIC18F2455/2550/4455/4550
PIC18FX553).
devices. For information on the features
and specifications shared by 2. A/D channels (10 for 28-pin devices, 13 for
the PIC18F2458/2553/4458/4553 and 40-pin and 44-pin devices).
PIC18F2455/2550/4455/4550 devices, 3. I/O ports (3 bidirectional ports and 1 input only
see the “PIC18F2455/2550/4455/4550 port on 28-pin devices, 5 bidirectional ports on
Data Sheet” (DS39632). 40-pin and 44-pin devices).
4. CCP and Enhanced CCP implementation
The PIC18F4553 family of devices offers the advan- (28-pin devices have two standard CCP
tages of all PIC18 microcontrollers – namely, high modules, 40-pin and 44-pin devices have one
computational performance at an economical price – standard CCP module and one ECCP module).
with the addition of high-endurance, Enhanced Flash
5. Streaming Parallel Port (present only on
program memory. In addition to these features, the
40/44-pin devices).
PIC18F4553 family introduces design enhancements
that make these microcontrollers a logical choice for All other features for devices in this family are identical.
many high-performance, power sensitive applications. These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
1.1 Special Features Table 1-3.
• 12-Bit A/D Converter: The PIC18F4553 family Members of the PIC18F4553 family are available as
implements a 12-bit A/D Converter. The A/D both standard and low-voltage devices. Standard
Converter incorporates programmable acquisi- devices with Enhanced Flash memory, designated with
tion time. This allows for a channel to be selected an “F” in the part number (such as PIC18F2458),
and a conversion to be initiated, without waiting accommodate an operating VDD range of 4.2V to 5.5V.
for a sampling period and thus, reducing code Low-voltage parts, designated by “LF” (such as
overhead. PIC18LF2458), function over an extended VDD range
of 2.0V to 5.5V.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 5

PIC18F2458/2553/4458/4553
TABLE 1-1: DEVICE FEATURES
Features PIC18F2458 PIC18F2553 PIC18F4458 PIC18F4553
Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz
Program Memory (Bytes) 24576 32768 24576 32768
Program Memory 12288 16384 12288 16384
(Instructions)
Data Memory (Bytes) 2048 2048 2048 2048
Data EEPROM Memory 256 256 256 256
(Bytes)
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM 2 2 1 1
Modules
Enhanced Capture/ 0 0 1 1
Compare/PWM Modules
Serial Communications MSSP, MSSP, MSSP, MSSP,
Enhanced USART Enhanced USART Enhanced USART Enhanced USART
Universal Serial Bus (USB) 1 1 1 1
Module
Streaming Parallel Port (SPP) No No Yes Yes
12-Bit Analog-to-Digital 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Converter Module
Comparators 2 2 2 2
Resets (and Delays) POR, BOR, WDT, POR, BOR, WDT, POR, BOR, WDT, POR, BOR, WDT,
RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction,
Stack Full, Stack Stack Full, Stack Stack Full, Stack Stack Full, Stack
Underflow, MCLR Underflow, MCLR Underflow, MCLR Underflow, MCLR
(optional), (optional), (optional), (optional),
(PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST)
Programmable High/ Yes Yes Yes Yes
Low-Voltage Detect
Programmable Brown-out Yes Yes Yes Yes
Reset
Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions;
83 with Extended 83 with Extended 83 with Extended 83 with Extended
Instruction Set Instruction Set Instruction Set Instruction Set
Enabled Enabled Enabled Enabled
Packages 28-Pin SPDIP 28-Pin SPDIP 40-Pin PDIP 40-Pin PDIP
28-Pin SOIC 28-Pin SOIC 44-Pin QFN 44-Pin QFN
44-Pin TQFP 44-Pin TQFP
Corresponding Devices with PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550
10-Bit A/D

DS39887B-page 6 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
FIGURE 1-1: PIC18F2458/2553 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21> PORTA

Data Latch RA0/AN0

inc/dec logic 8 8 RA1/AN1
Data Memory RA2/AN2/VREF-/CVREF
(2 Kbytes) RA3/AN3/VREF+
PCLATU PCLATH
21 RA4/T0CKI/C1OUT/RCV
20 Address Latch RA5/AN4/SS/HLVDIN/C2OUT
PCU PCH PCL OSC2/CLKO/RA6
Program Counter 12
Data Address<12>
31 Level Stack
Address Latch 4 12 4
BSR FSR0 Access
Program Memory STKPTR Bank
(24/32 Kbytes) FSR1
FSR2 12
Data Latch PORTB
RB0/AN12/INT0/FLT0/SDI/SDA
inc/dec RB1/AN10/INT1/SCK/SCL
8 logic
Table Latch RB2/AN8/INT2/VMO
RB3/AN9/CCP2(3)/VPO
RB4/AN11/KBI0
ROM Latch Address RB5/KBI1/PGM
Instruction Bus <16> Decode RB6/KBI2/PGC
RB7/KBI3/PGD
IR

8
Instruction State Machine
Decode & Control Signals
Control
PRODH PRODL
PORTC
8 x 8 Multiply RC0/T1OSO/T13CKI
3 8 RC1/T1OSI/CCP2(3)/UOE
(2) Internal RC2/CCP1
OSC1 Power-up
Oscillator BITOP W
Timer 8 RC4/D-/VM
Block 8 8
OSC2(2) Oscillator RC5/D+/VP
INTRC Start-up Timer RC6/TX/CK
Oscillator Power-on 8 8 RC7/RX/DT/SDO
T1OSI
Reset
8 MHz ALU<8>
T1OSO Oscillator Watchdog
Timer
8
Single-Supply Brown-out
MCLR(1) Reset
Programming
In-Circuit Fail-Safe
VDD, VSS Debugger Clock Monitor
PORTE
USB Voltage Band Gap
VUSB
Regulator Reference
MCLR/VPP/RE3(1)

BOR Data
EEPROM Timer0 Timer1 Timer2 Timer3
HLVD

Comparator CCP1 CCP2 MSSP EUSART ADC USB

12-Bit

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: RB3 is the alternate pin for CCP2 multiplexing.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 7

PIC18F2458/2553/4458/4553
FIGURE 1-2: PIC18F4458/4553(40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21> PORTA
RA0/AN0
Data Latch RA1/AN1
inc/dec logic 8 8
RA2/AN2/VREF-/CVREF
Data Memory RA3/AN3/VREF+
PCLATU PCLATH (2 Kbytes) RA4/T0CKI/C1OUT/RCV
21
Address Latch RA5/AN4/SS/HLVDIN/C2OUT
20
PCU PCH PCL OSC2/CLKO/RA6
Program Counter 12
Data Address<12>
PORTB
31 Level Stack
12 RB0/AN12/INT0/FLT0/SDI/SDA
Address Latch 4 4
RB1/AN10/INT1/SCK/SCL
BSR Access
Program Memory STKPTR FSR0 RB2/AN8/INT2/VMO
Bank
(24/32 Kbytes) FSR1 RB3/AN9/CCP2(4)/VPO
FSR2 12 RB4/AN11/KBI0/CSSPP
Data Latch
RB5/KBI1/PGM
RB6/KBI2/PGC
inc/dec
8 logic RB7/KBI3/PGD
Table Latch

Address PORTC
ROM Latch
Instruction Bus <16> Decode RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
IR RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
8 RC6/TX/CK
Instruction State Machine RC7/RX/DT/SDO
Decode & Control Signals
Control
PRODH PRODL
PORTD
8 x 8 Multiply
VDD, VSS 3 8
Internal
(2) Oscillator Power-up RD0/SPP0:RD4/SPP4
OSC1 BITOP W
Block Timer 8 RD5/SPP5/P1B
8 8
OSC2(2) Oscillator RD6/SPP6/P1C
INTRC RD7/SPP7/P1D
Start-up Timer
T1OSI Oscillator 8 8
Power-on
T1OSO 8 MHz
Oscillator Reset ALU<8>
Watchdog 8
ICPGC(3) Single-Supply Timer
Programming Brown-out
ICPGD(3) PORTE
Reset
In-Circuit RE0/AN5/CK1SPP
ICPORTS(3) Debugger Fail-Safe RE1/AN6/CK2SPP
Clock Monitor Band Gap RE2/AN7/OESPP
ICRST(3)
Reference MCLR/VPP/RE3(1)
MCLR(1) USB Voltage
Regulator
VUSB

BOR Data
EEPROM Timer0 Timer1 Timer2 Timer3
HLVD

MSSP EUSART ADC

Comparator ECCP1 CCP2 USB
12-Bit

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: These pins are only available on 44-pin TQFP packages under certain conditions.
4: RB3 is the alternate pin for CCP2 multiplexing.

DS39887B-page 8 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553

TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS

Pin
Number Pin Buffer
Pin Name Description
SPDIP, Type Type
SOIC

MCLR/VPP/RE3 1 Master Clear (input) or programming voltage (input).

MCLR I ST Master Clear (Reset) input. This pin is an active-low
Reset to the device.
VPP P Programming voltage input.
RE3 I ST Digital input.
OSC1/CLKI 9 Oscillator crystal or external clock input.
OSC1 I Analog Oscillator crystal input or external clock source input.
CLKI I Analog External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6 10 Oscillator crystal or clock output.
OSC2 O — Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
CLKO O — In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
RA6 I/O TTL General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 9

PIC18F2458/2553/4458/4553
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Number Pin Buffer
Pin Name Description
SPDIP, Type Type
SOIC
PORTA is a bidirectional I/O port.
RA0/AN0 2
RA0 I/O TTL Digital I/O.
AN0 I Analog Analog input 0.
RA1/AN1 3
RA1 I/O TTL Digital I/O.
AN1 I Analog Analog input 1.
RA2/AN2/VREF-/CVREF 4
RA2 I/O TTL Digital I/O.
AN2 I Analog Analog input 2.
VREF- I Analog A/D reference voltage (low) input.
CVREF O Analog Analog comparator reference output.
RA3/AN3/VREF+ 5
RA3 I/O TTL Digital I/O.
AN3 I Analog Analog input 3.
VREF+ I Analog A/D reference voltage (high) input.
RA4/T0CKI/C1OUT/RCV 6
RA4 I/O ST Digital I/O.
T0CKI I ST Timer0 external clock input.
C1OUT O — Comparator 1 output.
RCV I TTL External USB transceiver RCV input.
RA5/AN4/SS/ 7
HLVDIN/C2OUT
RA5 I/O TTL Digital I/O.
AN4 I Analog Analog input 4.
SS I TTL SPI slave select input.
HLVDIN I Analog High/Low-Voltage Detect input.
C2OUT O — Comparator 2 output.
RA6 — — — See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

DS39887B-page 10 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Number Pin Buffer
Pin Name Description
SPDIP, Type Type
SOIC
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/FLT0/ 21
SDI/SDA
RB0 I/O TTL Digital I/O.
AN12 I Analog Analog input 12.
INT0 I ST External interrupt 0.
FLT0 I ST PWM Fault input (CCP1 module).
SDI I ST SPI data in.
SDA I/O ST I2C™ data I/O.
RB1/AN10/INT1/SCK/ 22
SCL
RB1 I/O TTL Digital I/O.
AN10 I Analog Analog input 10.
INT1 I ST External interrupt 1.
SCK I/O ST Synchronous serial clock input/output for SPI mode.
SCL I/O ST Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO 23
RB2 I/O TTL Digital I/O.
AN8 I Analog Analog input 8.
INT2 I ST External interrupt 2.
VMO O — External USB transceiver VMO output.
RB3/AN9/CCP2/VPO 24
RB3 I/O TTL Digital I/O.
AN9 I Analog Analog input 9.
CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output.
VPO O — External USB transceiver VPO output.
RB4/AN11/KBI0 25
RB4 I/O TTL Digital I/O.
AN11 I Analog Analog input 11.
KBI0 I TTL Interrupt-on-change pin.
RB5/KBI1/PGM 26
RB5 I/O TTL Digital I/O.
KBI1 I TTL Interrupt-on-change pin.
PGM I/O ST Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC 27
RB6 I/O TTL Digital I/O.
KBI2 I TTL Interrupt-on-change pin.
PGC I/O ST In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD 28
RB7 I/O TTL Digital I/O.
KBI3 I TTL Interrupt-on-change pin.
PGD I/O ST In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 11

PIC18F2458/2553/4458/4553
TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Number Pin Buffer
Pin Name Description
SPDIP, Type Type
SOIC
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI 11
RC0 I/O ST Digital I/O.
T1OSO O — Timer1 oscillator output.
T13CKI I ST Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/UOE 12
RC1 I/O ST Digital I/O.
T1OSI I CMOS Timer1 oscillator input.
CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output.
UOE — — External USB transceiver OE output.
RC2/CCP1 13
RC2 I/O ST Digital I/O.
CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output.
RC4/D-/VM 15
RC4 I TTL Digital input.
D- I/O — USB differential minus line (input/output).
VM I TTL External USB transceiver VM input.
RC5/D+/VP 16
RC5 I TTL Digital input.
D+ I/O — USB differential plus line (input/output).
VP O TTL External USB transceiver VP input.
RC6/TX/CK 17
RC6 I/O ST Digital I/O.
TX O — EUSART asynchronous transmit.
CK I/O ST EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO 18
RC7 I/O ST Digital I/O.
RX I ST EUSART asynchronous receive.
DT I/O ST EUSART synchronous data (see TX/CK).
SDO O — SPI data out.
RE3 — — — See MCLR/VPP/RE3 pin.
VUSB 14 Internal USB transceiver power supply.
O — When the internal USB regulator is enabled, VUSB is the
regulator output.
P — When the internal USB regulator is disabled, VUSB is the
power input for the USB transceiver.
VSS 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 P — Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

DS39887B-page 12 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Pin Name Description
PDIP QFN TQFP Type Type

MCLR/VPP/RE3 1 18 18 Master Clear (input) or programming voltage (input).

MCLR I ST Master Clear (Reset) input. This pin is an active-low
Reset to the device.
VPP P Programming voltage input.
RE3 I ST Digital input.
OSC1/CLKI 13 32 30 Oscillator crystal or external clock input.
OSC1 I Analog Oscillator crystal input or external clock source input.
CLKI I Analog External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6 14 33 31 Oscillator crystal or clock output.
OSC2 O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
RA6 I/O TTL General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 13

PIC18F2458/2553/4458/4553
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin NumberPin Buffer
Pin Name Description
PDIP QFN TQFP Type Type

PORTA is a bidirectional I/O port.

RA0/AN0 2 19 19
RA0 I/O TTL Digital I/O.
AN0 I Analog Analog input 0.
RA1/AN1 3 20 20
RA1 I/O TTL Digital I/O.
AN1 I Analog Analog input 1.
RA2/AN2/VREF-/ 4 21 21
CVREF
RA2 I/O TTL Digital I/O.
AN2 I Analog Analog input 2.
VREF- I Analog A/D reference voltage (low) input.
CVREF O Analog Analog comparator reference output.
RA3/AN3/VREF+ 5 22 22
RA3 I/O TTL Digital I/O.
AN3 I Analog Analog input 3.
VREF+ I Analog A/D reference voltage (high) input.
RA4/T0CKI/C1OUT/ 6 23 23
RCV
RA4 I/O ST Digital I/O.
T0CKI I ST Timer0 external clock input.
C1OUT O — Comparator 1 output.
RCV I TTL External USB transceiver RCV input.
RA5/AN4/SS/ 7 24 24
HLVDIN/C2OUT
RA5 I/O TTL Digital I/O.
AN4 I Analog Analog input 4.
SS I TTL SPI slave select input.
HLVDIN I Analog High/Low-Voltage Detect input.
C2OUT O — Comparator 2 output.
RA6 — — — — — See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

DS39887B-page 14 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Buffer
Pin Name Description
PDIP QFN TQFP Type Type

PORTB is a bidirectional I/O port. PORTB can be soft-

ware programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/ 33 9 8
FLT0/SDI/SDA
RB0 I/O TTL Digital I/O.
AN12 I Analog Analog input 12.
INT0 I ST External interrupt 0.
FLT0 I ST Enhanced PWM Fault input (ECCP1 module).
SDI I ST SPI data in.
SDA I/O ST I2C™ data I/O.
RB1/AN10/INT1/SCK/ 34 10 9
SCL
RB1 I/O TTL Digital I/O.
AN10 I Analog Analog input 10.
INT1 I ST External interrupt 1.
SCK I/O ST Synchronous serial clock input/output for SPI mode.
SCL I/O ST Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO 35 11 10
RB2 I/O TTL Digital I/O.
AN8 I Analog Analog input 8.
INT2 I ST External interrupt 2.
VMO O — External USB transceiver VMO output.
RB3/AN9/CCP2/VPO 36 12 11
RB3 I/O TTL Digital I/O.
AN9 I Analog Analog input 9.
CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output.
VPO O — External USB transceiver VPO output.
RB4/AN11/KBI0/CSSPP 37 14 14
RB4 I/O TTL Digital I/O.
AN11 I Analog Analog input 11.
KBI0 I TTL Interrupt-on-change pin.
CSSPP O — SPP chip select control output.
RB5/KBI1/PGM 38 15 15
RB5 I/O TTL Digital I/O.
KBI1 I TTL Interrupt-on-change pin.
PGM I/O ST Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC 39 16 16
RB6 I/O TTL Digital I/O.
KBI2 I TTL Interrupt-on-change pin.
PGC I/O ST In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD 40 17 17
RB7 I/O TTL Digital I/O.
KBI3 I TTL Interrupt-on-change pin.
PGD I/O ST In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 15

PIC18F2458/2553/4458/4553
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Buffer
Pin Name Description
PDIP QFN TQFP Type Type

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI 15 34 32
RC0 I/O ST Digital I/O.
T1OSO O — Timer1 oscillator output.
T13CKI I ST Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/ 16 35 35
UOE
RC1 I/O ST Digital I/O.
T1OSI I CMOS Timer1 oscillator input.
CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output.
UOE O — External USB transceiver OE output.
RC2/CCP1/P1A 17 36 36
RC2 I/O ST Digital I/O.
CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output.
P1A O TTL Enhanced CCP1 PWM output, channel A.
RC4/D-/VM 23 42 42
RC4 I TTL Digital input.
D- I/O — USB differential minus line (input/output).
VM I TTL External USB transceiver VM input.
RC5/D+/VP 24 43 43
RC5 I TTL Digital input.
D+ I/O — USB differential plus line (input/output).
VP I TTL External USB transceiver VP input.
RC6/TX/CK 25 44 44
RC6 I/O ST Digital I/O.
TX O — EUSART asynchronous transmit.
CK I/O ST EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO 26 1 1
RC7 I/O ST Digital I/O.
RX I ST EUSART asynchronous receive.
DT I/O ST EUSART synchronous data (see TX/CK).
SDO O — SPI data out.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

DS39887B-page 16 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number Pin Buffer
Pin Name Description
PDIP QFN TQFP Type Type

PORTD is a bidirectional I/O port or a Streaming

Parallel Port (SPP). PORTD can be software
programmed for internal weak pull-ups on all inputs.
These pins have TTL input buffers when the SPP
module is enabled.
RD0/SPP0 19 38 38
RD0 I/O ST Digital I/O.
SPP0 I/O TTL Streaming Parallel Port data.
RD1/SPP1 20 39 39
RD1 I/O ST Digital I/O.
SPP1 I/O TTL Streaming Parallel Port data.
RD2/SPP2 21 40 40
RD2 I/O ST Digital I/O.
SPP2 I/O TTL Streaming Parallel Port data.
RD3/SPP3 22 41 41
RD3 I/O ST Digital I/O.
SPP3 I/O TTL Streaming Parallel Port data.
RD4/SPP4 27 2 2
RD4 I/O ST Digital I/O.
SPP4 I/O TTL Streaming Parallel Port data.
RD5/SPP5/P1B 28 3 3
RD5 I/O ST Digital I/O.
SPP5 I/O TTL Streaming Parallel Port data.
P1B O — ECCP1 PWM output, channel B.
RD6/SPP6/P1C 29 4 4
RD6 I/O ST Digital I/O.
SPP6 I/O TTL Streaming Parallel Port data.
P1C O — ECCP1 PWM output, channel C.
RD7/SPP7/P1D 30 5 5
RD7 I/O ST Digital I/O.
SPP7 I/O TTL Streaming Parallel Port data.
P1D O — ECCP1 PWM output, channel D.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 17

PIC18F2458/2553/4458/4553
TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name Description
PDIP QFN TQFP Type Type

PORTE is a bidirectional I/O port.

RE0/AN5/CK1SPP 8 25 25
RE0 I/O ST Digital I/O.
AN5 I Analog Analog input 5.
CK1SPP O — SPP clock 1 output.
RE1/AN6/CK2SPP 9 26 26
RE1 I/O ST Digital I/O.
AN6 I Analog Analog input 6.
CK2SPP O — SPP clock 2 output.
RE2/AN7/OESPP 10 27 27
RE2 I/O ST Digital I/O.
AN7 I Analog Analog input 7.
OESPP O — SPP output enable output.
RE3 — — — — — See MCLR/VPP/RE3 pin.
VSS 12, 6, 30, 6, 29 P — Ground reference for logic and I/O pins.
31 31
VDD 11, 32 7, 8, 7, 28 P — Positive supply for logic and I/O pins.
28, 29
VUSB 18 37 37 Internal USB transceiver power supply.
O — When the internal USB regulator is enabled, VUSB is
the regulator output.
P — When the internal USB regulator is disabled, VUSB
is the power input for the USB transceiver.
NC/ICCK/ICPGC(3) — — 12 No Connect or dedicated ICD/ICSP™ port clock.
ICCK I/O ST In-Circuit Debugger clock.
ICPGC I/O ST ICSP programming clock.
NC/ICDT/ICPGD(3) — — 13 No Connect or dedicated ICD/ICSP port clock.
ICDT I/O ST In-Circuit Debugger data.
ICPGD I/O ST ICSP programming data.
NC/ICRST/ICVPP(3) — — 33 No Connect or dedicated ICD/ICSP port Reset.
ICRST I — Master Clear (Reset) input.
ICVPP P — Programming voltage input.
NC/ICPORTS(3) — — 34 P — No Connect or 28-pin device emulation.
ICPORTS Enable 28-pin device emulation when connected
to VSS.
NC — 13 — — — No Connect.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

DS39887B-page 18 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
2.0 12-BIT ANALOG-TO-DIGITAL The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
CONVERTER (A/D) MODULE
register, shown in Register 2-2, configures the
The Analog-to-Digital (A/D) Converter module has functions of the port pins. The ADCON2 register,
10 inputs for the 28-pin devices and 13 for the 40-pin shown in Register 2-3, configures the A/D clock
and 44-pin devices. This module allows conversion of an source, programmed acquisition time and justification.
analog input signal to a corresponding 12-bit digital
number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)

REGISTER 2-1: ADCON0: A/D CONTROL REGISTER 0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)(1,2)
0110 = Channel 6 (AN6)(1,2)
0111 = Channel 7 (AN7)(1,2)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12
1101 = Unimplemented(2)
1110 = Unimplemented(2)
1111 = Unimplemented(2)
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled

Note 1: These channels are not implemented on 28-pin devices.

2: Performing a conversion on unimplemented channels will return a floating input measurement.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 19

PIC18F2458/2553/4458/4553
REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W(1) R/W(1) R/W(1)
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
AN7(2)

AN6(2)

AN5(2)
AN12

AN10
AN11

PCFG3:
AN9

AN8

AN4

AN3

AN2

AN1

AN0
PCFG0

0000(1) A A A A A A A A A A A A A
0001 A A A A A A A A A A A A A
0010 A A A A A A A A A A A A A
0011 D A A A A A A A A A A A A
0100 D D A A A A A A A A A A A
0101 D D D A A A A A A A A A A
0110 D D D D A A A A A A A A A
0111(1) D D D D D A A A A A A A A
1000 D D D D D D A A A A A A A
1001 D D D D D D D A A A A A A
1010 D D D D D D D D A A A A A
1011 D D D D D D D D D A A A A
1100 D D D D D D D D D D A A A
1101 D D D D D D D D D D D A A
1110 D D D D D D D D D D D D A
1111 D D D D D D D D D D D D D
A = Analog input D = Digital I/O

Note 1: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40-pin and 44-pin devices.

DS39887B-page 20 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 21

PIC18F2458/2553/4458/4553
The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state.
either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any
(VDD and VSS), or the voltage level on the RA3/AN3/ conversion in progress is aborted.
VREF+ and RA2/AN2/VREF-/CVREF pins. Each port pin associated with the A/D Converter can be
The A/D Converter has a unique feature of being able configured as an analog input or as a digital I/O. The
to operate while the device is in Sleep mode. To oper- ADRESH and ADRESL registers contain the result of
ate in Sleep, the A/D conversion clock must be derived the A/D conversion. When the A/D conversion is com-
from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH:ADRESL
The output of the sample and hold is the input into the register pair, the GO/DONE bit (ADCON0 register) is
Converter, which generates the result via successive cleared and the A/D Interrupt Flag bit, ADIF, is set. The
approximation. block diagram of the A/D module is shown in Figure 2-1.

FIGURE 2-1: A/D BLOCK DIAGRAM

CHS3:CHS0

1100
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
12-Bit (Input Voltage) 0011
AN3
A/D
Converter 0010
AN2
0001
VCFG1:VCFG0 AN1

VDD 0000
AN0
X0
VREF+ X1
Reference 1X
Voltage
VREF- 0X

VSS

Note 1: Channels AN5 through AN7 are not available on 28-pin devices.

DS39887B-page 22 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
The value in the ADRESH:ADRESL registers is 5. Wait for A/D conversion to complete, by either:
unknown following Power-on and Brown-out Resets, • Polling for the GO/DONE bit to be cleared
and is not affected by any other Reset.
OR
After the A/D module has been configured as desired,
• Waiting for the A/D interrupt
the selected channel must be acquired before the
conversion is started. The analog input channels must 6. Read A/D Result registers (ADRESH:ADRESL);
have their corresponding TRIS bits selected as an clear bit ADIF, if required.
input. To determine acquisition time, see Section 2.1 7. For next conversion, go to step 1 or step 2, as
“A/D Acquisition Requirements”. After this acquisi- required. The A/D conversion time per bit is
tion time has elapsed, the A/D conversion can be defined as TAD. A minimum wait of 2 TAD is
started. An acquisition time can be programmed to required before the next acquisition starts.
occur between setting the GO/DONE bit and the actual
start of the conversion. FIGURE 2-2: A/D TRANSFER FUNCTION
The following steps should be followed to perform an A/D
conversion: FFFh
1. Configure the A/D module:
FFEh
• Configure analog pins, voltage reference and
digital I/O (ADCON1)

Digital Code Output

• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
003h
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
002h
2. Configure A/D interrupt (if desired):
• Clear ADIF bit 001h
• Set ADIE bit
• Set GIE bit 000h
0.5 LSB
1 LSB
1.5 LSB
2 LSB
2.5 LSB
3 LSB

4094 LSB
4094.5 LSB
4095 LSB
4095.5 LSB
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
Analog Input Voltage

FIGURE 2-3: ANALOG INPUT MODEL

VDD
Sampling
Switch
VT = 0.6V
ANx RIC ≤ 1k SS RSS
Rs

VAIN CPIN CHOLD = 25 pF

ILEAKAGE
5 pF VT = 0.6V
±100 nA

VSS

Legend: CPIN = Input Capacitance

VT = Threshold Voltage 6V
ILEAKAGE = Leakage Current at the pin due to 5V
VDD 4V
various junctions
3V
RIC = Interconnect Resistance 2V
SS = Sampling Switch
CHOLD = Sample/Hold Capacitance (from DAC) 1 2 3 4
RSS = Sampling Switch Resistance Sampling Switch (kΩ)

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 23

PIC18F2458/2553/4458/4553
2.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
For the A/D Converter to meet its specified accuracy, is used (4096 steps for the 12-bit A/D). The 1/2 LSb error
the charge holding capacitor (CHOLD) must be allowed is the maximum error allowed for the A/D to meet its
to fully charge to the input channel voltage level. The specified resolution.
analog input model is shown in Figure 2-3. The source
impedance (RS) and the internal sampling switch (RSS) Example 2-3 shows the calculation of the minimum
impedance directly affect the time required to charge required acquisition time, TACQ. This calculation is
the capacitor CHOLD. The sampling switch (RSS) based on the following application system
impedance varies over the device voltage (VDD). The assumptions:
source impedance affects the offset voltage at the ana- CHOLD = 25 pF
log input (due to pin leakage current). The maximum Rs = 2.5 kΩ
recommended impedance for analog sources is Conversion Error ≤ 1/2 LSb
2.5 kΩ. After the analog input channel is selected VDD = 3V → Rss = 4 kΩ
(changed), the channel must be sampled for at least Temperature = 85°C (system max.)
the minimum acquisition time before starting a
conversion.
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.

EQUATION 2-1: ACQUISITION TIME

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF

EQUATION 2-2: A/D MINIMUM CHARGING TIME

VHOLD = (VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/4096)

EQUATION 2-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ = TAMP + TC + TCOFF
TAMP = 0.2 µs
TCOFF = (Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/4096) µs
-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs
1.56 µs
TACQ = 0.2 µs + 1.56 μs + 1.2 µs
2.96 µs

DS39887B-page 24 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
2.2 Selecting and Configuring 2.3 Selecting the A/D Conversion
Acquisition Time Clock
The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The
acquisition time that occurs each time the GO/DONE A/D conversion requires 13 TAD per 12-bit conversion.
bit is set. It also gives users the option to use an The source of the A/D conversion clock is software
automatically determined acquisition time. selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0 • 2 TOSC
bits (ADCON2<5:3>), which provides a range of 2 to • 4 TOSC
20 TAD. When the GO/DONE bit is set, the A/D module • 8 TOSC
continues to sample the input for the selected acquisi-
• 16 TOSC
tion time, then automatically begins a conversion.
Since the acquisition time is programmed, there may • 32 TOSC
be no need to wait for an acquisition time between • 64 TOSC
selecting a channel and setting the GO/DONE bit. • Internal RC Oscillator
Manual acquisition is selected when For correct A/D conversions, the A/D conversion clock
ACQT2:ACQT0 = 000. When the GO/DONE bit is set, (TAD) must be as short as possible, but greater than the
sampling is stopped and a conversion begins. The user minimum TAD (see parameter 130 for more
is responsible for ensuring the required acquisition time information).
has passed between selecting the desired input
Table 2-1 shows the resultant TAD times derived from
channel and setting the GO/DONE bit. This option is
the device operating frequencies and the A/D clock
also the default Reset state of the ACQT2:ACQT0 bits
source selected.
and is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.

TABLE 2-1: TAD vs. DEVICE OPERATING FREQUENCIES

A/D Clock Source (TAD) Assumes TAD Min. = 0.8 μs

Operation ADCS2:ADCS0 Maximum FOSC

2 TOSC 000 2.50 MHz
4 TOSC 100 5.00 MHz
8 TOSC 001 10.00 MHz
16 TOSC 101 20.00 MHz
32 TOSC 010 40.00 MHz
64 TOSC 110 48.00 MHz
RC(1) x11 1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 2.5 μs.
2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 25

PIC18F2458/2553/4458/4553
2.4 Operation in Power-Managed 2.5 Configuring Analog Port Pins
Modes The ADCON1, TRISA, TRISB and TRISE registers all
The selection of the automatic acquisition time and A/D configure the A/D port pins. The port pins needed as
conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits
source and frequency while in a power-managed mode. set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in The A/D operation is independent of the state of the
ADCON2 should be updated in accordance with the CHS3:CHS0 bits and the TRIS bits.
clock source to be used. The ACQT2:ACQT0 bits do Note 1: When reading the PORT register, all pins
not need to be adjusted as the ADCS2:ADCS0 bits configured as analog input channels will
adjust the TAD time for the new clock speed. After read as cleared (a low level). Analog con-
entering the mode, an A/D acquisition or conversion version on pins configured as digital pins
may be started. Once started, the device should can be performed. The voltage on the pin
continue to be clocked by the same clock source until will be accurately converted.
the conversion has been completed.
2: Analog levels on any pin defined as a dig-
If desired, the device may be placed into the ital input may cause the digital input buffer
corresponding Idle mode during the conversion. If the to consume current out of the device’s
device clock frequency is less than 1 MHz, the A/D RC specification limits.
clock source should be selected.
3: The PBADEN bit in Configuration
Operation in Sleep mode requires the A/D FRC clock to Register 3H configures PORTB pins to
be selected. If bits ACQT2:ACQT0 are set to ‘000’ and reset as analog or digital pins by control-
a conversion is started, the conversion will be delayed ling how the PCFG3:PCFG0 bits in
one instruction cycle to allow execution of the SLEEP ADCON1 are reset.
instruction and entry to Sleep mode. The IDLEN bit
(OSCCON<7>) must have already been cleared prior
to starting the conversion.

DS39887B-page 26 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
2.6 A/D Conversions After the A/D conversion is completed or aborted, a
2 TCY wait is required before the next acquisition can
Figure 2-4 shows the operation of the A/D Converter be started. After this wait, acquisition on the selected
after the GO/DONE bit has been set and the channel is automatically started.
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into Note: The GO/DONE bit should NOT be set in
Sleep mode before the conversion begins. the same instruction that turns on the A/D.
Code should wait at least 2 μs after
Figure 2-5 shows the operation of the A/D Converter
enabling the A/D before beginning an
after the GO/DONE bit has been set and the
acquisition and conversion cycle.
ACQT2:ACQT0 bits are set to ‘010’, and selecting a
4 TAD acquisition time before the conversion starts.
2.7 Discharge
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will The discharge phase is used to initialize the value of
NOT be updated with the partially completed A/D the holding capacitor. The array is discharged before
conversion sample. This means the ADRESH:ADRESL every sample. This feature helps to optimize the unity
registers will continue to contain the value of the last gain amplifier, as the circuit always needs to charge the
completed conversion (or the last value written to the capacitor array, rather than charge/discharge based on
ADRESH:ADRESL registers). previous measure values.

FIGURE 2-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Conversion starts Discharge

(typically 200 ns)
Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO/DONE bit

On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.

FIGURE 2-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

TACQT Cycles TAD Cycles

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 TAD1
Automatic b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Acquisition
Time Conversion starts Discharge
(Holding capacitor is disconnected) (typically
200 ns)

Set GO/DONE bit

(Holding capacitor continues On the following cycle:
acquiring input) ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 27

PIC18F2458/2553/4458/4553
2.8 Use of the CCP2 Trigger the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
An A/D conversion can be started by the Special Event period is either timed by the user, or an appropriate TACQ
Trigger of the CCP2 module. This requires that the time selected before the Special Event Trigger sets the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- GO/DONE bit (starts a conversion).
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/ If the A/D module is not enabled (ADON is cleared), the
DONE bit will be set, starting the A/D acquisition and Special Event Trigger will be ignored by the A/D
conversion, and the Timer1 (or Timer3) counter will be module, but will still reset the Timer1 (or Timer3)
reset to zero. Timer1 (or Timer3) is reset to automatically counter.
repeat the A/D acquisition period with minimal software
overhead (firmware must move ADRESH:ADRESL to

TABLE 2-2: REGISTERS ASSOCIATED WITH A/D OPERATION

Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values
on Page:
INTCON GIE/GIEH PEIE/GIEL (4)
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF (4)

PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE (4)

IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP (4)
(4)
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF
(4)
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE
(4)
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP
(4)
ADRESH A/D Result Register High Byte
(4)
ADRESL A/D Result Register Low Byte
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 19
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 20
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 21
PORTA — RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 (4)

TRISA — TRISA6(2) PORTA Data Direction Control Register (4)

(4)
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
(4)
TRISB PORTB Data Direction Control Register
(4)
LATB PORTB Data Latch Register (Read and Write to Data Latch)
PORTE(1) RDPU — — — RE3(3) RE2(1) RE1(1) RE0(1) (4)
(1) (4)
TRISE — — — — — TRISE2 TRISE1 TRISE0
LATE(1) — — — — — PORTE Data Latch Register (4)

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’.
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: For these Reset values, see the “PIC18F2455/2550/4455/4550 Data Sheet”.

DS39887B-page 28 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
3.0 SPECIAL FEATURES OF THE 3.1 Device ID Registers
CPU The Device ID registers are “read-only” registers.
They identify the device type and revision to device
Note: For additional details on the Con-
programmers, and can be read by firmware using
figuration bits, refer to the
table reads.
“PIC18F2455/2550/4455/4550 Data Sheet”,
Section 25.1 “Configuration Bits”. Device
ID information presented in this section is for
PIC18F2458/2553/4458/4553 only.
PIC18F2458/2553/4458/4553 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These include:
• Device ID Registers

TABLE 3-1: DEVICE IDs

Default/
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed
Value

3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx(1)
Legend: x = unknown, u = unchanged
Note 1: See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the
user.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 29

PIC18F2458/2553/4458/4553

REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2458/2553/4458/4553 DEVICES

R R R R R R R R
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0

Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-5 DEV2:DEV0: Device ID bits

See Register 3-2 for a complete listing.
bit 4-0 REV3:REV0: Revision ID bits
These bits are used to indicate the device revision.

REGISTER 3-2: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2458/2553/4458/4553 DEVICES

R R R R R R R R
DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3
bit 7 bit 0

Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-0 DEV10:DEV3: Device ID bits

DEV10:DEV3 DEV2:DEV0
Device
(DEVID2<7:0>) (DEVID1<7:5>)
0010 1010 011 PIC18F2458
0010 1010 010 PIC18F2553
0010 1010 001 PIC18F4458
0010 1010 000 PIC18F4553

DS39887B-page 30 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
4.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RE3 pin, rather than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 31

PIC18F2458/2553/4458/4553
FIGURE 4-1: PIC18F2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V
5.5V
5.0V PIC18F2458/2553/4458/4553
4.5V
Voltage

4.2V
4.0V
3.5V
3.0V
2.5V
2.0V

48 MHz
Frequency

FIGURE 4-2: PIC18LF2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V
5.5V
5.0V PIC18LF2458/2553/4458/4553
4.5V
Voltage

4.2V
4.0V
3.5V
3.0V
2.5V
2.0V

4 MHz 40 MHz 48 MHz

Frequency
For 2.0V ≤ VDD < 4.2V: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
For 4.2V ≤ VDD: FMAX = 48 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.

DS39887B-page 32 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
TABLE 4-1: A/D CONVERTER CHARACTERISTICS: PIC18F2458/2553/4458/4553 (INDUSTRIAL)
PIC18LF2458/2553/4458/4553 (INDUSTRIAL)
Param
Sym Characteristic Min Typ Max Units Conditions
No.

A01 NR Resolution — — 12 bit ΔVREF ≥ 3.0V

A03 EIL Integral Linearity Error — ±1 ±2.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V
— — ±2.0 LSB VDD = 5.0V
A04 EDL Differential Linearity Error — ±1 +1.5/-1.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V
— — +1.5/-1.0 LSB VDD = 5.0V
A06 EOFF Offset Error — ±1 ±5 LSB VDD = 3.0V ΔVREF ≥ 3.0V
— — ±3 LSB VDD = 5.0V
A07 EGN Gain Error — ±1 ±1.25 LSB VDD = 3.0V ΔVREF ≥ 3.0V
— — ±2.00 LSB VDD = 5.0V
A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF
A20 ΔVREF Reference Voltage Range 3 — VDD – VSS V For 12-bit resolution
(VREFH – VREFL)
A21 VREFH Reference Voltage High VSS + 3.0V — VDD + 0.3V V For 12-bit resolution
A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V For 12-bit resolution
A25 VAIN Analog Input Voltage VREFL — VREFH V
A30 ZAIN Recommended — — 2.5 kΩ
Impedance of Analog
Voltage Source
A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition.
— — 150 μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 33

PIC18F2458/2553/4458/4553
FIGURE 4-3: A/D CONVERSION TIMING

BSF ADCON0, GO
(Note 2)
131
Q4
130
(1) 132
A/D CLK

A/D DATA 11 10 9 ... ... 3 2 1 0

ADRES OLD_DATA NEW_DATA

ADIF TCY

GO DONE

SAMPLING STOPPED
SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

TABLE 4-2: A/D CONVERSION REQUIREMENTS

Param
Symbol Characteristic Min Max Units Conditions
No.
130 TAD A/D Clock Period PIC18FXXXX 0.8 12.5(1) μs TOSC based, VREF ≥ 3.0V
PIC18LFXXXX 1.4 25.0(1) μs VDD = 3.0V;
TOSC based, VREF full range
PIC18FXXXX — 1 μs A/D RC mode
PIC18LFXXXX — 3 μs VDD = 3.0V; A/D RC mode
131 TCNV Conversion Time 13 14 TAD
(not including acquisition time)(2)
132 TACQ Acquisition Time(3) 1.4 — μs
135 TSWC Switching Time from Convert → Sample — (Note 4)
137 TDIS Discharge Time 0.2 — μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.

DS39887B-page 34 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
5.0 PACKAGING INFORMATION
For packaging information, see the “PIC18F2455/
2550/4455/4550 Data Sheet” (DS39632).

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 35

PIC18F2458/2553/4458/4553
NOTES:

DS39887B-page 36 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE
DIFFERENCES
Revision A (May 2007)
The differences between the devices listed in this data
Original data sheet for the PIC18F2458/2553/4458/ sheet are shown in Table B-1.
4553 devices.

Revision B (June 2007)

Changes to Figure 4-2: PIC18LF2458/2553/4458/4553
Voltage-Frequency Graph (Industrial).

TABLE B-1: DEVICE DIFFERENCES

Features PIC18F2458 PIC18F2553 PIC18F4458 PIC18F4553
Program Memory (Bytes) 24576 32768 24576 32768
Program Memory (Instructions) 12288 16384 12288 16384
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Capture/Compare/PWM Modules 2 2 1 1
Enhanced Capture/Compare/ 0 0 1 1
PWM Modules
Parallel Communications (SPP) No No Yes Yes
12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Packages 28-Pin SPDIP 28-Pin SPDIP 40-Pin PDIP 40-Pin PDIP
28-Pin SOIC 28-Pin SOIC 44-Pin TQFP 44-Pin TQFP
44-Pin QFN 44-Pin QFN

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 37

PIC18F2458/2553/4458/4553
APPENDIX C: MIGRATION FROM APPENDIX D: MIGRATION FROM
MID-RANGE TO HIGH-END TO
ENHANCED DEVICES ENHANCED DEVICES
A detailed discussion of the differences between the A detailed discussion of the migration pathway and
mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e.,
enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e.,
AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18C442”. The changes discussed, while device PIC18CXXX Migration”.
specific, are generally applicable to all mid-range to This Application Note is available as Literature Number
enhanced device migrations. DS00726.
This Application Note is available as Literature Number
DS00716.

DS39887B-page 38 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
INDEX
A M
A/D ..................................................................................... 19 Microchip Internet Web Site ............................................... 41
A/D Converter Interrupt, Configuring ......................... 23 Migration from High-End to
Acquisition Requirements .......................................... 24 Enhanced Devices ..................................................... 38
ADCON0 Register ...................................................... 19 Migration from Mid-Range to
ADCON1 Register ...................................................... 19 Enhanced Devices ..................................................... 38
ADCON2 Register ...................................................... 19
ADRESH Register ................................................ 19, 22 P
ADRESL Register ...................................................... 19 Packaging Information ....................................................... 35
Analog Port Pins, Configuring .................................... 26 Pin Functions
Associated Registers ................................................. 28 MCLR/VPP/RE3 ........................................................... 9
Calculating the Minimum Required MCLR/VPP/RE3 ......................................................... 13
Acquisition Time ................................................ 24 NC/ICCK/ICPGC ....................................................... 18
Configuring the Module .............................................. 23 NC/ICDT/ICPGD ........................................................ 18
Conversion Clock (TAD) ............................................. 25 NC/ICPORTS ............................................................ 18
Conversion Status (GO/DONE Bit) ............................ 22 NC/ICRST/ICVPP ....................................................... 18
Conversions ............................................................... 27 OSC1/CLKI ............................................................ 9, 13
Converter Characteristics .......................................... 33 OSC2/CLKO/RA6 .................................................. 9, 13
Discharge ................................................................... 27 RA0/AN0 .............................................................. 10, 14
Operation in Power-Managed Modes ........................ 26 RA1/AN1 .............................................................. 10, 14
Selecting and Configuring Acquisition Time .............. 25 RA2/AN2/VREF-/CVREF ....................................... 10, 14
Special Event Trigger (CCP) ...................................... 28 RA3/AN3/VREF+ .................................................. 10, 14
Use of the CCP2 Trigger ............................................ 28 RA4/T0CKI/C1OUT/RCV ..................................... 10, 14
Absolute Maximum Ratings ............................................... 31 RA5/AN4/SS/HLVDIN/C2OUT ............................ 10, 14
ADCON0 Register .............................................................. 19 RB0/AN12/INT0/FLT0/SDI/SDA .......................... 11, 15
GO/DONE Bit ............................................................. 22 RB1/AN10/INT1/SCK/SCL .................................. 11, 15
ADCON1 Register .............................................................. 19 RB2/AN8/INT2/VMO ............................................ 11, 15
ADCON2 Register .............................................................. 19 RB3/AN9/CCP2/VPO .......................................... 11, 15
ADRESH Register .............................................................. 19 RB4/AN11/KBI0 ......................................................... 11
ADRESL Register ........................................................ 19, 22 RB4/AN11/KBI0/CSSPP ............................................ 15
Analog-to-Digital Converter. See A/D. RB5/KBI1/PGM .................................................... 11, 15
RB6/KBI2/PGC .................................................... 11, 15
B RB7/KBI3/PGD .................................................... 11, 15
Block Diagrams RC0/T1OSO/T13CKI ........................................... 12, 16
A/D ............................................................................. 22 RC1/T1OSI/CCP2/UOE ....................................... 12, 16
Analog Input Model .................................................... 23 RC2/CCP1 ................................................................. 12
PIC18F2458/2553 ........................................................ 7 RC2/CCP1/P1A ......................................................... 16
PIC18F4458/4553 ........................................................ 8 RC4/D-/VM .......................................................... 12, 16
RC5/D+/VP .......................................................... 12, 16
C RC6/TX/CK .......................................................... 12, 16
Compare (CCP Module) RC7/RX/DT/SDO ................................................. 12, 16
Special Event Trigger ................................................. 28 RD0/SPP0 ................................................................. 17
Configuration Bits ............................................................... 29 RD1/SPP1 ................................................................. 17
Customer Change Notification Service .............................. 41 RD2/SPP2 ................................................................. 17
Customer Notification Service ............................................ 41 RD3/SPP3 ................................................................. 17
Customer Support .............................................................. 41 RD4/SPP4 ................................................................. 17
RD5/SPP5/P1B ......................................................... 17
D RD6/SPP6/P1C ......................................................... 17
Device Differences ............................................................. 37 RD7/SPP7/P1D ......................................................... 17
Device ID Registers ........................................................... 29 RE0/AN5/CK1SPP .................................................... 18
Device Overview .................................................................. 5 RE1/AN6/CK2SPP .................................................... 18
Other Special Features ................................................ 5 RE2/AN7/OESPP ...................................................... 18
VDD ...................................................................... 12, 18
E
VSS ...................................................................... 12, 18
Electrical Characteristics .................................................... 31 VUSB .................................................................... 12, 18
Equations Pinout I/O Descriptions
A/D Acquisition Time .................................................. 24 PIC18F2458/2553 ....................................................... 9
A/D Minimum Charging Time ..................................... 24 PIC18F4458/4553 ..................................................... 13
Errata ................................................................................... 4 Power-Managed Modes
I and A/D Operation ..................................................... 26

Internet Address ................................................................. 41

Interrupt Sources
A/D Conversion Complete ......................................... 23

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 39

PIC18F2458/2553/4458/4553
R T
Reader Response .............................................................. 42 Timing Diagrams
Registers A/D Conversion .......................................................... 34
ADCON0 (A/D Control 0) ........................................... 19 Timing Diagrams and Specifications
ADCON1 (A/D Control 1) ........................................... 20 A/D Conversion Requirements .................................. 34
ADCON2 (A/D Control 2) ........................................... 21
DEVID1 (Device ID 1) ................................................ 30 W
DEVID2 (Device ID 2) ................................................ 30 WWW Address .................................................................. 41
Revision History ................................................................. 37 WWW, On-Line Support ...................................................... 4

S
Special Features of the CPU .............................................. 29

DS39887B-page 40 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 41

PIC18F2458/2553/4458/4553
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N

Device: PIC18F2458/2553/4458/4553 Literature Number: DS39887B

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS39887B-page 42 Preliminary © 2007 Microchip Technology Inc.

 PIC18F2458/2553/4458/4553
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Examples:
Device Temperature Package Pattern a) PIC18LF4553-I/P 301 = Industrial temp., PDIP
Range package, Extended VDD limits, QTP pattern
#301.
b) PIC18LF2458-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
Device PIC18F2458/2553(1), PIC18F4458/4553(1), c) PIC18F4458-I/P = Industrial temp., PDIP
PIC18F2458/2553T(2), PIC18F4458/4553T(2); package, normal VDD limits.
VDD range 4.2V to 5.5V
PIC18LF2458/2553(1), PIC18LF4458/4553(1),
PIC18LF2458/2553T(2), PIC18LF4458/4553T(2);
VDD range 2.0V to 5.5V

Temperature Range I = -40°C to +85°C (Industrial)

E = -40°C to +125°C (Extended)

Package PT = TQFP (Thin Quad Flatpack) Note 1: F = Standard Voltage Range

SO = SOIC
SP = Skinny PDIP LF = Wide Voltage Range
P = PDIP 2: T = In tape and reel TQFP
ML = QFN packages only.

Pattern QTP, SQTP, Code or Special Requirements

(blank otherwise)

© 2007 Microchip Technology Inc. Preliminary DS39887B-page 43

 WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-4182-8400 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-4182-8422 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon Denmark - Copenhagen
India - New Delhi
Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://support.microchip.com Fax: 852-2401-3431
India - Pune France - Paris
Web Address:
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
www.microchip.com
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
Atlanta Fax: 61-2-9868-6755
Japan - Yokohama Germany - Munich
Duluth, GA
China - Beijing Tel: 49-89-627-144-0
Tel: 678-957-9614 Tel: 81-45-471- 6166
Tel: 86-10-8528-2100 Fax: 49-89-627-144-44
Fax: 678-957-1455 Fax: 81-45-471-6122
Fax: 86-10-8528-2104 Italy - Milan
Boston Korea - Daegu
China - Chengdu Tel: 39-0331-742611
Westborough, MA Tel: 82-53-744-4301
Tel: 86-28-8665-5511 Fax: 39-0331-466781
Tel: 774-760-0087 Fax: 82-53-744-4302
Fax: 86-28-8665-7889 Netherlands - Drunen
Fax: 774-760-0088 Korea - Seoul
China - Fuzhou Tel: 82-2-554-7200 Tel: 31-416-690399
Chicago
Tel: 86-591-8750-3506 Fax: 82-2-558-5932 or Fax: 31-416-690340
Itasca, IL
Tel: 630-285-0071 Fax: 86-591-8750-3521 82-2-558-5934 Spain - Madrid
Fax: 630-285-0075 China - Hong Kong SAR Tel: 34-91-708-08-90
Malaysia - Penang
Tel: 852-2401-1200 Tel: 60-4-646-8870 Fax: 34-91-708-08-91
Dallas
Addison, TX Fax: 852-2401-3431 Fax: 60-4-646-5086 UK - Wokingham
Tel: 972-818-7423 China - Qingdao Tel: 44-118-921-5869
Philippines - Manila
Fax: 972-818-2924 Tel: 86-532-8502-7355 Fax: 44-118-921-5820
Tel: 63-2-634-9065
Detroit Fax: 86-532-8502-7205 Fax: 63-2-634-9069
Farmington Hills, MI China - Shanghai Singapore
Tel: 248-538-2250 Tel: 86-21-5407-5533 Tel: 65-6334-8870
Fax: 248-538-2260 Fax: 86-21-5407-5066 Fax: 65-6334-8850
Kokomo China - Shenyang Taiwan - Hsin Chu
Kokomo, IN Tel: 86-24-2334-2829 Tel: 886-3-572-9526
Tel: 765-864-8360 Fax: 86-24-2334-2393 Fax: 886-3-572-6459
Fax: 765-864-8387
China - Shenzhen Taiwan - Kaohsiung
Los Angeles Tel: 86-755-8203-2660 Tel: 886-7-536-4818
Mission Viejo, CA Fax: 86-755-8203-1760 Fax: 886-7-536-4803
Tel: 949-462-9523
China - Shunde Taiwan - Taipei
Fax: 949-462-9608
Tel: 86-757-2839-5507 Tel: 886-2-2500-6610
Santa Clara Fax: 86-757-2839-5571 Fax: 886-2-2508-0102
Santa Clara, CA
China - Wuhan Thailand - Bangkok
Tel: 408-961-6444
Tel: 86-27-5980-5300 Tel: 66-2-694-1351
Fax: 408-961-6445
Fax: 86-27-5980-5118 Fax: 66-2-694-1350
Toronto
China - Xian
Mississauga, Ontario,
Tel: 86-29-8833-7252
Canada
Fax: 86-29-8833-7256
Tel: 905-673-0699
Fax: 905-673-6509

06/25/07

DS39887B-page 44 Preliminary © 2007 Microchip Technology Inc.