OPA810

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SBOS799D – AUGUST 2019 – REVISED JULY 2020
SBOS799D – AUGUST 2019 – REVISED JULY 2020

OPA810 140-MHz, Rail-to-Rail Input and Output, FET-Input Operational Amplifier

1 Features 3 Description
• Gain-Bandwidth Product: 70 MHz The OPA810 is a single-channel, field-effect transistor
• Small-Signal Bandwidth: 140 MHz (FET)-input, voltage-feedback operational amplifier
• Slew Rate: 200 V/µs with bias current in the picoampere (pA) range. The
• Wide Supply Range: 4.75 V to 27 V OPA810 is unity-gain stable with a small-signal, unity-
gain bandwidth of 140 MHz, and offers excellent DC
• Low Noise:
precision and dynamic AC performance at a low
– Input Voltage Noise: 6.3 nV/√ Hz (f = 500 kHz) quiescent current (IQ) of 3.7 mA per channel. The
– Input Current Noise: 5 fA/√ Hz (f = 10 kHz) OPA810 is fabricated on Texas Instrument's
• Rail-to-Rail Input and Output: proprietary, high-speed SiGe BiCMOS process and
– FET Input Stage: 2-pA Input Bias Current achieves significant performance improvements over
(Typical) comparable FET-input amplifiers at similar levels of
– High Linear Output Current: 75 mA quiescent power. With a gain-bandwidth product
• Input Offset: ±500 µV (Maximum) (GBWP) of 70 MHz, slew rate of 200 V/µs, and low-
• Offset Drift: ±2.5 µV/°C (Typical) noise voltage of 6.3 nV/√ Hz, the OPA810 is well
suited for use in a wide range of high-fidelity data
• Low Power: 3.7 mA/Channel
acquisition and signal processing applications.
• Extended Temperature Operation:
–40°C to +125°C The OPA810 features rail-to-rail inputs and outputs
• Dual-Channel Version: OPA2810 and delivers 75 mA of linear output current, suitable
for driving optoelectronics components and analog-to-
2 Applications digital converter (ADC) inputs or buffering digital-to-
• Wideband Photodiode Transimpedance Amplifiers analog converter (DAC) outputs into heavy loads.
• Analog Input and Output Modules The OPA810 is rated over the extended industrial
• Impedance Measurements temperature range of –40°C to +125°C. The OPA2810
• Power Analyzers and Meters is a dual-channel variant of this device, available in 8-
• High-Z Voltage and Current Measurements pin SOIC, SOT-23, and VSSOP packages.
• Data Acquisition Device Information
• Multichannel Sensor Interfaces
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
• Optoelectronic Drivers
SOIC (8) 4.90 mm × 3.91 mm
OPA810 SOT-23 (5) 2.90 mm × 1.60 mm
SC70 (5) 2.00 mm × 1.25 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
CF

12V

± RF

OPA810 RG 1.8V 1.8V

VIN+ + 12V RS
AVDD DVDD
R C
-12V ± C CB ADS911 0
VOCM
THS456 1 18-bit
12V 2 MSPS
+ CCB
RG
VREF
±
-0.2V
OPA810
VIN- + RF R¶
R C
-12V R¶
5V
CF
5V ±
12V
± OPA837
REF505 0 RFIL T OPA378 +
5.0 V +
Reference
CFIL T

High-Z Input Data Acquisition Front-End

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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intellectual Instruments
property Incorporated
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Table of Contents
1 Features............................................................................1 8 Detailed Description......................................................22
2 Applications..................................................................... 1 8.1 Overview................................................................... 22
3 Description.......................................................................1 8.2 Functional Block Diagram......................................... 22
4 Revision History.............................................................. 2 8.3 Feature Description...................................................23
5 Device Comparison Table...............................................3 8.4 Device Functional Modes..........................................24
6 Pin Configuration and Functions...................................3 9 Application and Implementation.................................. 25
Pin Functions.................................................................... 3 9.1 Application Information............................................. 25
7 Specifications.................................................................. 4 9.2 Typical Applications.................................................. 30
7.1 Absolute Maximum Ratings........................................ 4 10 Power Supply Recommendations..............................34
7.2 ESD Ratings............................................................... 4 11 Layout........................................................................... 34
7.3 Recommended Operating Conditions.........................4 11.1 Layout Guidelines................................................... 34
7.4 Thermal Information....................................................4 11.2 Layout Example...................................................... 36
7.5 Electrical Characteristics: 10 V................................... 5 12 Device and Documentation Support..........................37
7.6 Electrical Characteristics: 24 V................................... 7 12.1 Third-Party Products Disclaimer............................. 37
7.7 Electrical Characteristics: 5 V..................................... 9 12.2 Documentation Support.......................................... 37
7.8 Typical Characteristics: VS = 10 V.............................11 12.3 Receiving Notification of Documentation Updates..37
7.9 Typical Characteristics: VS = 24 V............................ 14 12.4 Support Resources................................................. 37
7.10 Typical Characteristics: VS = 5 V............................ 17 12.5 Trademarks............................................................. 37
7.11 Typical Characteristics: ±2.375-V to ±12-V Split 12.6 Electrostatic Discharge Caution..............................37
Supply......................................................................... 19 12.7 Glossary..................................................................38

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2020) to Revision C (July 2020) Page
• Changed the status of the DCK package From: Preview To: Production .......................................................... 1

Changes from Revision A (December 2019) to Revision B (June 2020) Page

• Changed the status of the DBV package From: Preview To: Production .......................................................... 1
• Added noise corner information to 10 V, 24 V and 5 V electrical characteristics tables..................................... 5
• Changed offset voltage test conditions for 10 V, 24 V and 5 V supplies for SOIC, SOT23 and SC70 packages.
............................................................................................................................................................................5
• Updated Figure 62. Noninverting Amplifier ......................................................................................................25

Changes from Revision * (August 2019) to Revision A (December 2019) Page

• Changed document status From: Advance Information To: Production Data ....................................................1

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5 Device Comparison Table

IQ /
GBWP SLEW RATE VOLTAGE NOISE (nV/√
DEVICE VS ± (V) CHANNEL AMPLIFIER DESCRIPTION
(MHz) (V/μs) Hz)
(mA)
OPA2810 ±12 3.6 70 192 6 Unity-gain stable FET input
Gain of 6, stable, low-cost CMOS
OPA607 ±2.5 0.9 50 24 3.8
amplifier
THS4631 ±15 13 210 900 7 Unity-gain stable FET input
OPA859 ±2.625 20.5 1800 1150 3.3 Unity-gain stable FET input
OPA818 ±6.5 27.7 2700 1400 2.2 Gain of 7, stable FET input

6 Pin Configuration and Functions

NC 1 8 NC VO 1 5 VS+
VIN± 2 7 VS+

VIN+ 3 6 VO
VS± 2
VS± 4 5 NC
VIN+ 3 4 VIN±

Not to scale
Figure 6-2. 5-Pin SOT23 (DBV) and SC70 (DCK)
Figure 6-1. 8-Pin SOIC (D) Package
Packages

Pin Functions
PIN
TYPE(1) DESCRIPTION
NAME SOIC SOT-23 and SC70
NC 1 — — No internal connection
VIN– 2 4 I Inverting input pin
VIN+ 3 3 I Noninverting input pin
VS– 4 2 P Negative power-supply pin
NC 5 — — No internal connection
VO 6 1 O Output pin
VS+ 7 5 P Positive power-supply pin
NC 8 — — No internal connection

(1) I = input, O = output, and P = power.

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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).(1)
MIN MAX UNIT
VS Supply voltage (total bipolar supplies)(4) ±14 V
VIN Input voltage VS– – 0.5 VS+ + 0.5 V
VIN,Diff Differential input voltage(2) ±7 V
II Continuous input current ±10 mA
TA = –40℃ to +85℃ ±40 mA
IO Continuous output current(3)
TA = 125℃ ±15 mA
PD Continuous power dissipation See Section 7.4
TJ Junction temperature 150 °C
Tstg Storage temperature –65 125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Equal to the lower of ±7 V or total supply voltage.
(3) Long-term continuous output current for electromigration limits.
(4) VS is the total supply voltage given by VS = VS+ – VS– .

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).
MIN NOM MAX UNIT
VS Total supply voltage 4.75 27 V
TA Ambient temperature –40 25 125 °C

7.4 Thermal Information

OPA810
THERMAL METRIC(1) D (SOIC) DBV (SOT-23) DCK (SC70) UNIT
8 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 134.8 174.3 190.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 75.2 94.7 140.1 °C/W
RθJB Junction-to-board thermal resistance 78.2 45.4 69.0 °C/W
ψJT Junction-to-top characterization parameter 25.2 21.6 45.9 °C/W
ψJB Junction-to-board characterization parameter 77.4 45.0 68.8 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Electrical Characteristics: 10 V

Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, common-mode voltage (VCM) = mid-
supply, RL = 1 kΩ connected to mid-supply(5).
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL(3)
AC PERFORMANCE
G = 1, VO = 20 mVPP, RF = 0 Ω 135 C
G = 1, VO = 20 mVPP, RF = 0 Ω,
SSBW Small-signal bandwidth 140 MHz C
CL = 10 pF
G = –1, VO = 20 mVPP 68 C
LSBW Large-signal bandwidth G = 2, VO = 2 VPP 41 MHz C
GBWP Gain-bandwidth product 70 MHz C
Bandwdith for 0.1-dB flatness G = 2, VO = 20 mVPP 16 MHz C
SR Slew rate (20%-80%)(4) G = 2, VO = –2-V to 2-V step 200 V/µs C
Rise time VO = 200-mV step 4 ns C
Fall time VO = 200-mV step 4 ns C
G = 2, VO = 2-V step 47 C
Settling time to 0.1% ns
G = 2, VO = 8-V step 65 C
G = 2, VO = 2-V step 330 C
Settling time to 0.001% ns
G = 2, VO = 8-V step 230 C
G = 1, RF = 0 Ω, (VS– – 0.5 V) to (VS+ +
Input overdrive recovery 55 ns C
0.5 V) input
G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)
Output overdrive recovery 55 ns C
input

Second-order harmonic f = 100 kHz, RL = 1 kΩ, VO = 2 VPP –120 C

HD2 dBc
distortion f = 1 MHz, RL = 1 kΩ, VO = 2 VPP –101 C

Third-order harmonic f = 100 kHz, RL = 1 kΩ, VO = 2 VPP –137 C

HD3 dBc
distortion f = 1 MHz, RL = 1 kΩ, VO = 2 VPP –101 C
en Input-referred voltage noise Flatband, 1/f corner at 1.5 kHz 6.3 nV/√ Hz C
in Input-referred current noise f = 10 kHz 5 fA/√ Hz C
Closed-loop output
zO f = 100 kHz 0.007 Ω C
impedance
DC PERFORMANCE
AOL Open-loop voltage gain f = DC, VO = ±2.5 V 108 120 dB A
SOIC package 100 500
VOS Input offset voltage µV A
DBV and DCK packages 100 715
Input offset voltage drift TA = –40°C to +125°C 2.5 10 µV/°C B
Input bias current 2 20 pA A
Input offset current 1 20 pA A
f = DC, VCM = –3 V to 1 V, SOIC
80 100 A
CMRR Common-mode rejection ratio package dB
TA = –40°C to +125°C, SOIC package 80 B
INPUT
Allowable input differential
See Figure 7-54 ±7 V C
voltage
Common-mode input
In closed-loop configuration 12 || 2 GΩ||pF C
impedance
Differential input capacitance In open-loop configuration 0.5 pF C
Most positive input voltage ΔVOS < 5 mV(1) VS+ + 0.2 VS+ + 0.3 V A

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TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LEVEL(3)
Most negative input voltage ΔVOS < 5 mV(1) VS– – 0.2 VS– – 0.3 V A
Most positive input voltage
See Figure 7-17 VS+ – 2.9 VS+ – 2.5 V C
for main-JFET stage
OUTPUT
VOCRH Output voltage range high RL = 667 Ω VS+ – 0.18 VS+ – 0.11 V A
VOCRH Output voltage range high TA = –40°C to +125°C, RL = 667 Ω VS+ – 0.2 V B
VS– +
VOCRL Output voltage range low RL = 667 Ω VS– + 0.08 V A
0.15
VOCRL Output voltage range low TA = –40°C to +125°C, RL = 667 Ω VS– + 0.2 V B
Linear output drive (sourcing
IO(max) VO = 2.65 V, RL = 51 Ω, ΔVOS < 1 mV 52 75 mA A
and sinking)
ISC Output short-circuit current 100 mA B
CL Capacitive load drive < 3-dB peaking, RS = 0 Ω 10 pF C
POWER SUPPLY
Quiescent current per
IQ 3.7 4.6 mA A
channel
ΔVS = ±2 V(2), SOIC package 79 100 A
PSRR Power-supply rejection ratio dB
TA = –40°C to +125°C, SOIC package 79 B
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product 27 MHz C
Input-referred voltage noise f = 1 MHz 20 nV/√ Hz C
VCM = VS+ – 1.5 V, no load, SOIC
Input offset voltage 1.6 mV A
Package
Input bias current VCM = VS+ – 1.5 V 2 20 pA A

(1) Change in input offset from its value when input is biased to midsupply.
(2) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.
(3) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(4) Lower of the measured positive and negative slew rate.
(5) For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).

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7.6 Electrical Characteristics: 24 V

Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, common-mode voltage (VCM) = mid-
supply, RL = 1 kΩ connected to mid-supply(5).
Test
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Level(3)
AC PERFORMANCE
G = 1, Vo = 20 mVPP, RF = 0 Ω 135 C
G = 1, Vo = 20 mVPP, RF = 0 Ω,
SSBW Small-signal bandwidth 140 MHz C
CL= 10 pF
G = –1, Vo = 20 mVPP 68 C
G = 2 Vo = 2 VPP 44 C
LSBW Large-signal bandwidth MHz
G = 2 Vo = 10 VPP 14 C
GBWP Gain-bandwidth product 70 MHz C
Bandwdith for 0.1-dB flatness G = 2, Vo = 20 mVPP 16 MHz C
G = 2, Vo = –2-V to 2-V step 237 C
SR Slew rate (20%-80%)(4) G = –1, Vo = –2-V to 2-V step 222 V/µs C
G = 2, Vo = –4.5-V to 3.5-V step 254 C
Rise time Vo = 200-mV step 4 ns C
Fall time Vo = 200-mV step 4 ns C
G = 2, Vo = 2-V step 47 C
Settling time to 0.1% ns
G = 2, Vo = 10-V step 70 C
G = 2, Vo = 2-V step 320 C
Settling time to 0.001% ns
G = 2, Vo = 10-V step 200 C
G = 1, RF = 0 Ω, (VS– – 0.5 V) to (VS+ +
Input overdrive recovery 35 ns C
0.5 V) input
G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)
Output overdrive recovery 45 ns C
input
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –118 C

Second-order harmonic f = 100 kHz, RL =1 kΩ, Vo = 10 VPP –108 C

HD2 dBc
distortion f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –112 C
f = 1 MHz, RL=1 kΩ, Vo = 10 VPP –91 C
f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –136 C

Third-order harmonic f = 100 kHz, RL =1 kΩ, Vo = 10 VPP –130 C

HD3 dBc
distortion f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –104 C
f = 1 MHz, RL =1 kΩ, Vo = 10 VPP –91 C
en Input-referred voltage noise Flatband, 1/f corner at 1.5 kHz 6.3 nV/√ Hz C
in Input-referred current noise f = 10 kHz 5 fA/√ Hz C
Closed-loop output
zO f = 100 kHz 0.007 Ω C
impedance
DC PERFORMANCE
AOL Open-loop voltage gain f = DC, Vo = ±8 V 108 120 dB A
SOIC package 100 500
VOS Input offset voltage µV A
DBV and DCK packages 100 550
Input offset voltage drift TA = –40°C to +125°C 2.5 10 µV/°C B
Input bias current 2 20 pA A
Input offset current 1 20 pA A
f = DC, VCM = ±5 V, SOIC package 90 105 A
CMRR Common-mode rejection ratio dB
TA = –40°C to +125°C, SOIC package 90 B

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Test
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Level(3)
INPUT
Allowable input differential
see Figure 7-54 ±7 V C
voltage
Common-mode input
In closed-loop configuration 12 || 2.5 GΩ||pF C
impedance
Differential input capacitance In open-loop configuration 0.5 pF C
Most positive input voltage ΔVOS < 5 mV(1) VS+ + 0.2 VS+ + 0.3 V A
Most negative input voltage ΔVOS < 5 mV(1) VS– – 0.2 VS– – 0.3 V A
Most positive input voltage
See Figure 7-33 VS+ – 2.9 VS+ – 2.5 V C
for main-JFET stage
OUTPUT
RL = 667 Ω VS+ – 0.33 VS+ – 0.22 A
VOCRH Output voltage range high V
TA = –40°C to +125°C, RL = 667 Ω VS+ – 0.36 B
VS– +
RL = 667 Ω VS– + 0.15 A
0.23
VOCRL Output voltage range low V
VS– +
TA = –40°C to +125°C, RL = 667 Ω B
0.33
Linear output drive (sourcing
IO(max) Vo = 7.25 V, RL = 151 Ω, ΔVOS < 1 mV 48 64 mA A
and sinking)
ISC Output short-circuit current 108 mA B
CL Capacitive load drive < 3-dB peaking, RS = 0 Ω 10 pF C
POWER SUPPLY
Quiescent current per
IQ 3.8 4.7 mA A
channel
ΔVS = ±2 V(2), SOIC package 90 105 A
PSRR Power supply rejection ratio dB
TA = –40°C to +125°C, SOIC package 90 B
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product 27 MHz C
Input-referred voltage noise f = 1 MHz 20 nV/√ Hz C
VCM = VS+ – 1.5 V, no load, SOIC
Input offset voltage 1.6 mV A
Package
Input bias current VCM = VS+ – 1.5 V 2 24 pA A

(1) Change in input offset from its value when input is biased to midsupply.
(2) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and -PSRR.
(3) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(4) Lower of the measured positive and negative slew rate.
(5) For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).

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7.7 Electrical Characteristics: 5 V

Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, common-mode voltage (VCM) = 1.25
V, RL = 1 kΩ connected to 1.25 V(5).
Test
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Level(1)
AC PERFORMANCE
G = 1, Vo = 20 mVPP, RF = 0 Ω 133 C
G = 1, Vo = 20 mVPP, RF= 0 Ω,
SSBW Small-signal bandwidth 135 MHz C
CL= 10 pF
G = –1, Vo = 20 mVPP 65 C
LSBW Large-signal bandwidth G = 2 Vo = 2 VPP 36 MHz C
GBWP Gain-bandwidth product 70 MHz C
Bandwdith for 0.1-dB flatness G = 2, Vo = 20 mVPP 16 MHz C
G = 2, Vo = –1-V to 1-V step 134 C
SR Slew rate (20%-80%)(4) G = 2, Vo = –2-V to 2-V step, V/µs
78 C
VS = ±2.5 V
Rise time Vo = 200-mV step 4 ns C
Fall time Vo = 200-mV step 4 ns C
G = 2, Vo = –2-V to 0-V step,
Settling time to 0.1% 100 ns C
VS = ±2.5 V
G = 2, Vo = –2-V to 0-V step,
Settling time to 0.001% 565 ns C
VS = ±2.5 V
G = 1, (VS– – 0.5 V) to (VS+ + 0.5 V)
Input overdrive recovery 76 ns C
input, VS = ±2.5 V
G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)
Output overdrive recovery 93 ns C
input, VS = ±2.5 V

Second-order harmonic f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –102 C

HD2 dBc
distortion f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –81 C

Third-order harmonic f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –114 C

HD3 dBc
distortion f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –92 C
en Input-referred voltage noise Flatband, 1/f corner at 1.5 kHz 6.3 nV/√ Hz C
in Input-referred current noise f = 10 kHz 5 fA/√ Hz C
Closed-loop output
zO f = 100 kHz 0.007 Ω C
impedance
DC PERFORMANCE
AOL Open-loop voltage gain f = DC, Vo = 1.25 V to 3.25 V 104 118 dB A
SOIC package 100 550
VOS Input offset voltage µV A
DBV and DCK packages 100 760
Input offset voltage drift TA = –40°C to +125°C 2.5 10 µV/°C B
Input bias current 2 20 pA A
Input offset current 1 20 pA A
f = DC, VCM = 0.75 V to 1.75 V, SOIC
73 92 A
CMRR Common-mode rejection ratio package dB
TA = –40°C to +125°C, SOIC package 73 B
INPUT
Allowable input differential
See Figure 7-54 ±5 V C
voltage
Common-mode input
In closed-loop configuration 12 || 2.5 GΩ||pF C
impedance
Differential input capacitance In open-loop configuration 0.5 pF C

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Test
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Level(1)
Most positive input voltage ΔVOS < 5 mV(2) VS+ + 0.2 VS+ + 0.3 V A
Most negative input voltage ΔVOS < 5 mV(2) VS- – 0.2 VS- – 0.3 V A
Most positive input voltage
See Figure 7-41 VS+ – 2.9 VS+ – 2.5 V C
for main-JFET stage
OUTPUT
RL = 667 Ω VS+ – 0.12 VS+ – 0.09 A
VOCRH Output voltage range high V
TA = –40°C to +125°C, RLOAD = 667 Ω VS+ – 0.15 B
VS– +
RL = 667 Ω VS–+ 0.06 A
0.11
VOCRL Output voltage range low V
VS– +
TA = –40°C to +125°C, RL = 667 Ω B
0.15
Linear output drive (sourcing VO = 1.4 V, RL = 27.5 Ω, ΔVOS < 1
IO(max) 50 64 mA A
and sinking) mV, VS+ = 3 V and VS– = –2 V
ISC Output short-circuit current 96 mA B
CL Capacitive load drive < 3-dB peaking, RS = 0 Ω 10 pF C
POWER SUPPLY
Quiescent current per
IQ 3.15 3.7 4.5 mA A
channel
ΔVS = ±0.5 V(3), SOIC package 78 100 A
PSRR Power-supply rejection ratio dB
TA = –40°C to +125°C, SOIC package 78 B
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product 27 MHz C
Input-referred voltage noise f = 1 MHz 20 nV/√ Hz C
VCM = VS+ – 1.5 V, no load, SOIC
Input offset voltage 1.6 mV A
Package
Input bias current VCM = VS+ – 1.5 V 2 20 pA A

(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) Change in input offset from its value when input is biased to 0 V.
(3) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and -PSRR.
(4) Lower of the measured positive and negative slew rate.
(5) For AC specifications, VS+ = 3.5 V, VS– = –1.5 V, G = 2 V/V, RF = 1 kΩ, CL = 4.7 pF, VCM = 0 V (unless otherwise noted).

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7.8 Typical Characteristics: VS = 10 V

At VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC
specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted).

3 3

0
0
-3
Normalized Gain (dB)

Normalized Gain (dB)

-3
-6

-9 -6

-12
-9
Gain = 1 V/V
-15 Gain = 1 V/V
Gain = 2 V/V -12
-18 Gain = 5 V/V RL = 500 :
Gain = 10 V/V RL = 1 k:
-21 -15
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) D041
Frequency (Hz) D042

See Figure 9-1 and Figure 9-2, VO = 20 mVPP See Figure 9-1, VO = 20 mVPP, gain = 1 V/V, RF = 0 Ω

Figure 7-1. Small-Signal Frequency Response vs Figure 7-2. Small-Signal Frequency Response vs
Gain Output Load
6 6

3 3

0 0
Normalized Gain (dB)

Normalized Gain (dB)

-3 -3

-6 -6

-9 -9

-12 -12
RS = 0 :, CL = 4.7 pF
-15 RS = 0 :, CL = 10 pF -15 RS = 0 :, CL = 4.7 pF
RS = 56 :, CL = 22 pF RS = 0 :, CL = 10 pF
-18 RS = 40 :, CL = 33 pF -18 RS = 0 :, CL = 22 pF
RS = 47 :, CL = 47 pF RS = 56 :, CL = 47 pF
-21 -21
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) D044
Frequency (Hz) D045

See Figure 9-1 and Figure 8-1, See Figure 9-1and Figure 8-1, VO = 20 mVPP, gain = 2 V/V
VO = 20 mVPP, gain = 1 V/V, RF = 0 Ω

Figure 7-3. Small-Signal Frequency Response vs Figure 7-4. Small-Signal Frequency Response vs
CL CL
3 3

0 0

-3 -3
Normalized Gain (dB)

Normalized Gain (dB)

-6 -6

-9 -9

-12 -12

-15 VO = 200 mVPP -15 VO = 200 mVPP

VO = 1 VPP VO = 1 VPP
-18 VO = 2 VPP -18 VO = 2 VPP
VO = 4 VPP VO = 4 VPP
-21 -21
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) D046
Frequency (Hz) D047

See Figure 9-1, gain = 1 V/V, RF = 0 Ω See Figure 9-1, gain = 2 V/V

Figure 7-5. Large-Signal Frequency Response vs Figure 7-6. Large-Signal Frequency Response vs
Output Voltage Output Voltage

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1 -60
Gain = 1 V/V HD2, RL = 1 k:
0.8 Gain = 1 V/V -70 HD3, RL = 1 k:
0.6 Gain = 2 V/V -80 HD2, RL = 500 :

Harmonic Distortion (dBc)

Gain = 5 V/V HD3, RL = 500 :
Normalized Gain (dB)

0.4 Gain = 10 V/V -90

0.2 -100
0 -110
-0.2 -120
-0.4 -130
-0.6 -140
-0.8 -150
-1 -160
100k 1M 10M 100M 1k 10k 100k 1M
Frequency (Hz) D051
Frequency (Hz) D048

See Figure 9-1 and Figure 9-2, VO = 20 mVPP See Figure 9-1, gain = 2 V/V

Figure 7-7. Small-Signal Response Flatness vs Figure 7-8. Harmonic Distortion vs Frequency
Gain
-60 -60
HD2, RL = 1 k: HD2, Gain = 1
-70 HD3, RL = 1 k: -70 HD3, Gain = 1
-80 HD2, RL = 500 : -80 HD2, Gain = 2
Harmonic Distortion (dBc)

Harmonic Distortion (dBc)

HD3, RL = 500 : HD3, Gain = 2
-90 -90 HD2, Gain = -1
HD3, Gain = -1
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
-150 -150
-160 -160
1k 10k 100k 1M 1k 10k 100k 1M
Frequency (Hz) D049
Frequency (Hz) D050

See Figure 9-2, gain = –1 V/V See Figure 9-1 and Figure 9-2, RF = 0 Ω

Figure 7-9. Harmonic Distortion vs Frequency Figure 7-10. Harmonic Distortion vs Gain
0.15 45
Overshoot, VO = 2 VPP
40 Undershoot, VO = 2 VPP
0.1 Overshoot, VO = 200 mVPP
Overshoot/Undershoot (%)

35 Undershoot, VO = 200 mVPP

Output Voltage (V)

30
0.05
25

20
0
15

-0.05 10

-0.1 0
Time (100 ns/div) 5 10 15 20 25 30 35 40 45 50
D052
Load Capacitance (pF) D053

See Figure 9-1, gain = 1 V/V, RF = 0 Ω, CL = 10 pF See Figure 9-1, gain = 1 V/V, RF = 0 Ω

Figure 7-11. Small-Signal Transient Response Figure 7-12. Overshoot and Undershoot vs CL

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6 6

4 4
Input and Output Voltage (V)

Input and Output Voltage (V)

2 2

0 0

-2 -2

-4 -4
VIN VIN x -1 Gain
VOUT VO
-6 -6
0 200 400 600 800 1000 1200 1400 1600 0 200 400 600 800 1000 1200 1400
Time (nsec) D054
Time (nsec) D055

See Figure 9-1, gain = 1 V/V, RF = 0 Ω See Figure 9-2, gain = –1 V/V

Figure 7-13. Input Overdrive Recovery Figure 7-14. Output Overdrive Recovery
6 120

90

Output Short-Circuit Current (mA)

4
60
Output Voltage (V)

2 30

0 Sourcing
0 Sourcing
Sinking Sinking
-30

-2 -60

-90
-4
-120

-6 -150
0 10 20 30 40 50 60 70 80 90 -40 -20 0 20 40 60 80 100 120 140
Output Current (mA) D056
Ambient Temperature (qC) D057

Output saturated and then short-circuited

Figure 7-15. Output Voltage vs Load Current Figure 7-16. Output Short-Circuit Current vs
Ambient Temperature
1200

800
Input Offset Voltage (PV)

400

-400

-800

-1200
-6 -4 -2 0 2 4 6
Input Common-Mode Voltage (V) D058

Measured for 12 units

Figure 7-17. Input Offset Voltage vs Input Common-Mode Voltage

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7.9 Typical Characteristics: VS = 24 V

At VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC
specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted).

3 3

0 0

-3 -3
Normalized Gain (dB)

Normalized Gain (dB)

-6 -6

-9 -9

-12 -12

-15 Gain = 1 V/V -15

Gain = 1 V/V VCM = 0 V
-18 Gain = 2 V/V -18 VCM = 9 V
Gain = 5 V/V VCM = 11 V
-21 -21
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) D071
Frequency (Hz) D072

See Figure 9-1 and Figure 9-2, VO = 20 See Figure 9-1, VO = 20 mVPP, gain = 1 V/V, CL = 4.7 pF, RF =
mVPP 0Ω

Figure 7-18. Noninverting Small-Signal Frequency Figure 7-19. Small-Signal Frequency Response vs
Response vs Gain Output Common-Mode Voltage
3 3

0 0

-3 -3
Normalized Gain (dB)

Normalized Gain (dB)

-6 -6

-9 -9

-12 -12
VO = 200 mVPP
-15 VO = 200 mVPP -15 VO = 1 VPP
VO = 1 VPP VO = 2 VPP
-18 VO = 2 VPP -18 VO = 4 VPP
VO = 4 VPP VO = 10 VPP
-21 -21
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) D074
Frequency (Hz) D075

See Figure 9-1, gain = 1 V/V, RF = 0 Ω See Figure 9-1, gain = 2 V/V

Figure 7-20. Large-Signal Frequency Response vs Figure 7-21. Large-Signal Frequency Response vs
Output Voltage Vo
-20 -40
HD2, VO = 2 VPP HD2, VO = 2 VPP
-40 HD3, VO = 2 VPP HD3, VO = 2 VPP
HD2, VO = 10 VPP -60 HD2, VO = 10 VPP
Harmonic Distortion (dBc)

Harmonic Distortion (dBc)

HD3, VO = 10 VPP HD3, VO = 10 VPP

-60 HD2, VO = 20 VPP HD2, VO = 20 VPP
HD3, VO = 20 VPP -80 HD3, VO = 20 VPP
-80
-100
-100
-120
-120

-140 -140

-160 -160
1k 10k 100k 1M 1k 10k 100k 1M
Frequency (Hz) D076
Frequency (Hz) D077

See Figure 9-1, gain = 2 V/V See Figure 9-2, gain = –1 V/V

Figure 7-22. Harmonic Distortion vs Frequency vs Figure 7-23. Harmonic Distortion vs Frequency vs
Vo Vo

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0.15 6

4
0.1
Output Voltage (V)

Output Voltage (V)

2
0.05
0
0
-2

-0.05
-4

-0.1 -6
Time (100 ns/div) Time (100 ns/div)
D078 D079

See Figure 9-1, gain = 1 V/V, RF = 0 Ω, CL = 10 pF See Figure 9-1, gain = 1 V/V, RF = 0 Ω

Figure 7-24. Small-Signal Transient Response Figure 7-25. Large-Signal Transient Response
12 6
VO = 2 VPP VO = 4 VPP
VO = 10 VPP VO = 10 VPP
8 VO = 20 VPP 4

Output Voltage (V)

Output Voltage (V)

4 2

0 0

-4 -2

-8 -4

-12 -6
Time (100 ns/div) Time (50 ns/div)
D080 D081

See Figure 9-1, gain = 2 V/V See Figure 9-2, gain = –1 V/V

Figure 7-26. Large-Signal Transient Response Figure 7-27. Large-Signal Transient Response
25 15
12
Input and Output Voltage (V)

20 9
Overshoot/Undershoot (%)

6
15 Overshoot, VO = 2 VPP 3
Undershoot, VO = 2 VPP 0
Overshoot, VO = 200 mVPP
10 Undershoot, VO = 200 mVPP -3
-6
5 -9
-12 VIN
VOUT
0 -15
5 10 15 20 25 30 35 40 45 50 55 60 0 200 400 600 800
Load Capacitance (pF) D082
Time (nsec) D083

See Figure 9-1, gain = 1 V/V, RF = 0 Ω See Figure 9-1, gain = 1 V/V, RF = 0 Ω

Figure 7-28. Overshoot and Undershoot vs CL Figure 7-29. Input Overdrive Recovery

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15 14
12
10
Input and Output Voltage (V)

9
6 6

Output Voltage (V)

3
2
Sourcing
0 Sinking
-2
-3
-6 -6
-9
VIN x -1 Gain -10
-12
VO
-15 -14
0 200 400 600 800 1000 1200 1400 0 10 20 30 40 50 60 70 80 90
Time (nsec) D084
Output Current (mA) D085

See Figure 9-2, gain = –1 V/V

Figure 7-30. Output Overdrive Recovery Figure 7-31. Output Voltage Range vs Load Current
150 1500
120
Output Short-Circuit Current (mA)

90 1000

Input Offset Voltage (PV)

60
500
30
Sourcing
0 Sinking
0
-30
-60
-500
-90
-120 -1000
-150
-180 -1500
-40 -20 0 20 40 60 80 100 120 140 -12.5 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10 12.5
Ambient Temperature (qC) D086
Input Common-Mode Voltage (V) D087

Output saturated and then short-circuited Measured for 12 units

Figure 7-32. Output Short-Circuit Current vs Figure 7-33. Input Offset Voltage vs Input
Ambient Temperature Common-Mode Voltage

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7.10 Typical Characteristics: VS = 5 V

At VS+ = 5 V, VS– = 0 V, VCM= 1.25 V, RL = 1 kΩ, output is biased to midsupply, and TA ≈ 25°C. For AC
specifications, VS+ = 3.5 V, VS– = –1.5 V, VCM= 0 V, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless
otherwise noted).

3 0.15

0
0.1
-3
Normalized Gain (dB)

Output Voltage (V)

-6 0.05
-9

-12 0

-15 Gain = 1 V/V

Gain = 1 V/V -0.05
-18 Gain = 2 V/V
Gain = 5 V/V
-21 -0.1
100k 1M 10M 100M Time (100 ns/div)
Frequency (Hz) D010 D011

See Figure 9-1 and Figure 9-2, VO = 20 mVPP See Figure 9-1, gain = 1 V/V, RF = 0 Ω, CL = 10 pF

Figure 7-34. Small-Signal Response vs Gain Figure 7-35. Small-Signal Transient Response
60 3
55 Overshoot, VO = 2 VPP
Undershoot, VO = 2 VPP
50 Overshoot, VO = 200 mVPP 2
Input and Output Voltage (V)
Overshoot/Undershoot (%)

45 Undershoot, VO = 200 mVPP

40 1
35
30 0
25
20 -1
15
10 -2
VIN
5 VOUT
0 -3
5 10 15 20 25 30 35 40 45 50 0 200 400 600 800 1000 1200 1400
Load Capacitance (pF) D012
Time (nsec) D014

See Figure 9-1, gain = 1 V/V, RF = 0 Ω See Figure 9-1, gain = 1 V/V, RF = 0 Ω

Figure 7-36. Overshoot and Undershoot vs CL Figure 7-37. Input Overdrive Recovery
3 3

2 2
Input and Output Voltage (V)

Output Voltage (V)

1 1

Sourcing
0 0 Sinking

-1 -1

-2 -2
VIN x -1 Gain
VO
-3 -3
0 200 400 600 800 1000 1200 1400 0 10 20 30 40 50 60 70 80 90
Time (nsec) D013
Output Current (mA) D015

See Figure 9-2, gain = –1 V/V

Figure 7-38. Output Overdrive Recovery Figure 7-39. Output Voltage Range vs Output
Current

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125 1000
100
Output Short-Circuit Current (mA)

75

Input Offset Voltage (PV)

500
50
25
0 0
-25
-50
-500
-75
-100
-125 -1000
-40 -20 0 20 40 60 80 100 120 140 -3 -2 -1 0 1 2 3
Ambient Temperature (qC) D016
Input Common-Mode Voltage (V) D017

Output saturated and then short-circuited Measured for 12 units

Figure 7-40. Output Short-Circuit Current vs Figure 7-41. Input Offset Voltage vs Input
Ambient Temperature Common-Mode Voltage

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7.11 Typical Characteristics: ±2.375-V to ±12-V Split Supply

At VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted).

130 180 3
Magnitude
110 Phase 160
Open-Loop Gain Magnitude (dB)

Normalized Gain (dB)

Open-Loop Phase (o)
90 140
-3
70 120
-6
50 100
-9
30 80

-12 VS = 5 V
10 60 VS = 10 V
VS = 24 V
-10 40 -15
10 100 1k 10k 100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) D109
Frequency (Hz) D101

Simulated with no output load See Figure 9-1, gain = 1 V/V, RF = 0 Ω

Figure 7-42. Open-Loop Gain and Phase vs Figure 7-43. Large-Signal Response vs Supply
Frequency Voltage
3 -60
HD2, VS = 5 V
-70 HD3, VS = 5 V
0 HD2, VS = 10 V
-80
Harmonic Distortion (dBc)

HD3, VS = 10 V
Normalized Gain (dB)

-90 HD2, VS = 24 V
-3 HD3, VS = 24 V
-100
-6 -110
-120
-9
-130

VS= 5 V -140
-12
VS= 10 V -150
VS= 24 V
-15 -160
100k 1M 10M 100M 1k 10k 100k 1M
Frequency (Hz) D102
Frequency (Hz) D103

See Figure 9-1, gain = 2 V/V See Figure 9-1, gain = 2 V/V

Figure 7-44. Large-Signal Response vs Supply Figure 7-45. Harmonic Distortion vs Frequency vs
Voltage Supply Voltage
-60 100
HD2, VS = 5 V
-70 HD3, VS = 5 V
HD2, VS = 10 V
Input Voltage Noise (nV/—Hz)

-80
Harmonic Distortion (dBc)

HD3, VS = 10 V
-90 HD2, VS = 24 V
HD3, VS = 24 V
-100
-110 10
-120
-130
-140
-150
-160 1
1k 10k 100k 1M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D104
Frequency (Hz) D103

See Figure 9-2, gain = –1 V/V Measured then fit to ideal 1/f model

Figure 7-46. Harmonic Distortion vs Frequency vs Figure 7-47. Input Voltage Noise Density vs
Supply Voltage Frequency

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10000 100
90
Aux Input Voltage Noise (nV/—Hz)

80

Output Impedance (:)

70
1000
60
50
40
100
30
20
10
10 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) D106
Frequency (Hz) D108

Measured then fit to ideal 1/f model

Figure 7-48. Auxiliary Input Stage Voltage Noise Figure 7-49. Open-Loop Output Impedance vs
Density vs Frequency Frequency
120 120
Common-Mode Rejection Ratio (dB)

Power Supply Rejection Ratio (dB)

100
100

80
80
60
60
40

40
20

20 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) D110
Frequency (Hz) D111

VS = 10 V and 24 V VS = 5 V and 10 V

Figure 7-50. Common-Mode Rejection Ratio vs Figure 7-51. Power Supply Rejection Ratio vs
Frequency Frequency
120 20
PSRR VS+
PSRR VS- 16
Power Supply Rejection Ratio (dB)

100
12
Input Bias Current (pA)

8
80
4
60 0
-4
40
-8
-12
20
-16
0 -20
100 1k 10k 100k 1M 10M 100M -12.5 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10 12.5
Frequency (Hz) D112
Input Common-Mode Voltage (V) D118

Simulated curves, VS = 24 V VS = ±12 V

Figure 7-52. Power Supply Rejection Ratio vs Figure 7-53. Input Bias Current vs Input Common-
Frequency Mode Voltage

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300 4.2
Non-Inverting Input Bias Current (PA)

200

Quiescent Current (mA)

4
100

0 3.8

-100
3.6
-200
TA = 25qC
TA = 125qC
-300 3.4
-7.5 -6 -4.5 -3 -1.5 0 1.5 3 4.5 6 7.5 -50 -25 0 25 50 75 100 125 150
Differential Input Voltage (V) D115
Ambient Temperature (qC) D117

Abs (VIN,Diff (max)) = VS when VS < 7 V 32 units, SOIC package, VS = ±5 V

Figure 7-54. Input Bias Current vs Differential Input Figure 7-55. Quiescent Current vs Ambient
Voltage Temperature
600 24000
22000
400 20000
Input Offset Voltage (PV)

No. of Units in Each Bin

18000
200
16000
0 14000
12000
-200 10000
8000
-400
6000
4000
-600
2000
-800 0
3.65

3.75

3.85

3.95

4.05
3.6

3.7

3.8

3.9

4.1
4
-50 -25 0 25 50 75 100 125 150
Ambient Temperature (qC) D116 D120
Quiescent Current (mA)
32 units, SOIC package
27000 units, µ = 3.82 mA, σ = 17 µA, VS = 24 V

Figure 7-56. Input Offset Voltage vs Ambient

Figure 7-57. Quiescent Current Distribution
Temperature
14000 14

12000 12
No. of Units in Each Bin

No. of Units in Each Bin

10000 10

8000 8

6000 6

4000 4

2000 2

0 0
-500

-400

-300

-200

-100

100

200

300

400

500
0

-8

-6

-4

-2

8
-10

10

D113 Input Offset Voltage Drift (PV/qC) D114

Input Offset Voltage (PV)
–40°C to +125°C fit, 32 units, µ = –0.15 µV/°C, σ = 2.5 µV/°C
27000 units, µ = 16 µV, σ = 63 µV, VS = 24 V

Figure 7-59. Input Offset Voltage Drift Distribution

Figure 7-58. Input Offset Voltage Distribution

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8 Detailed Description
8.1 Overview
The OPA810 is a single-channel, field-effect transistor (FET)-input, unity-gain stable, voltage-feedback
operational amplifier with extremely low input bias current across its common-mode input voltage range. The
OPA810, characterized to operate over a wide supply range of 4.75 V to 27 V, has a small-signal, unity-gain
bandwidth of 140 MHz and offers both excellent DC precision and dynamic AC performance at low quiescent
power. The OPA810 is fabricated on Texas Instrument's proprietary, high-speed SiGe BiCMOS process and
achieves significant performance improvements over comparable FET-input amplifiers at similar levels of
quiescent power. With a gain-bandwidth product (GBWP) of 70 MHz, extremely high slew rate (200 V/µs), and
low noise (6.3 nV/√ Hz), the OPA810 is ideal in a wide range of data acquisition and signal processing
applications. The OPA810 includes input clamps to allow maximum input differential voltage of up to 7 V, making
the device suitable for use with multiplexers and for processing signals with fast transients. The device achieves
these benchmark levels of performance while consuming a typical quiescent current (IQ) of 3.7 mA per channel.
The OPA810 can source and sink large amounts of current without degradation in its linearity performance. The
wide bandwidth of the OPA810 implies that the device has low output impedance across a wide frequency
range, thereby allowing the amplifier to drive capacitive loads up to 10 pF without requiring output isolation. This
device is suitable for a wide range of data acquisition, test and measurement front-end buffer, impedance
measurement, power analyzer, wideband photodiode transimpedance, and signal processing applications.
8.2 Functional Block Diagram

VS+

OPA810

VIN+
+ Aux-Stage

±
EN CC

+ JFET-Stage VO

±
EN

±
±
+

VS+ ±2.5 V
VIN±

VS±

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8.3 Feature Description

8.3.1 OPA810 Architecture
The OPA810 features a true high-impedance input stage including a JFET differential-input pair main stage and
a CMOS differential-input auxiliary (aux) stage operational within 2.5 V of the positive supply voltage. The bias
current is limited to a maximum of 20 pA throughout the common-mode input range of the amplifier. The Section
8.2 section provides a block diagram representation for the input stage of the OPA810. The amplifier exhibits
superior performance for high-speed signals (distortion, noise, and input offset voltage) while the aux stage
enables rail-to-rail inputs and prevents phase reversal. The device exhibits a CMRR and PSRR of 75 dB (typical)
when the input common-mode is in aux stage.
The OPA810 also includes input clamps that enable the maximum input differential voltage of up to 7 V (lower of
7 V and total supply voltage). This architecture offers significantly greater differential input voltage capability as
compared to one to two times the diode forward voltage drop maximum rating in standard amplifiers, and makes
this device suitable for use with multiplexers and processing of signals with fast transients. The input bias
currents are also clamped to maximum 300 µA, as Figure 7-54 shows, which does not load the previous driver
stage or require current-limiting resistors (except limiting current through the input ESD diodes when input
common-mode voltages are greater than the supply voltages). This feature also enables this amplifier to be used
as a comparator in systems that require an amplifier and a comparator for signal gain and fault detection,
respectively. For the lowest offset, distortion, and noise performance, limit the common-mode input voltage to the
main JFET-input stage (greater than 2.5 V away from the positive supply).
The OPA810 is a rail-to-rail output amplifier and swings to either of the rails at the output, as shown in Figure
7-15 for 10-V supply operation. This is particularly useful for inputs biased near the rails or when the amplifier is
configured in a closed-loop gain such that the output approaches the supply voltage. When the output saturates,
it recovers with 55 ns when inputs exceed the supply voltages by 0.5 V in an G = –1 V/V inverting gain with a
10–V supply. The outputs are short-circuit protected with the limits of Figure 7-16.
As Figure 8-1 shows, an amplifier phase margin reduces and becomes unstable when driving a capacitive load
(CL) at its output. Using a series resistor (RS) between the amplifier output and load capacitance introduces a
zero that cancels the pole formed by the amplifier output impedance and CL in the open-loop transfer function.
The OPA810 drives capacitive loads of up to 10 pF without causing instability. It is recommended to use a series
resistor for larger load capacitance values, as Figure 7-3 shows for OPA810 configured as a unity-gain buffer. As
Figure 7-4 shows, when used in a gain larger than 1 V/V, the OPA810 is able to drive a load capacitance larger
than 10 pF without the need for a series resistor at its output.

RS
VO
VIN +
CL RL

Figure 8-1. OPA810 Driving Capacitive Load

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8.3.2 ESD Protection

As Figure 8-2 shows, all device pins are protected with internal ESD protection diodes to the power supplies.
These diodes provide moderate protection to input overdrive voltages above the supplies. The protection diodes
can typically support 10-mA continuous input and output currents. The differential input clamps only limit the bias
current when the input common-mode voltages are within the supply voltage range, whereas current-limiting
series resistors must be added at the inputs if common-mode voltages higher than the supply voltages are
possible. Keep these resistor values as low as possible because using high values degrades noise performance
and frequency response.
VS+

Power Sup ply

VIN+ ESD Cell

+
300 A
ICLAMP ± VO

VIN±

VS±

Figure 8-2. Internal ESD Protection

8.4 Device Functional Modes

8.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
To facilitate testing with common lab equipment, the OPA810 can be configured to allow for split-supply
operation (see the OPA2810DGK Evaluation Module user guide). This configuration eases lab testing because
the mid-point between the power rails is ground, and most signal generators, network analyzers, oscilloscopes,
spectrum analyzers, and other lab equipment reference the inputs and outputs to ground. Figure 9-1 depicts the
OPA810 configured as a noninverting amplifier and Figure 9-2 illustrates the OPA810 configured as an inverting
amplifier. For split-supply operation referenced to ground, the power supplies VS+ and VS- are symmetrical
around ground and VREF is at GND. Split-supply operation is preferred in systems where the signals swing
around ground because of the ease-of-use; however, the system requires two supply rails.
8.4.2 Single-Supply Operation (4.75 V to 27 V)
Many newer systems use a single power supply to improve efficiency and reduce the cost of the extra power
supply. The OPA810 can be used with a single supply (with the negative supply set to ground) with no change in
performance if the input and output are biased within the linear operation of the device. To change the circuit
from split supply to a balanced, single-supply configuration, level shift all voltages by half the difference between
the power-supply rails. An additional advantage of configuring an amplifier for single-supply operation is that the
effects of PSRR are minimized because the low-supply rail is grounded. See the Single-Supply Op Amp Design
Techniques application report for examples of single-supply designs.

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

9.1.1 Amplifier Gain Configurations
The OPA810 is a classic voltage-feedback amplifier with each channel having two high-impedance inputs and a
low-impedance output. Standard application circuits (as shown in Figure 9-1 and Figure 9-2) include the
noninverting and inverting gain configurations. The DC operating point for each configuration is level-shifted by
the reference voltage VREF that is typically set to midsupply in single-supply operation. VREF is often connected
to ground in split-supply applications.
VSIG VS+

VREF (1+RF/R G)VSIG

VIN +
VO VREF
VREF -
RG
VS±

RF

Figure 9-1. Noninverting Amplifier

VS+
±(RF/RG)VSIG
VSIG VREF +
VO VREF
VREF VIN ±
RG
VS±

RF

Figure 9-2. Inverting Amplifier

Equation 1 shows the closed-loop gain of an amplifier in a noninverting configuration.

§ RF ·
VO VIN ¨ 1 ¸ VREF
© RG ¹ (1)

Equation 2 shows the closed-loop gain of an amplifier in an inverting configuration.

§ RF ·
VO VIN ¨ ¸ VREF
© RG ¹ (2)

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9.1.2 Selection of Feedback Resistors

The OPA810 is a classic voltage feedback amplifier with each channel having two high-impedance inputs and a
low-impedance output. Standard application circuits (as shown in Figure 9-3 and Figure 9-4) include the
noninverting and inverting gain configurations. The DC operating point for each configuration is level-shifted by
the reference voltage VREF which is typically set to midsupply in single-supply operation. VREF is often connected
to ground in split-supply applications.
VSIG
VS+
VREF (1+RF/RG)VSIG
VIN +
VO VREF
±
RG
VS-
VREF
RF

Figure 9-3. Noninverting Amplifier

VS+
-(RF/RG)VSIG
VSIG VREF +
VO VREF
VREF VIN ±
RG
VS-

RF

Figure 9-4. Inverting Amplifier

Equation 3 shows the closed-loop gain of an amplifier in noninverting configuration.

§ RF ·
VO VIN ¨ 1 ¸ VREF
© RG ¹ (3)

Equation 4 shows the closed-loop gain of an amplifier in an inverting configuration.

§ RF ·
VO VIN ¨ ¸ VREF
© RG ¹ (4)

The magnitude of the low-frequency gain is determined by the ratio of the magnitudes of the feedback resistor
(RF) and the gain setting resistor RG. The order of magnitudes of the individual values of RF and RG offer a
trade-off between amplifier stability, power dissipated in the feedback resistor network, and total output noise.
The feedback network increases the loading on the amplifier output. Using large values of the feedback resistors
reduces the power dissipated at the amplifier output. On the other hand, this increases the inherent voltage and
amplifier current noise contribution seen at the output while lowering the frequency at which a pole occurs in the
feedback factor (β). This pole causes a decrease in the phase margin at zero-gain crossover frequency and
potential instability. Using small feedback resistors increases power dissipation and also degrades amplifier
linearity due to a heavier amplifier output load. Figure 9-5 illustrates a representative schematic of the OPA810 in
an inverting configuration with the input capacitors shown.

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CCM VS+
-(RF/RG)VSIG
VSIG +
CDIFF VO VREF
VIN ±
VREF
RG CPCB
CCM VS-

RF

Figure 9-5. Inverting Amplifier with Input Capacitors

The effective capacitance at the amplifier inverting input pin is shown in Equation 5, which forms a pole in β at a
cut-off frequency of Equation 6.

CIN CCM CDIFF CPCB (5)

where
• CCM is the amplifier common-mode input capacitance
• CDIFF is the amplifier differential input capacitance
• CPCB is the PCB parasitic capacitance

1
FC
2SRFCIN
(6)

For low-power systems, greater the values of the feedback resistors, the earlier in frequency does the phase
margin begin to reduce and cause instability. Figure 9-6 and Figure 9-7 illustrate the loop gain magnitude and
phase plots, respectively, for the OPA810 simulation in TINA-TI configured as an inverting amplifier with values
of feedback resistors varying by orders of magnitudes.

120 100
110 RF = 200 :, RG = 50 :
RF = 10 k:, RG = 2.5 k: 90
100
RF = 1 M:, RG = 250 k: 80
90
80 70
Phase (Degrees)

70
60
Gain (dB)

60
50 50
40
40
30
20 30
10 20 RF = 200 :, RG = 50 :
0 RF = 10 k:, RG = 2.5 k:
10
-10 RF = 1 M:, RG = 250 k:
-20 0
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz) D802
D801

Figure 9-6. Loop-Gain vs Frequency for Circuit of Figure 9-7. Loop-Gain Phase vs Frequency for
Figure 9-5 Circuit of Figure 9-5

A lower phase margin results in peaking in the frequency response and lower bandwidth as Figure 9-8 shows,
which is synonymous with overshoot and ringing in the pulse response results. The OPA810 offers a flat-band
voltage noise density of 6.3 nV/√ Hz. TI recommends selecting an RF so the voltage noise contribution does not
exceed that of the amplifier. Figure 9-9 shows the voltage noise density variation with value of resistance at
25°C. A 2-kΩ resistor exhibits a thermal noise density of 5.75 nV/√ Hz which is comparable to the flatband noise
of the OPA810. Hence, TI recommends using an RF lower than 2 kΩ while being large enough to not dissipate

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excessive power for the output voltage swing and supply current requirements of the application. The Section
9.1.3 section shows a detailed analysis of the various contributors to noise.

30 1000
RF = 200 :, RG = 50 :
RF = 10 k:, RG = 2.5 k:

Voltage Noise Density (nV/—Hz)

RF = 1 M:, RG = 250 k:
20 100
Gain (dB)

10 10

0 1

0.1
-10
10 100 1k 10k 100k 1M 10M
10k 100k 1M 10M 100M
Resistance (:)
Frequency (Hz) D806
D803

Figure 9-8. Closed-Loop Gain vs. Frequency for Figure 9-9. Thermal Noise Density vs Resistance
Circuit of Figure 9-5

9.1.3 Noise Analysis and the Effect of Resistor Elements on Total Noise
The OPA810 provides a low input-referred broadband noise voltage density of 6.3 nV/√ Hz while requiring a low
3.7-mA quiescent supply current. To take full advantage of this low input noise, careful attention to the other
possible noise contributors is required. Figure 9-10 shows the operational amplifier noise analysis model with all
the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms
in nV/√ Hz or pA/√ Hz.
ENI

+
EO
RS IBN ±

ERS

4kTR S
RF

4kT IBI 4kTR F

RG
RG
4kT 1.6E 20 J
at 290q K

Figure 9-10. Operational Amplifier Noise Analysis Model

The total output spot noise voltage is computed as the square root of the squared contributing terms to the
output noise voltage. This computation adds all the contributing noise powers at the output by superposition,
then calculates the square root to get back to a spot noise voltage. Figure 9-10 shows the general form for this
output noise voltage using the terms shown in Equation 7.

2
EO = (E
NI
2 2
)
+ (IBNRS ) + 4kTRS NG2 + IBIRF ( ) + 4kTRFNG (7)

Dividing this expression by the noise gain (NG = 1 + RF / RG) shows the equivalent input referred spot noise
voltage at the noninverting input; see Equation 8.

2
æI R ö 4kTRF
EN = ENI2 + (IBNRS ) + 4kTRS + ç BI F ÷ +
2

è NG ø NG (8)

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Substituting large resistor values into Equation 8 can quickly dominate the total equivalent input referred noise. A
source impedance on the noninverting input of 2-kΩ adds a Johnson voltage noise term similar to that of the
amplifier (6.3 nV/√ Hz).
Table 9-1 compares the noise contributions from the various terms when the OPA810 is configured in a
noninverting gain of 5 V/V as Figure 9-11 shows. Two cases are considered where the resistor values in case 2
are 10x the resistor values in case 1. The total output noise in case 1 is 34 nV/√ Hz while the noise in case 2 is
51.5 nV/√ Hz. The large value resistors in case 2 dilute the benefits of selecting a low noise amplifier like the
OPA810. To minimize total system noise, reduce the size of the resistor values. This increases the amplifiers
output load and results in a degradation of distortion performance. The increased loading increases the dynamic
power consumption of the amplifier. The circuit designer must make the appropriate tradeoffs to maximize the
overall performance of the amplifier to match the system requirements.
VS+ = 5V

+
EO
Case1: 200 RS ±
Case2: 2 k
VS- = -5V

RG RF

Case1: 250 Case1: 1 k

Case2: 2.5 k Case2: 10 k

Figure 9-11. Comparing Noise Contributors for Two Cases with the Amplifier in a Noninverting Gain of
5 V/V

Table 9-1. Comparing Noise Contributions for the Circuit in Figure 9-11
CASE 1 CASE 2
OUTPUT VOLTAGE NOISE VOLTAGE NOISE
NOISE NOISE NOISE
NOISE NOISE POWER CONTRIBUTIO NOISE POWER CONTRIBUTIO
SOURCE SOURCE SOURCE
EQUATION CONTRIBUTIO CONTRIBUTIO N (%) CONTRIBUTIO CONTRIBUTIO N (%)
VALUE VALUE
N (nV/√ Hz) N (nV2/Hz) N (nV/√ Hz) N (nV2/Hz)
Source resistor, ERS (1 + 1.82 nV/√ 5.76 nV/√
9.1 82.81 7.15 28.8 829.44 31.29
RS RF /RG) Hz Hz
Gain resistor, ERG (RF / 2.04 nV/√ 6.44 nV/√
8.16 66.59 5.75 25.76 663.58 25.03
RG RG) Hz Hz
Feedback 4.07 nV/√ 12.87 nV/√
ERF 4.07 16.57 1.43 12.87 165.64 6.25
resistor, RF Hz Hz
Amplifier
ENI (1 + RF / 6.3 nV/√ 6.3 nV/√
voltage noise, 31.5 992.25 85.67 31.5 992.25 37.43
RG) Hz Hz
ENI
Inverting
current noise, IBI (RF || RG) 5 fA/√ Hz 5.0E-3 — — 5 fA/√ Hz 50E-3 — —
IBI
Noninverting
IBNRS (1 +
current noise, 5 fA/√ Hz 1.0E-3 — — 5 fA/√ Hz 10E-3 — —
RF/ RG)
IBN

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9.2 Typical Applications

9.2.1 Transimpedance Amplifier
The high GBWP and low input voltage and current noise for the OPA810 make the device an ideal wideband
transimpedance amplifier for moderate to high transimpedance gains.
Sup ply Decouplin g n ot
VBIAS shown
+5 V

OPA810
+
Oscillosco pe
with 50- Inputs
-
CD CPCB
20 pF 0.3 pF -5 V
RF
100 k

CF + CPCB
1.03 pF

Figure 9-12. Wideband, High-Sensitivity, Transimpedance Amplifier

9.2.1.1 Design Requirements

Table 9-2 lists the design requirements for a high-bandwidth, high-gain transimpedance amplifier circuit.
Table 9-2. Design Requirements
PARAMETER DESIGN REQUIREMENT
Target bandwidth > 2 MHz
Transimpedance gain 100 kΩ
Photodiode capacitance 20 pF

9.2.1.2 Detailed Design Procedure

Designs that require high bandwidth from a large area detector with relatively high transimpedance gain benefit
from the low input voltage noise of the OPA810. This input voltage noise is peaked up over frequency by the
diode source capacitance, and can (in many cases) become the limiting factor to input sensitivity. The key
elements to the design are the expected diode capacitance (CD) with the reverse bias voltage (VBIAS) applied,
the desired transimpedance gain, RF, and the GBWP for the OPA810 (70 MHz). Figure 9-12 shows a
transimpedance circuit with the parameters as described in Table 9-2. With these three variables set (and
including the parasitic input capacitance for the OPA810 and the printed circuit board (PCB) added to CD), the
feedback capacitor value (CF) can be set to control the frequency response. The Transimpedance
Considerations for High-Speed Amplifiers application report discusses using high-speed amplifiers for
transimpedance applications. Set the feedback pole according to Equation 9 in order to achieve a maximally-flat
second-order Butterworth frequency response:

1 GBWP
2S RF CF 4S RF CD
(9)

The input capacitance of the amplifier is the sum of the common-mode and differential capacitance (2.0 +
0.5) pF. The parasitic capacitance from the photodiode package and the PCB is approximately 0.3 pF. Using
Equation 5 gives a total input capacitance of CD = 22.8 pF. From Equation 9, set the feedback pole at 1.55 MHz.
Setting the pole at 1.55 MHz requires a total feedback capacitance of 1.03 pF.
Equation 10 shows the approximate –3-dB bandwidth of the transimpedance amplifier circuit:

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f 3 dB GBWP / (2S RF CD ) Hz
(10)

Equation 10 estimates a closed-loop bandwidth of 2.19 MHz. Figure 9-13 and Figure 9-14 show the loop-gain
magnitude and phase plots from the TINA-TI simulations of the transimpedance amplifier circuit of Figure 9-12.
The 1/β gain curve has a zero from RF and CIN at 70 kHz and a pole from RF and CF cancelling the 1/β zero at
1.5 MHz, resulting in a 20-dB per decade rate-of-closure at the loop-gain crossover frequency (the frequency
where AOL equals 1/β), ensuring a stable circuit. A phase margin of 62° is obtained with a closed-loop bandwidth
of 3 MHz and a 100-kΩ transimpedance gain.
9.2.1.3 Application Curves

120 100
110 AOL
1/E 90
100 AOLE 80
90
80 70

Phase (Degrees)
70 60
Gain (dB)

AOL
60 1/E
50
50 AOLE
40 40
30 30
20
20
10
0 10
-10 0
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) D804
Frequency (Hz) D805

Figure 9-13. Loop-Gain Magnitude vs Frequency Figure 9-14. Loop-Gain Phase vs Frequency for the
for the Transimpedance Amplifier Circuit of Figure Transimpedance Amplifier Circuit of Figure 9-12
9-12

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9.2.2 High-Z Input Data Acquisition Front-End

An ideal data acquisition system must measure a parameter without altering the measurand. When measuring a
voltage or current from sensors with a large output impedance, an extremely high input impedance front-end with
a pA range bias current is needed. Figure 9-15 shows an example circuit with the OPA810 used at the front-end.
For systems with large input voltage attenuated with the MΩ range resistor divider, the OPA810 with its pA range
bias currents adds negligible offset voltage and distortion because of the bias current induced resistor voltage
drops. This circuit shows a funneling architecture with the OPA810 FET-input amplifier used as a unity-gain
buffer, followed by attenuation to the ADS9110 5-V, full-scale input range and the ADC input drive using the
THS4561 fully-differential amplifier (FDA). The THS4561 helps achieve better SNR and ENOB than a similar 5-V
FDA, with a higher 12.6-V supply voltage and signal swings up to the ADC full-scale input range.
As a result of the capacitive switching and current inrush on the ADC VREF input pin, a wide bandwidth amplifier
such as the OPA837 is used with the OPA378 in a composite loop as a reference buffer. The OPA378, driven
from the REF5050 5-V voltage reference, offers high precision and the OPA837 gives fast-settling performance
for the ADC reference input drive. See the Reference Design Maximizing Signal Dynamic Range for True 10 Vpp
Differential Input to 20 bit ADC design guide for more a detailed analysis of this high-Z front-end.
CF

12V

± RF

OPA810 RG 1.8V 1.8V

VIN+ + 12V RS
AVDD DVDD
R C
-12V ± C CB ADS911 0
VOCM
THS456 1 18-bit
12V 2 MSPS
+ CCB
RG
VREF
±
-0.2V
OPA810
VIN- + RF R¶
R C
-12V R¶
5V
CF
5V ±
12V
± OPA837
REF505 0 RFIL T OPA378 +
5.0 V +
Reference
CFIL T

Figure 9-15. High-Z Input Data Acquisition Front-End

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9.2.3 Multichannel Sensor Interface

High-Z input amplifiers are particularly useful when interfaced with sensors that have relatively high output
impedance. Such multichannel systems usually interface these sensors with the signal chain through a
multiplexer. Figure 9-16 shows one such implementation using an amplifier for the interface with each sensor,
and driving into an ADC through a multiplexer. An alternate circuit, shown in Figure 9-17, can use a single higher
GBWP and fast-settling amplifier at the output of the multiplexer. This architecture gives rise to large signal
transients when switching between channels, where the settling performance of the amplifier and maximum
allowed differential input voltage limits signal chain performance and amplifier reliability, respectively.

+
MUX ADC

Figure 9-16. Multichannel Sensor Interface Using Multiple Amplifiers

OPA810
-
ADC
MUX +

Figure 9-17. Multichannel Sensor Interface Using a Single Higher GBWP Amplifier

Figure 9-18 shows the output voltage and input differential voltage when a 8-V step is applied at the noninverting
terminal of the OPA810 configured as a unity-gain buffer of Figure 9-17.
7.5
Input and Output Voltage (V)

2.5

-2.5 VIN
VO
VIN,Diff
-5
Time (10 ns/div)
BD_M

Figure 9-18. Large-Signal Transient Response Using the OPA810

Because of the fast input transient, the amplifier is slew-limited and the inputs cease to track each other (a
maximum VIN,Diff of 7 V is shown in Figure 9-18) until the output reaches its final value and the negative
feedback loop is closed. For standard amplifiers with a 0.7-V to 1.5-V maximum VIN,Diff rating, current-limiting
resistors must be used in series with the input pins to protect the device from irreversible damage, which also
limits the device frequency response. The OPA810 has built-in input clamps that allow the application of as much
as 7 V of VIN,Diff, with no external resistors required and no damage to the device or a shift in performance
specifications. Such an input-stage architecture, coupled with its fast settling performance, makes the OPA810 a
good fit for multichannel sensor multiplexed systems.

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10 Power Supply Recommendations

The OPA810 is intended for operation on supplies ranging from 4.75 V to 27 V. The OPA810 can be operated on
single-sided supplies, split and balanced bipolar supplies, or unbalanced bipolar supplies. Operating from a
single supply can have numerous advantages. With the negative supply at ground, the DC errors resulting from
the –PSRR term can be minimized. Typically, AC performance improves slightly at 10-V operation with minimal
increase in supply current. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency, 0.01-
µF decoupling capacitors. A larger capacitor (2.2 µF typical) is used along with a high-frequency, 0.01-µF,
supply-decoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has
these capacitors. When a split supply is used, use these capacitors from each supply to ground. If necessary,
place the larger capacitors further from the device and share these capacitors among several devices in the
same area of the printed circuit board (PCB). An optional supply decoupling capacitor across the two power
supplies (for split-supply operation) reduces second harmonic distortion.
11 Layout
11.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the OPA810 requires careful attention
to board layout parasitics and external component types. The OPA2810EVM can be used as a reference when
designing the circuit board. Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any AC ground for all signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability—on the noninverting input, this capacitance can react with the
source impedance to cause unintentional band-limiting. To reduce unwanted capacitance, open a window
around the signal I/O pins in all ground and power planes around those pins. Otherwise, ground and power
planes must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency, 0.01-µF decoupling
capacitors. At the device pins, do not allow the ground and power plane layout to be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the
supply pins. These capacitors can be placed somewhat farther from the device and shared among several
devices in the same area of the PC board.
3. Careful selection and placement of external components preserve the high-frequency performance of
the OPA810. Resistors must be a low reactance type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film and carbon composition axially leaded resistors can also provide good high-
frequency performance. Again, keep their leads and PCB trace length as short as possible. Never use
wirewound type resistors in a high-frequency application. Because the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as
close as possible to the output pin. Other network components, such as noninverting input termination
resistors, must also be placed close to the package. Even with a low parasitic capacitance shunting the
external resistors, excessively high resistor values can create significant time constants that can degrade
performance. Good axial metal film or surface-mount resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values greater than 10 kΩ, this parasitic capacitance can add a pole or zero close to the
GBWP of 70 MHz and subsequently affects circuit operation. Keep resistor values as low as possible and
consistent with load driving considerations. Lowering the resistor values keeps the resistor noise terms low,
and minimizes the effect of parasitic capacitance, however lower resistor values increase the dynamic power
consumption because RF and RG become part of the amplifiers output load network. Transimpedance
applications (see the Section 9.2.1 section) can use whatever feedback resistor is required by the application
as long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the
inverting node.

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4. Connections to other wideband devices on the board can be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground and
power planes opened up around them. Estimate the total capacitive load and set RS for sufficient phase
margin and stability. Low parasitic capacitive loads (< 10 pF) may not need an RS because the OPA810 is
nominally compensated to operate with a 10-pF parasitic load. Higher parasitic capacitive loads without an
RS are allowed with increase in signal gain (increasing the unloaded phase margin). If a long trace is
required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement
a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design
handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary
onboard, and a higher impedance environment improves distortion. With a characteristic board trace
impedance defined based on board material and trace dimensions, a matching series resistor into the trace
from the output of the OPA810 is used as well as a terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and
the input impedance of the destination device—this total effective impedance must be set to match the trace
impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can
be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the
series resistor value to obtain sufficient phase margin and stability. This does not preserve signal integrity as
well as a doubly-terminated line. If the input impedance of the destination device is low, the signal attenuates
because of the voltage divider formed by the series output into the terminating impedance.
5. Take care to design the PCB layout for optimal thermal dissipation. For the extreme case of 125°C
operating ambient, using the approximate 134.8°C/W for the SOIC package, and an internal power of 24-V
supply × 4.7-mA 125°C supply current gives a maximum internal power dissipation of 113 mW. This power
gives a 15°C increase from ambient to junction temperature. Load power adds to this value and this
dissipation must also be calculated to determine the worst-case safe operating point.
6. Socketing a high-speed device such as the OPA810 is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network
that can almost make achieving a smooth, stable frequency response impossible. Best results are obtained
by soldering the OPA810 onto the board.
11.1.1 Thermal Considerations
The OPA810 does not require heat sinking or airflow in most applications. Maximum allowed junction
temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction
temperature to exceed 150°C.
Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the
sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL
depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when
the output is fixed at a voltage equal to half of either supply voltage (for equal split-supplies). Under this
condition PDL = VS 2 / (4 × RL) where RL includes feedback network loading.
The power in the output stage and not into the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using a DCK (SC70 package) configured as a unity gain
buffer, operating on ±12-V supplies at an ambient temperature of 25°C and driving a grounded 500-Ω load.
PD = 24 V × 4.7 mA + 122 /(4 × 500 Ω) = 184.8 mW
Maximum TJ = 25°C + (0.185 W × 190.8°C/W) = 60°C, which is well below the maximum allowed junction
temperature of 150oC.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 35

Product Folder Links: OPA810
OPA810
SBOS799D – AUGUST 2019 – REVISED JULY 2020 www.ti.com

11.2 Layout Example

VS+
Representative schematic of a
single channe l
CBYP

+ RS

CBYP
VS-

RG RF

Gro und and power plan e e xist on

inne r la yer s.

Gro und and power plan e re mo ved

Remove G ND and Power plan e from in ner layers. Gro und fill on
und er o utp ut and inverting pins to 1 8 outer layers a lso removed
minimize stray PCB capacitance
RG CBYP Place bypass capacitors
Place inpu t resistor close to pin 2 to close to power pins
2 7
minimize p arasitic ca pacita nce

RS Place output r esi stors close to

Place feedback r esistor on the output pin to minimize
bottom of PCB be tween pin s 2 and 6 3 6 para sitic capa citance

Remove G ND and Power plan e

Place bypass capacitors
und er o utp ut and inverting pins to
close to power pins 4 5
minimize stray PCB capacitance
CBYP

Figure 11-1. Layout Recommendation

36 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: OPA810

 OPA810
www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020

12 Device and Documentation Support

12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA2810 Dual-Channel, 27-V, Rail-to-Rail Input/Output FET-Input Operational Amplifier
data sheet.
• Texas Instruments, ADS9110 18-Bit, 2-MSPS, 15-mW, SAR ADC With Enhanced Performance Features data
sheet
• Texas Instruments, THS4561 Low-Power, High Supply Range, 70-MHz, Fully Differential Amplifier data sheet
• Texas Instruments, OPAx837 Low-Power, Precision, 105-MHz, Voltage-Feedback Op Amp data sheet
• Texas Instruments, OPAx378 Low-Noise, 900kHz, RRIO, Precision Operational Amplifier Zerø-Drift Series
data sheet
• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, OPA2810DGK Evaluation Module user's guide
• Texas Instruments, Single-Supply Op Amp Design Techniques application report
• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report
• Texas Instruments, Blog: What you need to know about transimpedance amplifiers – part 1
• Texas Instruments, Blog: What you need to know about transimpedance amplifiers – part 2
• Texas Instruments, Noise Analysis for High-Speed Op Amps application report
• Texas Instruments, TINA model and simulation tool
• Texas Instruments, TIDA-01057 Reference Design Maximizing Signal Dynamic Range for True 10 Vpp
Differential Input to 20 bit ADC
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 37

Product Folder Links: OPA810
OPA810
SBOS799D – AUGUST 2019 – REVISED JULY 2020 www.ti.com

12.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

38 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: OPA810

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA810IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1ZQ5

OPA810IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1ZQ5

OPA810IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1GG

OPA810IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 810

OPA810IDT ACTIVE SOIC D 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 810

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Nov-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA810IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA810IDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA810IDCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
OPA810IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA810IDT SOIC D 8 250 180.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Nov-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA810IDBVR SOT-23 DBV 5 3000 190.0 190.0 30.0
OPA810IDBVT SOT-23 DBV 5 250 190.0 190.0 30.0
OPA810IDCKR SC70 DCK 5 3000 213.0 191.0 35.0
OPA810IDR SOIC D 8 2500 853.0 449.0 35.0
OPA810IDT SOIC D 8 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/E 09/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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