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The J-K Flip Flop: Objectives

This document summarizes a lab experiment on the J-K flip flop. The objectives are to test various configurations of the J-K flip flop including asynchronous and synchronous inputs, compare edge-triggering and pulse-triggering, and analyze the circuit. The J-K flip flop is described as being more versatile than other flip flops as it can avoid invalid output states by toggling. It can be constructed using AND and NOR gates. The procedure involves building the circuit, applying input combinations, and verifying the truth table for both NAND and non-NAND versions.

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76 views

The J-K Flip Flop: Objectives

This document summarizes a lab experiment on the J-K flip flop. The objectives are to test various configurations of the J-K flip flop including asynchronous and synchronous inputs, compare edge-triggering and pulse-triggering, and analyze the circuit. The J-K flip flop is described as being more versatile than other flip flops as it can avoid invalid output states by toggling. It can be constructed using AND and NOR gates. The procedure involves building the circuit, applying input combinations, and verifying the truth table for both NAND and non-NAND versions.

Uploaded by

ALvi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital Logic Design By Muhammad Hammad

Lab 10
The J-K Flip Flop
OBJECTIVES
After completing this experiment, you will be able to:
• Test various configurations for a J-K flip-flop, including the asynchronous and
synchronous inputs.
• Compare edge-triggering with pulse-triggering.
•
COMPONENTS REQUIRED

• 7411, 3 I/P AND gate


• 7402, 2 I/P NOR gate

THEORY
The edge-triggered D flip-flop avoids the problem of the R-S invalid output states by not
allowing an invalid state. Instead of four possible input states, the D flip-flop has only two
possible input states: HIGH or LOW. However, unlike the R-S flip-flop, the D flipflop cannot be
latched unless the clock pulses are removed—a condition that limits a number of applications for
this device. A solution to these problems is the J-K flip-flop, which is basically a clocked R-S
flip-flop with additional logic to replace the R-S invalid output states with a new mode called
toggle causes the flip-flop to change to the state opposite to its present state. It is similar to the
operation of an automatic garage door opener. If the button is pressed when the door is open, the
door will close; if it is closed, it will open.

The J-K flip-flop is the most versatile of the basic flip-flops. All applications for flipflops can be
accomplished with either the D or the J-K flip-flop. The clocked R-S flipflop is seldom used; it is
used mostly as an internal component of integrated circuits. The inputs are labeled J (the set
mode) and K (the reset mode) to avoid confusion with the RS flip-flop.

The need to assure that input data do not affect the output until they are at the correct level led to
the concept of edge-triggering, investigated in the last experiment. Edge triggering is not the only
method for assuring synchronous, transitions, although it is preferred. The other method is pulse-
triggered or master-slave flip-flops. In these flipflops, the data are clocked into the master on the
leading edge of the clock and into the slave on the trailing edge of the clock. It is imperative that
the input data not change during the time the clock pulse is HIGH or the data in the master will
be changed. In principle, any flip-flop could use pulse-triggering. However, in practice D flip
flops are available only as edge triggered devices. J-K flip-flops are available as either edge-, or
pulse-triggered devices. A modification called the data-lockout flip-flop transfers data to the
master on the leading edge of the clock and into the slave on the trailing edge of the clock,
eliminating the requirement to hold the data at a constant level during the clock pulse. A certain

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Digital Logic Design By Muhammad Hammad

amount of time is required for the input of a logic gate to affect the output. This time, called the
propagation delay time, depends on the logic family.

PROCEDURE
• Construct the circuit of the figure a.
• Use LEDs as logic monitors to monitor the output by giving different combination
of inputs.
• Verify the truth table and repeat the whole process for NAND version of JK flip
flop. Check, what will happen to the output?

(a) Logic diagram

(b) Graphical symbol (c) Transition table

Clocked JK flip-flop

Review Questions
1. What is the difference between an asynchronous and a synchronous input?
2. Describe how you would set a J-K flip-flop asynchronously?
3. What is the difference between edge-triggering and pulse-triggering?

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