Microprocessor and Interfacing
Microprocessor and Interfacing
Group Members
Anupama KR
Hrishikesh Sonalikar
Noel R
Anurag Nishad
Date: 13/4/2020
[Email address]
Contents
User Requirements & Technical Specifications............................................................................................2
Assumptions & Justifications.......................................................................................................................2
Justification..............................................................................................................................................2
Assumptions............................................................................................................................................2
Components used with justification wherever required.............................................................................3
Address Map...............................................................................................................................................4
Memory Map...........................................................................................................................................4
I/O Map...................................................................................................................................................4
Design..........................................................................................................................................................5
Flow Chart...................................................................................................................................................6
Main Program..........................................................................................................................................6
Flow Chart of ISR.....................................................................................................................................7
ADC ISR....................................................................................................................................................8
Variations in Proteus Implementation with Justification.............................................................................9
Firmware...................................................................................................................................................10
List of Attachments....................................................................................................................................11
User Requirements & Technical Specifications
Design a System that senses the temperature in a room and displays them on 2, 7-segment displays.
Size of the room is as large as the BITS Auditorium only one floor
Temperature range is from 150C to 350C
Resolution required is 10C
Temperature has to be sensed every 2 minutes and the display should be updated
Assumptions
None Made.
Components used with justification wherever required
8086
8284
Temperature Sensor (Manual Attached) – 6 Nos.
ATS2000A – This covers the required temperature range with required resolution
ADC 0808 – 6 analog inputs with voltage varying from 0 – 5 V with 8-bit resolution T 20 output
can be directly connected to it (as it directly compatible) – Manual Attached
Common Anode Seven Segment Display – 2 Nos. As 2 digits are to be displayed
7447 – BCD to Common Anode 7 – Segment converter -as values will be only numeric values
8255 – Interface ADC and 7447
8254 – to generate ADC Clock and 2 Minute RTI – to read the temperature
8259 – Interrupts from EOC from ADC and Timer Interrupt every 2 Minute. Timer given higher
priority as the timer is the one that enables the ADC for conversion
2716 – 4 nos. Smallest ROM chip available is 2K and as we need to have even and odd bank and
ROM is required at reset address which is at FFFF0 H and 00000H - where there is the IVT
6116 – 2 nos. Smallest RAM chip available is 2 K and we need odd and even bank. We need RAM
for stack and temporary storage of data
LS 138 – 2 decoders
LS 373, LS 245, LS 244 and required gates
Address Map
Memory Map
ROM1 – 00000H – 00FFFH
I/O Map
8255 – 00 – 06H
8254 – 08 – 0EH
8259 – 10 – 12H
Design
Complete design shown with proper labelling (design attached)
Flow Chart
Main Program
Main
Initialize 8255,8254,8259
All sensors
read
N
Y
Find average
o
Convert to C
Display Temp
Enable INT
N
All sensors
read
Y
Find average
o
Convert to C
Display Temp
IRET
ADC ISR
ISR2
Read ADC
IRET
Variations in Proteus Implementation with Justification
1. Using 2 Min delay as 8259 does not work in proteus – EOC is used as NMI and the Timer Int
replaced by software delay as 2 Minutes
2. ROM in only 00000 – as proteus allows to change reset address.
3. Using 8253 – as 8254 not available in Proteus.
4. Clock is at 2 MHz as the clock generated for 8086 requires a long rise and fall time of clock. So
ADC clock will be only 500KHz that is also ok as 1 MHz is the max clock that can be provided.
5. 2732 is used as 2716 – not available in Proteus.
6. Using a gate-based circuit for memory – does the same as LS 138 here
7. Temperature Sensor – replaced by DC voltage source giving voltage between 0 – 5 V – as all
sensors not there in Proteus
8. 8259 not there – justification is as per point 1.
Firmware
Implemented using emu8086 attached.
List of Attachments
1. Complete Hardware Real World Design – example.pdf
2. Manuals
a. ADC 0808
b. ATS 2000A
3. Proteus File – adc.dsn
4. EMU8086 ASM File – adc.asm
5. Binary File after assembly – adc.bin