1 2 3 4 5 6 7 8

PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND1
BU3 Block Diagram
LAYER 3 : IN1
LAYER 4 : GND
PENRYN-SFF
A LAYER 5 : VCC Micro-FCBGA956/10W A

LAYER 6 : IN2 FSB P3,4

LAYER 7 : GND2
FSB(667/800/1066MHZ)
LAYER 8 : BOT

DDR SYSTEM MEMORY

FSB
PCI-E USB-3
Dual Channel DDR III INT_LVDS LCD/CCD Con. P17

Graphics Interfaces
DDRIII-SODIMM1 CANTIGA-SFF
800/1066 MHZ
DDRIII-SODIMM2
P16 NB INT_CRT
P5,6,7,8,9,10,11 CRT Con.
P17
DMI
PCI-Ex16

USB-5
DMI(x2/x4)
HDMI/USB Con.
P18
SATA 0 SATA
Main SATA - HDD
P22 DMI
B B

11.6" SATA HDD

P22 PCI-E
PCI-Express CK505 P2

PCIE-3
SATA 1 SATA
POWER SYSTEM
SATA - ODD USB-6 3G USB-7
Sim Con. P24
P22
ISL88731
Intel I/O Controller Hub 9 P20 P20 ISL6237 P25
USB 2.0 (Port0~9) (ICH9M-SFF) RT8152B P26
USB-2
Bluetooth Con. USB TPS51116REGR P27
P21
SB UP6111AQDD P28
P12, 13, 14, 15 RT9205 P29
USB-9 ISL6263A P30
USB SW PCIE-6
P18 WiFi or WiMAX
USB-10
P20

VCC_CORE
C PCIE-5 C
Atheros RTC
10/100 Lan +1.8V
P23 Azalia BATTERY
IHDA
LPC P12
+1.05V

LPC
+1.5VSUS
+1.5V
LAN CON.&Audio&Card Reader&USB*2/B EC
P26 +3VPCU
P22 +3V_S5
+3VSUS
+3V
Audio Codec FAN TP/LED/Hall Sensor Con. Power /B +5VPCU
Con. +5V
P3 P19 P21 P21 +SMDDR_VTERM
Port-B

Port-A

+SMDDR_VREF
USB*2 Con.

D D
LAN Con.

USB-0
Card Reader USB-4 K/B Con. SPI Flash G-Sensor Kill SW
USB-1 MIC JACK HP/SPDIF SPK Con.
P21 P22 P19 P21

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
Block Diagram
Date: Monday, August 10, 2009 Sheet 1 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+3V
0.25A +3V_VDD_CK_VDD
(20mils)
CLOCK GEN L24 PBY160808T-301Y-N_6

C353

0.1u/10V_4
+3V

R140 2.2K_4 H_STP_PCI#

C270 C371 R139 2.2K_4 H_STP_CPU#

A 0.1u/10V_4 0.1u/10V_4 A

F3B
C372 C263 U18

0.1u/10V_4 10u/6.3V_8
9 61 CLK_CPU_BCLK_R RP17 4 3 *short_4P2R
VDD_PCI CPU-0 CLK_CPU_BCLK [3]
4 60 CLK_CPU_BCLK#_R 2 1 To CPU BCLK
VDD_REF CPU-0# CLK_CPU_BCLK# [3]
23
VDD_PLL3 CLK_MCH_BCLK_R RP15
16 58 4 3 *short_4P2R CLK_MCH_BCLK [5]
VDD_48 CPU-1 CLK_MCH_BCLK#_R
46
VDD_SRC CPU-1#
57 2 1 CLK_MCH_BCLK# [5] To NB HPLL_CLK
62
C368
19
VDD_CPU

VDD_IO1
CK505 SRC-0/DOT96
SRC-0#/DOT96#
20
21
DOT96_SSC_R
DOT96_SSC#_R
RP16 2
4
1 *short_4P2R
3
MCH_DREFCLK [6]
MCH_DREFCLK# [6] To NB DPLL_REF_CLK
0.1u/10V_4 27
+1.05V 33
VDD_IO2 QFN64 24 DREF_SSCLK_R RP14 2 1 *short_4P2R

L19 PBY160808T-301Y-N_6
0.25A (20mils)
+1.05V_CK_VDD_IO
43
VDD_IO3
VDD_IO4
SRC-1/SE1
SRC-1#/SE2
25 DREF_SSCLK#_R 4 3
DREF_SSCLK [6]
DREF_SSCLK# [6] To NB DPLL_REF_SSCLK
52
VDD_IO5 CLK_PCIE_SATA_R RP13
56 28 2 1 *short_4P2R CLK_PCIE_SATA [12]
C258 C357 C364 C352 C358 C355 C367 VDD_IO6 SRC-2/SATA CLK_PCIE_SATA#_R
SRC-2#/SATA#
29 4 3 CLK_PCIE_SATA# [12] To ICH9 SATA_CLK
15
10u/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 GND6 CLK_PCIE_ICH_R RP12
18 31 2 1 *short_4P2R CLK_PCIE_ICH [13]
GND7 CR#_C/SRC-3 CLK_PCIE_ICH#_R
22
GND8 CR#_D/SRC-3#
32 4 3 CLK_PCIE_ICH# [13] To ICH9 DMI_CLK
26
GND9 CLK_PCIE_MINI1_R RP11
30 34 2 1 *short_4P2R
36
GND10
GND11
SRC-4
SRC-4#
35 CLK_PCIE_MINI1#_R 4 3
CLK_PCIE_MINI1 [20]
CLK_PCIE_MINI1# [20] To Mini Card 1 B1A
49
GND12 H_STP_PCI#
59 45 H_STP_PCI# [14]
GND13 PCI_STOP#/SRC-5 H_STP_CPU#
1
GND14 CPU_STOP#/SRC5-5#
44 H_STP_CPU# [14] From SB CLK
R189 33_4 PCLK0 8 48 CLK_PCIE_3G_R RP21 4 3 *3G@0X2
B [20] PCLK_DEBUG
T88 PCLK1 10
CR#_A/PCI-0
CR_B/PCI-1
SRC-6
SRC-6#
47 CLK_PCIE_3G#_R 2 1
CLK_PCIE_3G [20]
CLK_PCIE_3G# [20] To 3G Card B1A B

PCLK2 11
PCLK3 TME/PCI-2 CLK_CR#_F
12 51
[22] PCLK_591
PCLK_591 R338 33_4 PCLK_591_R 13
SRC5_EN/PCI-3
27M_SEL/PCI-4
CR#_F/SRC-7
CR#_E/SRC-7#
50 CLK_CR#_E
T78
T77
D3A
CLK_PCI_ICH R339 33_4 CLK_PCI_ICH_R 14
[13] CLK_PCI_ICH ITP_EN/PCIF-5#
54 CLK_SRC8
SRC-8/CPU_ITP
SRC-8#/CPU_ITP#
53 CLK_SRC8#
T85
T81
F3B
CLK_ICH_48M R333 33_4
[14] CLK_ICH_48M
CPU_MCH_BSEL0 R327 2.2K_4 FSA_R 17 37 CLK_PCIE_LAN_R RP10 2 1 *short_4P2R
EMI RESERVE [3]
[3]
[3]
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
CPU_MCH_BSEL1
CPU_MCH_BSEL2 R341 10K_4 FSC_R
64
5
FSA/USB48
FSB/TEST_MODE
FSC/TEST_SEL/REF
SRC-9
SRC-9#
38 CLK_PCIE_LAN#_R 4 3
CLK_PCIE_LAN [23]
CLK_PCIE_LAN# [23] To PCIE LAN
CLK_ICH_14M R340 33_4 41 MCH_3GPLL_R RP9 2 1 *short_4P2R
[14] CLK_ICH_14M SRC-10 CLK_MCH_3GPLL [6]
55 42 MCH_3GPLL#_R 4 3 To NB PEG_CLK
RESET# SRC-10# CLK_MCH_3GPLL# [6]
PCLK_591 C276 *33p/50V_4
40 CLK_3GPLLREQ#_R R300 475/F_4 From NB CLKREQ#
CR#_H/SRC-11 CLK_3GPLLREQ# [6]
CGDAT_SMB 6 39 CLK_CR#_G T76
CLK_PCI_ICH C275 *33p/50V_4 CGCLK_SMB SDATA CR#_G/SRC-11#
7
D3A SCLK
CK_PWRGD/PD#
63 CLK_PWRGD [14] To ICH9 CK_PWRGD
C373 33p/50V_4 CG_XOUT 2
CLK_ICH_48M C370 *33p/50V_4 CG_XIN XOUT
3 65
1
XIN GND1

74
73
72
71
70
69
68
67
66
Y5
CLK_ICH_14M C277 *33p/50V_4 14.318MHZ ICS9LPRS365BKLFT INS109622231

74
73
72
71
70
69
68
67
66
2

C374 33p/50V_4

C C

BSEL Frequency Select Table Clock Gen Strap Clock Gen I2C
+3V

FSC FSB FSA CPU SRC PCI

SLG8SP513 PULL HIGH PULL DOWN
1 0 1 100 100 33 R349
0 0 1 133 100 33

2
PIN11 PCI2/TME NO OVERCLOCKING (default) NORMAL RUN 10K_4
0 1 1 166 100 33 PIN44/45 IS CGDAT_SMB
3 1 CGDAT_SMB [16,20]
PIN12 PCI-3 PIN44/45 IS SRC5 PCI_STOP/CPU_STOP (default) [14,23] SDATA
0 1 0 200 100 33 Q29 ME2N7002E
PIN 21/20
0 0 0 266 100 33 PIN13 PCI-4/27M_SEL PIN 24/25 IS 27MHz IS SRC/DOT (default)
1 0 0 333 100 33 +3V
PIN14 PCIF-5/ITP_EN PIN 53/54 IS CPUITP PIN 53/54 IS SRC (default)
1 1 0 400 100 33 SMbus address D2
1 1 1 RSVD 100 33
R344

2
10K_4

3 1 CGCLK_SMB
[14,23] SCLK CGCLK_SMB [16,20]
+1.05V R328 *1K_4 CPU_MCH_BSEL0 R331 1K_4
MCH_BSEL0 [6]
Q30 ME2N7002E
R334 *1K_4
D D
+3V R187 10K_4 PCLK2 R188 *10K_4

+1.05V R330 *1K_4 CPU_MCH_BSEL1 R329 1K_4 PCLK3 R337 10K_4

MCH_BSEL1 [6]
R326 *1K_4
+3V R185 *10K_4 PCLK_591_R R184 10K_4
PROJECT : BU3
R355 *1K_4 CPU_MCH_BSEL2 R348 1K_4
MCH_BSEL2 [6] +3V R182 *10K_4 CLK_PCI_ICH_R R183 10K_4 Quanta Computer Inc.
Size Document Number Rev
Custom D3B
NB7
CLOCK GEN_9LPRS365BKLFT
Date: Monday, August 10, 2009 Sheet 2 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

CPU [5] H_A#[3..16]

H_A#[3..16]
H_A#3
H_A#4
H_A#5
H_A#6
P2
V4
W1
T4
U14A
A[3]#
A[4]#
A[5]#
A[6]#
ADS#
BNR#
BPRI#
M4
J5
L5
H_ADS# [5]
H_BNR# [5]
H_BPRI# [5] [5] H_D#[0..15]
H_D#[0..15]
H_D#0 F40
U14B
D[0]# D[32]#
AP44 H_D#32
H_D#[32..47]
H_D#[32..47] [5]

ADDR GROUP 0
H_A#7 AA1 N5 H_D#1 G43 AR43 H_D#33
H_A#8 A[7]# DEFER# H_DEFER# [5] H_D#2 D[1]# D[33]# H_D#34
AB4 F38 H_DRDY# [5] E43 AH40
H_A#9 A[8]# DRDY# H_D#3 D[2]# D[34]# H_D#35
T2
A[9]# DBSY#
J1 H_DBSY# [5] Layout Note: J43
D[3]# D[35]#
AF40

DATA GROUP 0
H_A#10 AC5 H_D#4 H40 AJ43 H_D#36
A[10]# Place Resistor close to CPU. D[4]# D[36]#

CONTROL
H_A#11 AD2 M2 H_D#5 H44 AG41 H_D#37
A[11]# BR0# H_BR0# [5] D[5]# D[37]#

DATA GROUP 2
H_A#12 AD4 H_D#6 G39 AF44 H_D#38
H_A#13 A[12]# H_IERR# R274 56_4 H_D#7 D[6]# D[38]# H_D#39
AA5 B40 +1.05V E41 AH44
H_A#14 A[13]# IERR# H_D#8 D[7]# D[39]# H_D#40
AE5 D8 H_INIT# [12] L41 AM44
H_A#15 A[14]# INIT# H_D#9 D[8]# D[40]# H_D#41
AB2 K44 AN43
H_A#16 A[15]# H_D#10 D[9]# D[41]# H_D#42
AC1 N1 H_LOCK# [5] N41 AM40
A[16]# LOCK# H_D#11 D[10]# D[42]# H_D#43
A
[5] H_ADSTB#0 Y4 T40 AK40 A
H_REQ#[0..4] ADSTB[0]# H_RESET# H_D#12 D[11]# D[43]# H_D#44
[5] H_REQ#[0..4] G5 H_RESET# [5] M40 AG43
H_REQ#0 RESET# H_D#13 D[12]# D[44]# H_D#45
R1 K2 H_RS#0 [5] G41 AP40
H_REQ#1 REQ[0]# RS[0]# H_D#14 D[13]# D[45]# H_D#46
R5 H4 H_RS#1 [5] M44 AN41
H_REQ#2 REQ[1]# RS[1]# H_D#15 D[14]# D[46]# H_D#47
U1 K4 H_RS#2 [5] L43 AL41
H_REQ#3 REQ[2]# RS[2]# D[15]# D[47]#
P4 L1 H_TRDY# [5] [5] H_DSTBN#0 K40 AK44 H_DSTBN#2 [5]
H_REQ#4 REQ[3]# TRDY# DSTBN[0]# DSTBN[2]#
W5 [5] H_DSTBP#0 J41 AL43 H_DSTBP#2 [5]
H_A#[17..35] REQ[4]# DSTBP[0]# DSTBP[2]#
[5] H_A#[17..35] H2 H_HIT# [5] [5] H_DINV#0 P40 AJ41 H_DINV#2 [5]
H_A#17 HIT# DINV[0]# DINV[2]#
AN1 F2 H_HITM# [5]
H_A#18 A[17]# HITM# H_D#[16..31] H_D#[48..63]
AK4 [5] H_D#[16..31] H_D#[48..63] [5]
H_A#19 A[18]# ITP_BPM#0 H_D#16 H_D#48
AG1 AY8 T1 P44 AV38
A[19]# BPM[0]# D[16]# D[48]#

ADDR GROUP 1
H_A#20 AT4 BA7 ITP_BPM#1 H_D#17 V40 AT44 H_D#49
A[20]# BPM[1]# T2 D[17]# D[49]#
H_A#21 AK2 BA5 ITP_BPM#2 H_D#18 V44 AV40 H_D#50
A[21]# BPM[2]# T5 D[18]# D[50]#
H_A#22 AT2 AY2 ITP_BPM#3 H_D#19 AB44 AU41 H_D#51
A[22]# BPM[3]# T8 D[19]# D[51]#

XDP/ITP SIGNALS
H_A#23 AH2 AV10 ITP_BPM#4 H_D#20 R41 AW41 H_D#52
A[23]# PRDY# T7 D[20]# D[52]#

DATA GROUP 1
H_A#24 AF4 AV2 ITP_BPM#5 H_D#21 W41 AR41 H_D#53
A[24]# PREQ# T6 D[21]# D[53]#

DATA GROUP 3
H_A#25 AJ5 AV4 ITP_TCK H_D#22 N43 BA37 H_D#54
H_A#26 A[25]# TCK ITP_TDI H_D#23 D[22]# D[54]# H_D#55
AH4 AW7 U41 BB38
H_A#27 A[26]# TDI ITP_TDO H_D#24 D[23]# D[55]# H_D#56
AM4 AU1 AA41 AY36
H_A#28 A[27]# TDO ITP_TMS H_D#25 D[24]# D[56]# H_D#57
AP4 AW5 AB40 AT40
H_A#29 A[28]# TMS ITP_TRST# H_D#26 D[25]# D[57]# H_D#58
AR5 AV8 AD40 BC35
H_A#30 A[29]# TRST# ITP_DBRESET# +1.05V H_D#27 D[26]# D[58]# H_D#59
AJ1 J7 ITP_DBRESET# [14] AC41 BC39
H_A#31 A[30]# DBR# H_D#28 D[27]# D[59]# H_D#60
AL1 AA43 BA41
H_A#32 A[31]# H_D#29 D[28]# D[60]# H_D#61
AM2 Y40 BB40
H_A#33 A[32]# H_D#30 D[29]# D[61]# H_D#62
AU5
A[33]# THERMAL Y44
D[30]# D[62]#
BA35
H_A#34 AP2 R265 H_D#31 T44 AU43 H_D#63
H_A#35 A[34]# H_PROCHOT#_D D[31]# D[63]#
AR1 D38 [5] H_DSTBN#1 U43 AY40 H_DSTBN#3 [5]
A[35]# PROCHOT# H_THERMDA 1K/F_4 DSTBN[1]# DSTBN[3]#
[5] H_ADSTB#1 AN5 BB34 [5] H_DSTBP#1 W43 AY38 H_DSTBP#3 [5]
ADSTB[1]# THERMDA H_THERMDC DSTBP[1]# DSTBP[3]#
BD34 [5] H_DINV#1 R43 BC37 H_DINV#3 [5]
THERMDC DINV[1]# DINV[3]#
[12] H_A20M# C7
A20M# H_PM_THRMTRIP# V_CPU_GTLREF AW43 COMP0 R269 27.4/F_6
[12] H_FERR# D4
FERR# THERMTRIP#
B10
GTLREF COMP[0]
AE43 Layout note:

ICH
F10 R276 *1K_4 CPU_TEST1 E37 MISC AD44 COMP1 R272 54.9/F_4
[12] H_IGNNE# IGNNE# R273 *1K_4 CPU_TEST2 D40
TEST1 COMP[1]
AE1 COMP2 R270 27.4/F_6 comp0,2: Zo=27.4ohm, L<0.5"
TEST2 COMP[2]
[12] H_STPCLK# F8
STPCLK#
R267
T73
CPU_TEST3 C43
TEST3 COMP[3]
AF2 COMP3 R268 54.9/F_4 comp1,3: Zo=55ohm, L<0.5"
C9 H CLK C336 *0.1u/10V_4 CPU_TEST4 AE41
[12] H_INTR LINT0 CPU_TEST5 TEST4
C5 A35 2K/F_4 AY10 G7
[12] H_NMI LINT1 BCLK[0] CLK_CPU_BCLK [2] T4 CPU_TEST6 TEST5 DPRSTP# H_DPRSTP# [6,12,26]
[12] H_SMI# E5 C35 CLK_CPU_BCLK# [2] T72 AC43 B8 H_DPSLP# [12]
SMI# BCLK[1] TEST6 DPSLP#
C41 H_DPWR# [5]
DPWR#
V2 [2] CPU_MCH_BSEL0 A37 E7 H_PWRGOOD [12]
RSVD01 BSEL[0] PWRGOOD
Y2 [2] CPU_MCH_BSEL1 C37 D10 H_CPUSLP# [5]
RSVD02 BSEL[1] SLP# H_PSI#
AG5 [2] CPU_MCH_BSEL2 B38 BD10 T3
B RSVD03 BSEL[2] PSI# B

RESERVED
AL5
RSVD04 Penryn_SFF_1p0
J9
RSVD05 Layout Note:
F4
H8
RSVD06 Place voltage divider
RSVD07
within 0.5" of GTLREF pin

Penryn_SFF_1p0

Thermal Trip CPU Thermal Monitor

+3V +3V +3V F3B 30mA(20mils)
+1.05V +1.05V
R12 *short_6 LM86VCC C34 0.1u/10V_4

2
Q7
C27 *100p/50V_4
3

[22] 2ND_MBCLK 3 1
R13 R15 R18
ME2N7002E
2 R34 D4 10K_4 10K_4 10K_4
[6,14,26] DELAY_VR_PWRGOOD
+3V
ME2N7002E *10K_4 *BAS316 U2
Q15 H_THERMDA

2
Q8 SMB_MBCLK 8 1
1

SCLK VCC
+1.05V 3 1 SMB_MBDATA 7 2 C44
[22] 2ND_MBDATA SDA DXP
R33 R35 ME2N7002E THERM_ALERT#_T 6 3 2200p/50V_6
C
ALERT# DXN C
R29 1K_4 100K_4 D3 *BAS316 4 5 H_THERMDC
[14] THERM_ALERT# OVERT# GND
56.2/F_4 Q14
2

+3V R19 10K_4 LM95245CIMM NOPB

MMBT3904-7-F Voltage Level shift
H_PM_THRMTRIP# Q11
1 3 SYS_SHDN# [25] MMBT3904-7-F
MSOP8 LM95245 : AL095245000
SYS_SHDN# 3 1THER_SHDN#
No use Thermal trip CPU side still PU 56ohm.
R27 *0_4
PM_THRMTRIP# [6,12] Use Thermal trip can share PU at SB side C69
ADDRESS: 98H

2
*1u/16V_6

+3V R24 330_4

Processor Hot CPU FAN CTRL XDP +1.05V

+1.05V R262 51/F_4 ITP_TDI

+1.05V +3V R266 *51/F_4 ITP_TDO

+5V R264 51/F_4 ITP_TMS

R31 R254
R4 51/F_4 ITP_BPM#5
*1K_4 10K_4
R278 +3V C1
[22] FANSIG ITP_TCK
R263 51/F_4
68_4 Q13 2.2u/6.3V_6 C329
2

D D
R257 51/F_4 ITP_TRST#
*MMBT3904-7-F 3mA(25mils) 40mils *0.01u/16V_4
CN15
H_PROCHOT#_D 1 3 R277 *2.2k_4 H_PROCHOT#_EC [22]
U1
2

2 3 TH_FAN_POWER
VIN VO 1 H_RESET# R25 *51/F_4
5 +1.05V
THERM_ALERT#_T CPUFANON# GND 2
1 3 1 6
R32 *0_4 Q1 ME2N7002E /FON GND C330 C331 3
[26] H_PROCHOT# 7
GND
[22] VFAN 4 8
VSET GND 10u/6.3V_8 0.01u/25V_4
G995P1U 85205-0300L

No use PROCHOT CPU side still PU 56ohm. FANPWR = 1.6*VSET Layout Note:
PROJECT : BU3
Use PROCHOT to optional receiver CPU side PU Place Resistor close to CPU Quanta Computer Inc.
68ohm and through isolat 2.2K ohm to receiver side with Stub length <200mils.
Size Document Number Rev
Custom Penryn (HOST BUS) D3B
NB7
Date: Monday, August 10, 2009 Sheet 3 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

CPU +VCC_CORE

F32
G33
H32
U14C
VCC[001]
VCC[002]
VCC[068]
VCC[069]
AB28
AD30
AD28
+VCC_CORE
18A (VCC PLANE)
+VCC_CORE

BD28
BB26
BD26
U14F

VCC_101
VCC_102
VCCP_021
VCCP_022
AL37
AN37
AP38
+1.05V

G25
G23
G21
J25
U14E

VSS_164
VSS_165
VSS_166
VSS_280
VSS_281
VSS_282
AA15
AC15
Y10
AD10
B42
F44
D44
D42
U14D
VSS[001]
VSS[002]
VSS[003]
VSS[082]
VSS[083]
VSS[084]
AM36
AR35
AU35
AV34
VCC[003] VCC[070] VCC_103 VCCP_023 VSS_167 VSS_283 VSS[004] VSS[085]
J33 Y26 B22 B32 J23 AH12 F42 AW35
VCC[004] VCC[071] VCC_104 VCCP_024 VSS_168 VSS_284 VSS[005] VSS[086]
K32 AB26 B24 C33 J21 AE15 H42 AW33
VCC[005] VCC[072] VCC_105 VCCP_025 VSS_169 VSS_285 VSS[006] VSS[087]
L33 AD26 D22 D32 L25 AG15 K42 AY34
VCC[006] VCC[073] VCC_106 VCCP_026 VSS_170 VSS_286 VSS[007] VSS[088]
M32 AF30 D24 E35 L23 AJ15 M42 AT36
VCC[007] VCC[074] VCC_107 VCCP_027 VSS_171 VSS_287 VSS[008] VSS[089]
N33 AF28 F24 E33 L21 AH10 P42 AV36
VCC[008] VCC[075] VCC_108 VCCP_028 VSS_172 VSS_288 VSS[009] VSS[090]
P32 AH30 F22 F34 N25 AM12 T42 BA33
VCC[009] VCC[076] VCC_109 VCCP_029 VSS_173 VSS_289 VSS[010] VSS[091]
R33 AH28 H24 G35 N23 AL15 V42 BC33
VCC[010] VCC[077] VCC_110 VCCP_030 VSS_174 VSS_290 VSS[011] VSS[092]
T32 AF26 H22 F36 N21 AN15 Y42 BB36
A VCC[011] VCC[078] VCC_111 VCCP_031 VSS_175 VSS_291 VSS[012] VSS[093] A
U33 AH26 K24 H36 R25 AR15 AB42 BD36
VCC[012] VCC[079] VCC_112 VCCP_032 VSS_176 VSS_292 VSS[013] VSS[094]
V32 AK30 K22 J35 R23 AM10 AD42 C27
VCC[013] VCC[080] VCC_113 VCCP_033 VSS_177 VSS_293 VSS[014] VSS[095]
W33 AK28 M24 L35 R21 AT12 AF42 C29
VCC[014] VCC[081] VCC_114 VCCP_034 VSS_178 VSS_294 VSS[015] VSS[096]
Y32 AM30 M22 N35 U25 AV12 AH42 C31
VCC[015] VCC[082] VCC_115 VCCP_035 VSS_179 VSS_295 VSS[016] VSS[097]
AA33 AM28 P24 K36 U23 AW13 AK42 E29
VCC[016] VCC[083] VCC_116 VCCP_036 VSS_180 VSS_296 VSS[017] VSS[098]
AB32 AP30 P22 R35 U21 AW11 AM42 E27
VCC[017] VCC[084] VCC_117 VCCP_037 VSS_181 VSS_297 VSS[018] VSS[099]
AC33 AP28 T24 U35 W25 AY12 AP42 G29
VCC[018] VCC[085] VCC_118 VCCP_038 VSS_182 VSS_298 VSS[019] VSS[100]
AD32 AK26 T22 P36 W23 AU15 AY44 G27
VCC[019] VCC[086] VCC_119 VCCP_039 VSS_183 VSS_299 VSS[020] VSS[101]
AE33 AM26 V24 V36 W21 AW15 AV44 E31
VCC[020] VCC[087] VCC_120 VCCP_040 VSS_184 VSS_300 VSS[021] VSS[102]
AF32 AP26 V22 W35 AA25 AT10 AT42 G31
VCC[021] VCC[088] VCC_121 VCCP_041 VSS_185 VSS_301 VSS[022] VSS[103]
AG33 AT30 Y24 AA35 AA23 BA13 AV42 J29
VCC[022] VCC[089] VCC_122 VCCP_042 VSS_186 VSS_302 VSS[023] VSS[104]
AH32 AT28 Y22 AC35 AA21 BA11 AY42 J27
VCC[023] VCC[090] VCC_123 VCCP_043 VSS_187 VSS_303 VSS[024] VSS[105]
AJ33 AV30 AB24 AB36 AC25 BB12 BA43 L29
VCC[024] VCC[091] VCC_124 VCCP_044 VSS_188 VSS_304 VSS[025] VSS[106]
AK32 AV28 AB22 AE35 AC23 BC11 BB42 L27
VCC[025] VCC[092] VCC_125 VCCP_045 VSS_189 VSS_305 VSS[026] VSS[107]
AL33 AY30 AD24 AG35 AC21 BA15 C39 N29
VCC[026] VCC[093] VCC_126 VCCP_046 VSS_190 VSS_306 VSS[027] VSS[108]
AM32 AY28 AD22 AJ35 AE25 BC15 E39 N27
VCC[027] VCC[094] VCC_127 VCCP_047 VSS_191 VSS_307 VSS[028] VSS[109]
AN33 AT26 AF24 AF36 AE23 B6 G37 J31
VCC[028] VCC[095] VCC_128 VCCP_048 VSS_192 VSS_308 VSS[029] VSS[110]
AP32 AV26 AF22 AL35 AE21 D6 H38 L31
VCC[029] VCC[096] VCC_129 VCCP_049 VSS_193 VSS_309 VSS[030] VSS[111]
AR33 AY26 AH24 AN35 AG25 E9 J39 N31
VCC[030] VCC[097] VCC_130 VCCP_050 VSS_194 VSS_310 VSS[031] VSS[112]
AT34 BB30 AH22 AK36 AG23 F6 L39 R29
VCC[031] VCC[098] VCC_131 VCCP_051 VSS_195 VSS_311 VSS[032] VSS[113]
AT32 BB28 AK24 AP36 AG21 G9 M38 R27
VCC[032] VCC[099] +1.05V VCC_132 VCCP_052 VSS_196 VSS_312 VSS[033] VSS[114]
AU33 BD30 AK22 B12 AJ25 H6 N39 U29
VCC[033] VCC[100] VCC_133 VCCP_053 VSS_197 VSS_313 VSS[034] VSS[115]
AV32
AY32
VCC[034]
J11
4.5A (VCC PLANE) AM24
AM22
VCC_134 VCCP_054
B14
C13
AJ23
AJ21
VSS_198 VSS_314
K8
K6
R39
T38
VSS[035] VSS[116]
U27
R31
VCC[035] VCCP_001 VCC_135 VCCP_055 VSS_199 VSS_315 VSS[036] VSS[117]
BB32 E11 AP24 D12 AL25 M8 U39 U31
VCC[036] VCCP_002 VCC_136 VCCP_056 VSS_200 VSS_316 VSS[037] VSS[118]
BD32 G11 AP22 D14 AL23 M6 W39 W29
F3B

1
VCC[037] VCCP_003 VCC_137 VCCP_057 VSS_201 VSS_317 VSS[038] VSS[119]
B28 J37 AT24 E13 AL21 P8 Y38 W27
VCC[038] VCCP_004 + C342 VCC_138 VCCP_058 VSS_202 VSS_318 VSS[039] VSS[120]
B30 K38 AT22 F14 AN25 P6 AA39 W31
VCC[039] VCCP_005 VCC_139 VCCP_059 VSS_203 VSS_319 VSS[040] VSS[121]
B26 L37 AV24 F12 AN23 T8 AC39 AA29
VCC[040] VCCP_006 *220u/2.5V_3528 VCC_140 VCCP_060 VSS_204 VSS_320 VSS[041] VSS[122]
D28 N37 AV22 G13 AN21 T6 AD38 AA27

2
VCC[041] VCCP_007 VCC_141 VCCP_061 VSS_205 VSS_321 VSS[042] VSS[123]
D30 P38 AY24 H14 AR25 V8 AE39 AC29
VCC[042] VCCP_008 VCC_142 VCCP_062 VSS_206 VSS_322 VSS[043] VSS[124]
F30 R37 AY22 H12 AR23 V6 AG39 AC27
VCC[043] VCCP_009 VCC_143 VCCP_063 VSS_207 VSS_323 VSS[044] VSS[125]
F28 U37 BB24 J13 AR21 U5 AH38 AA31
VCC[044] VCCP_010 VCC_144 VCCP_064 VSS_208 VSS_324 VSS[045] VSS[126]
H30 V38 BB22 K14 AU25 Y8 AJ39 AC31
VCC[045] VCCP_011 VCC_145 VCCP_065 VSS_209 VSS_325 VSS[046] VSS[127]
H28 W37 BD24 K12 AU23 Y6 AL39 AE29
VCC[046] VCCP_012 VCC_146 VCCP_066 VSS_210 VSS_326 VSS[047] VSS[128]
D26 AA37 BD22 L13 AU21 AB8 AM38 AE27
VCC[047] VCCP_013 +1.5V VCC_147 VCCP_067 VSS_211 VSS_327 VSS[048] VSS[129]
F26 AB38 B16 L11 AW25 AB6 AN39 AG29
VCC[048] VCCP_014 VCC_148 VCCP_068 VSS_212 VSS_328 VSS[049] VSS[130]
B H26 AC37 B18 M14 AW23 AD8 AR39 AG27 B
K30
VCC[049]
VCC[050]
VCCP_015
VCCP_016
AE37 0.13A (20mils) F3B B20
VCC_149
VCC_150
VCCP_069
VCCP_070
N13 AW21
VSS_213
VSS_214
VSS_329
VSS_330
AD6 AR37
VSS[050]
VSS[051]
VSS[131]
VSS[132]
AJ29
K28 D16 N11 BA25 AF8 AT38 AJ27
VCC[051] +VCCA_PROC R279 *short_6 VCC_151 VCCP_071 VSS_215 VSS_331 VSS[052] VSS[133]
M30 B34 D18 K10 BA23 AF6 AU39 AE31
VCC[052] VCCA[01] VCC_152 VCCP_072 VSS_216 VSS_332 VSS[053] VSS[134]
M28 D34 F18 P14 BA21 AH8 AU37 AG31
VCC[053] VCCA[02] VCC_153 VCCP_073 VSS_217 VSS_333 VSS[054] VSS[135]
K26 F16 P12 BC25 AH6 AW39 AJ31
VCC[054] +VCC_CORE C343 C344 VCC_154 VCCP_074 VSS_218 VSS_334 VSS[055] VSS[136]
M26 BD8 H_VID0 [26] H18 R13 BC23 AK8 AW37 AL29
VCC[055] VID[0] VCC_155 VCCP_075 VSS_219 VSS_335 VSS[056] VSS[137]
P30 BC7 H_VID1 [26] H16 R11 BC21 AK6 BA39 AL27
VCC[056] VID[1] 0.01u/25V_4 10u/6.3V_8 VCC_156 VCCP_076 VSS_220 VSS_336 VSS[057] VSS[138]
P28 BB10 H_VID2 [26] D20 T14 C17 AM8 BC41 AN29
VCC[057] VID[2] R256 VCC_157 VCCP_077 VSS_221 VSS_337 VSS[058] VSS[139]
T30 BB8 H_VID3 [26] F20 U13 C19 AM6 BD40 AN27
VCC[058] VID[3] VCC_158 VCCP_078 VSS_222 VSS_338 VSS[059] VSS[140]
T28 BC5 H_VID4 [26] H20 U11 E19 AP8 BD38 AL31
VCC[059] VID[4] 100/F_4 VCC_159 VCCP_079 VSS_223 VSS_339 VSS[060] VSS[141]
V30 BB4 H_VID5 [26] K18 V14 E17 AP6 B36 AN31
VCC[060] VID[5] VCC_160 VCCP_080 VSS_224 VSS_340 VSS[061] VSS[142]
V28 AY4 H_VID6 [26] K16 V12 G19 AT8 H34 AR29
VCC[061] VID[6] VCC_161 VCCP_081 VSS_225 VSS_341 VSS[062] VSS[143]
P26 M18 W13 G17 AT6 D36 AR27
VCC[062] VCC_162 VCCP_082 VSS_226 VSS_342 VSS[063] VSS[144]
T26 M16 W11 J19 AU9 K34 AR31
VCC[063] VCC_163 VCCP_083 VSS_227 VSS_343 VSS[064] VSS[145]
V26 BD12 VCCSENSE [26] K20 P10 J17 AV6 M34 AU29
VCC[064] VCCSENSE VCC_164 VCCP_084 VSS_228 VSS_344 VSS[065] VSS[146]
Y30 M20 V10 L19 AU7 M36 AU27
VCC[065] VCC_165 VCCP_085 VSS_229 VSS_345 VSS[066] VSS[147]
Y28 P18 Y14 L17 AW9 P34 AW29
VCC[066] VCC_166 VCCP_086 VSS_230 VSS_346 VSS[067] VSS[148]
AB30 BC13 VSSSENSE [26] P16 AA13 N19 AY6 T34 AW27
VCC[067] VSSSENSE VCC_167 VCCP_087 VSS_231 VSS_347 VSS[068] VSS[149]
T18 AA11 N17 BA9 V34 AU31
Penryn_SFF_1p0 R255 VCC_168 VCCP_088 VSS_232 VSS_348 VSS[069] VSS[150]
T16 AB14 R19 BB6 T36 AW31
VCC_169 VCCP_089 VSS_233 VSS_349 VSS[070] VSS[151]
V18 AB12 R17 BC9 Y34 BA29
100/F_4 VCC_170 VCCP_090 VSS_234 VSS_350 VSS[071] VSS[152]
V16 AC13 U19 BD6 AB34 BA27
VCC_171 VCCP_091 VSS_235 VSS_351 VSS[072] VSS[153]
P20 AC11 U17 B4 AD34 BC29
VCC_172 VCCP_092 VSS_236 VSS_352 VSS[073] VSS[154]
T20 AD14 W19 C3 Y36 BC27
VCC_173 VCCP_093 VSS_237 VSS_353 VSS[074] VSS[155]
V20 AB10 W17 E3 AD36 BA31
VCC_174 VCCP_094 VSS_238 VSS_354 VSS[075] VSS[156]
Y18 AE13 AA19 G3 AF34 BC31
VCC_175 VCCP_095 VSS_239 VSS_355 VSS[076] VSS[157]
Y16 AE11 AA17 J3 AH34 C21
VCC_176 VCCP_096 VSS_240 VSS_356 VSS[077] VSS[158]
AB18 AF14 AC19 L3 AH36 C23
VCC_177 VCCP_097 VSS_241 VSS_357 VSS[078] VSS[159]
AB16 AF12 AC17 N3 AK34 C25
+VCC_CORE VCC_178 VCCP_098 VSS_242 VSS_358 VSS[079] VSS[160]
AD18 AG13 AE19 R3 AM34 E25
VCC_179 VCCP_099 VSS_243 VSS_359 VSS[080] VSS[161]
AD16 AG11 AE17 U3 AP34 E23
VCC_180 VCCP_100 VSS_244 VSS_360 VSS[081] VSS[162]
Y20 AH14 AG19 W3 E21
VCC_181 VCCP_101 VSS_245 VSS_361 VSS[163]
AB20 AJ13 AG17 AA3
VCC_182 VCCP_102 VSS_246 VSS_362
AD20 AJ11 AJ19 AC3
+ C101 C40 C17 C23 C61 C41 C42 C25 C60 C24 C14 C62 C20 VCC_183 VCCP_103 VSS_247 VSS_363 Penryn_SFF_1p0
AF18 AF10 AJ17 AE3
VCC_184 VCCP_104 VSS_248 VSS_364
AF16 AK14 AL19 AG3
330u/2.5V_7343 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 VCC_185 VCCP_105 VSS_249 VSS_365
AH18 AK12 AL17 AJ3
C VCC_186 VCCP_106 VSS_250 VSS_366 C
AH16 AL13 AN19 AL3
VCC_187 VCCP_107 VSS_251 VSS_367
AF20 AL11 AN17 AN3
VCC_188 VCCP_108 VSS_252 VSS_368
AH20 AN13 AR19 AR3
VCC_189 VCCP_109 VSS_253 VSS_369
AK18 AN11 AR17 AU3
VCC_190 VCCP_110 VSS_254 VSS_370
AK16 AP12 AU19 AW3
VCC_191 VCCP_111 VSS_255 VSS_371
AM18 AR13 AU17 BA3
+VCC_CORE VCC_192 VCCP_112 VSS_256 VSS_372
AM16 AR11 AW19 BC3
VCC_193 VCCP_113 VSS_257 VSS_373
AP18 AK10 AW17 D2
VCC_194 VCCP_114 VSS_258 VSS_374
AP16 AP10 BA19 E1
VCC_195 VCCP_115 VSS_259 VSS_375
AK20 AU13 BA17 G1
VCC_196 VCCP_116 VSS_260 VSS_376
AM20 AU11 BC19 AW1
C31 C46 C32 C67 C65 C78 C72 C30 C12 C73 C29 C15 VCC_197 VCCP_117 VSS_261 VSS_377
AP20 L9 BC17 BA1
VCC_198 VCCP_118 VSS_262 VSS_378
AT18 L7 C11 BB2
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 VCC_199 VCCP_119 VSS_263 VSS_379
AT16 N9 C15 A41
VCC_200 VCCP_120 VSS_264 VSS_380
AV18 N7 E15 A39
VCC_201 VCCP_121 VSS_265 VSS_381
AV16 R9 G15 A29
VCC_202 VCCP_122 VSS_266 VSS_382
AY18 R7 H10 A27
VCC_203 VCCP_123 VSS_267 VSS_383
AY16 U9 M12 A31
VCC_204 VCCP_124 VSS_268 VSS_384
AT20 U7 J15 A25
VCC_205 VCCP_125 VSS_269 VSS_385
AV20 W9 L15 A23
+VCC_CORE VCC_206 VCCP_126 VSS_270 VSS_386
AY20 W7 N15 A21
VCC_207 VCCP_127 VSS_271 VSS_387
BB18 AA9 M10 A19
VCC_208 VCCP_128 VSS_272 VSS_388
BB16 AA7 T12 A17
VCC_209 VCCP_129 VSS_273 VSS_389
BD18 AC9 R15 A11
VCC_210 VCCP_130 VSS_274 VSS_390
BD16 AC7 U15 A15
C19 C71 C45 C76 C13 C47 C21 C68 C74 C77 C66 C16 VCC_211 VCCP_131 VSS_275 VSS_391
BB20 AE9 W15 A7
VCC_212 VCCP_132 VSS_276 VSS_392
BD20 AE7 T10 A5
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 VCC_213 VCCP_133 VSS_277 VSS_393
AM14 AG9 Y12 A9
VCC_214 VCCP_134 VSS_278 VSS_394
AP14 AG7 AD12 BD4
VCC_215 VCCP_135 VSS_279 VSS_395
AT14 AJ9
VCC_216 VCCP_136
AV14 AJ7
VCC_217 VCCP_137 Penryn_SFF_1p0
AY14 AL9
+1.05V VCC_218 VCCP_138
BB14 AL7
VCC_219 VCCP_139
BD14 AN9
VCC_220 VCCP_140
AN7
VCCP_141
AF38 AR9
+1.05V VCCP_017 VCCP_142
AG37 AR7
VCCP_018 VCCP_143
D AJ37 A33 D
VCCP_019 VCCP_144
AK38 A13
VCCP_020 VCCP_145

C75 C36 C52 C26 C18 C70 C64 C63 C22 C43 C28 C48 Penryn_SFF_1p0

1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4

PROJECT : BU3
Quanta Computer Inc.
Size Document Number Rev
Custom D3B
Penryn (POWER/NC)
NB7
Date: Monday, August 10, 2009 Sheet 4 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

GS45 H_D#[0..63]
U15A
H_A#3
H_A#[3..35]
H_A#[3..35] [3]
[3] H_D#[0..63] H_A#_3 L15
H_D#0 J7 B14 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
H6 H_D#_1 H_A#_5 C15
H_D#2 L11 D12 H_A#6
H_D#3 H_D#_2 H_A#_6 H_A#7
A J3 H_D#_3 H_A#_7 F14 A
H_D#4 H4 G17 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
G3 H_D#_5 H_A#_9 B12
H_D#6 K10 J15 H_A#10
H_D#7 H_D#_6 H_A#_10 H_A#11
K12 H_D#_7 H_A#_11 D16
H_D#8 L1 C17 H_A#12
H_D#9 H_D#_8 H_A#_12 H_A#13
M10 H_D#_9 H_A#_13 D14
H_D#10 M6 K16 H_A#14
H_D#11 H_D#_10 H_A#_14 H_A#15
N11 H_D#_11 H_A#_15 F16
H_D#12 L7 B16 H_A#16
H_D#13 H_D#_12 H_A#_16 H_A#17
K6 H_D#_13 H_A#_17 C21
H_D#14 M4 D18 H_A#18
+1.05V_VCCP_GMCH H_D#15 H_D#_14 H_A#_18 H_A#19
K4 H_D#_15 H_A#_19 J19
H_D#16 P6 J21 H_A#20
H_D#17 H_D#_16 H_A#_20 H_A#21
W9 H_D#_17 H_A#_21 B18
H_D#18 V6 D22 H_A#22
R50 H_D#19 H_D#_18 H_A#_22 H_A#23
V2 H_D#_19 H_A#_23 G19
H_D#20 P10 J17 H_A#24
221/F_4 H_D#21 H_D#_20 H_A#_24 H_A#25
W7 H_D#_21 H_A#_25 L21
H_D#22 N9 L19 H_A#26
H_SWING H_D#23 H_D#_22 H_A#_26 H_A#27
P4 H_D#_23 H_A#_27 G21
H_D#24 U9 D20 H_A#28
H_D#25 H_D#_24 H_A#_28 H_A#29
V4 H_D#_25 H_A#_29 K22
R53 C132 H_D#26 U1 F18 H_A#30
H_D#27 H_D#_26 H_A#_30 H_A#31
W3 H_D#_27 H_A#_31 K20
100/F_4 0.1u/10V_4 H_D#28 V10 F20 H_A#32
H_D#29 H_D#_28 H_A#_32 H_A#33
U7 H_D#_29 H_A#_33 F22
B H_D#30 W11 B20 H_A#34 B
H_D#31 H_D#_30 H_A#_34 H_A#35
U11 H_D#_31 H_A#_35 A19
H_D#32 AC11
H_D#33 H_D#_32
AC9 H_D#_33 H_ADS# F10 H_ADS# [3]
H_D#34 Y4 A15
H_D#_34 H_ADSTB#_0 H_ADSTB#0 [3]
H_D#35 Y10 C19
H_D#_35 H_ADSTB#_1 H_ADSTB#1 [3]

HOST
H_D#36 AB6 C9
H_D#_36 H_BNR# H_BNR# [3]
H_D#37 AA9 B8
H_D#_37 H_BPRI# H_BPRI# [3]
H_D#38 AB10 C11
H_D#_38 H_BREQ# H_BR0# [3]
H_D#39 AA1 E5
H_D#_39 H_DEFER# H_DEFER# [3]
H_D#40 AC3 D6
H_D#_40 H_DBSY# H_DBSY# [3]
H_D#41 AC7 AH10
H_D#_41 HPLL_CLK CLK_MCH_BCLK [2]
H_D#42 AD12 AJ11
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# [2]
H_D#43 AB4 G11
H_D#_43 H_DPWR# H_DPWR# [3]
Layout Note: H_D#44 Y6 H2
H_D#_44 H_DRDY# H_DRDY# [3]
H_D#45 AD10 C7
H_RCOMP trace should be H_D#46 AA11
H_D#_45 H_HIT#
F8
H_HIT# [3]
H_D#_46 H_HITM# H_HITM# [3]
10-mil wide with 20-mil spacing. H_D#47 AB2 H_D#_47 H_LOCK# A11 H_LOCK# [3]
H_D#48 AD4 D8
H_D#_48 H_TRDY# H_TRDY# [3]
H_D#49 AE7
H_D#50 H_D#_49
AD2 H_D#_50
H_D#51 AD6
R47 24.9/F_4 H_RCOMP H_D#52 H_D#_51
AE3 H_D#_52
H_D#53 AG9 L9
H_D#_53 H_DINV#_0 H_DINV#0 [3]
H_D#54 AG7 N7
H_D#_54 H_DINV#_1 H_DINV#1 [3]
H_D#55 AE11 AA7
H_D#_55 H_DINV#_2 H_DINV#2 [3]
H_D#56 AK6 AG3
H_D#_56 H_DINV#_3 H_DINV#3 [3]
C H_D#57 AF6 C
H_D#58 H_D#_57
AJ9 H_D#_58 H_DSTBN#_0 K2 H_DSTBN#0 [3]
H_D#59 AH6 N3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 [3]
H_D#60 AF12 AA3
H_D#_60 H_DSTBN#_2 H_DSTBN#2 [3]
H_D#61 AH4 AF4
H_D#_61 H_DSTBN#_3 H_DSTBN#3 [3]
H_D#62 AJ7
H_D#63 H_D#_62
AE9 H_D#_63 H_DSTBP#_0 L3 H_DSTBP#0 [3]
H_DSTBP#_1 M2 H_DSTBP#1 [3]
H_DSTBP#_2 Y2 H_DSTBP#2 [3]
H_SWING B6 AF2
H_SWING H_DSTBP#_3 H_DSTBP#3 [3]
H_RCOMP D4
+1.05V_VCCP_GMCH H_RCOMP
H_REQ#_0 J13 H_REQ#0 [3]
H_REQ#_1 L13 H_REQ#1 [3]
H_REQ#_2 C13 H_REQ#2 [3]
H_REQ#_3 G13 H_REQ#3 [3]
R63 J11 G15
[3] H_RESET# H_CPURST# H_REQ#_4 H_REQ#4 [3]
[3] H_CPUSLP# G9 H_CPUSLP#
1K/F_4 F4
H_RS#_0 H_RS#0 [3]
H_RS#_1 F2 H_RS#1 [3]
H_RS#_2 G7 H_RS#2 [3]
H_AVREF L17 H_AVREF
K18 H_DVREF
F3B CANTIGASFF_1p0
R67 R68

2K/F_4 *short_4
D D

H_DVREF

PROJECT : BU3
Quanta Computer Inc.
Size Document Number Rev
Custom D3B
GANTIGA HOST(1/6)
NB7
Date: Monday, August 10, 2009 Sheet 5 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

U15B

J43
RSVD1
L43 BB32

DDR CLK/ CONTROL/COMPENSATION

RSVD2 SA_CK_0 M_CLK_DDR0 [16]
J41 BA25 M_CLK_DDR1 [16]
RSVD3 SA_CK_1
L41 BA33 M_CLK_DDR2 [16]
RSVD4 SB_CK_0
AN11 BA23 M_CLK_DDR3 [16]
RSVD5 SB_CK_1
AM10
RSVD6
AK10 BA31 M_CLK_DDR#0 [16]
RSVD7 SA_CK#_0
AL11 BC25 M_CLK_DDR#1 [16]
RSVD8 SA_CK#_1
F12 BC33 M_CLK_DDR#2 [16]
RSVD9 SB_CK#_0

RSVD
BB24 M_CLK_DDR#3 [16]
SB_CK#_1
BC35 M_CKE0 [16]
SA_CKE_0
BE33 M_CKE1 [16]
SA_CKE_1 U15C
C27 BE37 M_CKE2 [16]
RSVD14 SB_CKE_0
D30 BC37 M_CKE3 [16]
RSVD15 SB_CKE_1
J9 BK18 +1.05V_VCC_PEG
RSVD17 SA_CS#_0 M_CS#0 [16]
BK16 M_CS#1 [16] [17] INT_LVDS_PWM D38
A SA_CS#_1 L_BKLT_CTRL PEG_COMP R110 49.9/F_4 A
BE23 M_CS#2 [16] [17] INT_LVDS_BLON C37 U45
SB_CS#_0 L_CTRL_CLK L_BKLT_EN PEG_COMPI
AW42 BC19 M_CS#3 [16] K38 T44
RSVD20 SB_CS#_1 L_CTRL_CLK PEG_COMPO
BJ17 L_CTRL_DATA L37
SA_ODT_0 M_ODT0 [16] L_CTRL_DATA
BJ19 M_ODT1 [16] [17] LCD_DDCCLK J37 D52
SA_ODT_1 L_DDC_CLK PEG_RX#_0
BB20 BC17 M_ODT2 [16] [17] LCD_DDCDAT L35 G49
RSVD22 SB_ODT_0 L_DDC_DATA PEG_RX#_1
BE19 BE17 M_ODT3 [16] K54
RSVD23 SB_ODT_1 PEG_RX#_2
BF20
BF18
RSVD24
BL25 SMRCOMPP
close to chipset B36
PEG_RX#_3
H50
M52
RSVD25 SM_RCOMP [17] INT_LVDS_DIGON L_VDD_EN PEG_RX#_4
BK26 SMRCOMPN LVDS_IBG F50 N49
SM_RCOMP# INT_TXLCLKOUT- LVDS_IBG PEG_RX#_5
T21 H46 P54
SM_RCOMP_VOH LVDS_VBG PEG_RX#_6
BK32 P44 V46
SM_RCOMP_VOH SM_RCOMP_VOL LVDS_VREFH PEG_RX#_7
BL31 K46 Y50
SM_RCOMP_VOL C350 INT_TXLCLKOUT- LVDS_VREFL PEG_RX#_8
T22 AN45 [17] INT_TXLCLKOUT- D46 V52
ME_JTAG_TCK SMDDR_VREF INT_TXLCLKOUT+ LVDSA_CLK# PEG_RX#_9
T18 AP44 BC51 [17] INT_TXLCLKOUT+ B46 W49
ME_JTAG_TDI SM_VREF LVDSA_CLK PEG_RX#_10

LVDS
AT44 AY37 SM_PWROK *100p/50V_4 D44 AB54
T17 ME_JTAG_TDO SM_PWROK LVDSB_CLK# PEG_RX#_11
AN47 BH20 SM_REXT B44 AD46
T23 ME_JTAG_TMS SM_REXT LVDSB_CLK PEG_RX#_12
BA37 INT_TXLCLKOUT+ AC55
SM_DRAMRST# DDR3_DRAMRST# [16] PEG_RX#_13
INT_TXLOUT0- G45 AE49
[17] INT_TXLOUT0- LVDSA_DATA#_0 PEG_RX#_14
B42 INT_TXLOUT1- F46 AF54
DPLL_REF_CLK
DPLL_REF_CLK#
D42
MCH_DREFCLK [2]
MCH_DREFCLK# [2]
BOI [17] INT_TXLOUT1-
[17] INT_TXLOUT2-
INT_TXLOUT2- G41
LVDSA_DATA#_1
LVDSA_DATA#_2
PEG_RX#_15

GRAPHICS
B50 INT_TXLOUT3- C45 E51
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
D50
DREF_SSCLK [2]
DREF_SSCLK# [2]
T20 LVDSA_DATA#_3 PEG_RX_0
PEG_RX_1
F48 F3B HDMI Port B
INT_TXLOUT0+ F44 J55
[17] INT_TXLOUT0+ LVDSA_DATA_0 PEG_RX_2
R49 INT_TXLOUT1+ G47 J49 PEG_RXP3 R134 *short_4

CLK
PEG_CLK CLK_MCH_3GPLL [2] [17] INT_TXLOUT1+ LVDSA_DATA_1 PEG_RX_3 PORT-B_HPD# [18]
P50 INT_TXLOUT2+ F40 M54
PEG_CLK# CLK_MCH_3GPLL# [2] [17] INT_TXLOUT2+ LVDSA_DATA_2 PEG_RX_4
INT_TXLOUT3+ A45 M50
T19 LVDSA_DATA_3 PEG_RX_5
P52
PEG_RX_6
B40 U47
LVDSB_DATA#_0 PEG_RX_7
Layout Note: DMI_RXN_0
AG55 DMI_MRX_ITX_N0 [13] A41
LVDSB_DATA#_1 PEG_RX_8
AA49
AL49 F42 V54
Location of all MCH_CFG strap DMI_RXN_1
AH54
DMI_MRX_ITX_N1 [13]
D48
LVDSB_DATA#_2 PEG_RX_9
V50
DMI_RXN_2 DMI_MRX_ITX_N2 [13] LVDSB_DATA#_3 PEG_RX_10
resistors needs to be close to DMI_RXN_3
AL47 DMI_MRX_ITX_N3 [13] PEG_RX_11
AB52
minmize stub. D40 AC47
LVDSB_DATA_0 PEG_RX_12
AG53 DMI_MRX_ITX_P0 [13] C41 AC53
DMI_RXP_0 LVDSB_DATA_1 PEG_RX_13

PCI-EXPRESS
[2] MCH_BSEL0 K26 AK50 DMI_MRX_ITX_P1 [13] G43 AD50
CFG_0 DMI_RXP_1 LVDSB_DATA_2 PEG_RX_14
[2] MCH_BSEL1 G23 AH52 DMI_MRX_ITX_P2 [13] B48 AF52
CFG_1 DMI_RXP_2 LVDSB_DATA_3 PEG_RX_15
[2] MCH_BSEL2 G25 AL45 DMI_MRX_ITX_P3 [13]
MCH_CFG3 CFG_2 DMI_RXP_3 PEG_TXN0 C238 [email protected]/10V_4
T15 J25 L47 TMDSB_DATA2# [18]
MCH_CFG4 CFG_3 PEG_TX#_0 PEG_TXN1 C235 [email protected]/10V_4
T14 L25 AG49 DMI_MTX_IRX_N0 [13] F52 TMDSB_DATA1# [18]
MCH_CFG5 CFG_4 DMI_TXN_0 INT_TV_COMP PEG_TX#_1 PEG_TXN2 C240 [email protected]/10V_4
[11] MCH_CFG5 L27 AJ49 DMI_MTX_IRX_N1 [13] J27 P46 TMDSB_DATA0# [18]
CFG_5 DMI_TXN_1 TVA_DAC PEG_TX#_2

TV
MCH_CFG6 F24 AJ47 INT_TV_Y/G E27 H54 PEG_TXN3 C241 [email protected]/10V_4
B [11] MCH_CFG6 CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2 [13] TVB_DAC PEG_TX#_3 TMDSB_CLK# [18] B
MCH_CFG7 D24 AG47 INT_TV_C/R G27 L55
[11] MCH_CFG7 CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 [13] TVC_DAC PEG_TX#_4
MCH_CFG8 D26 T46
T13 CFG_8 PEG_TX#_5
CFG
MCH_CFG9 J23 AF50 F26 R53
[11] MCH_CFG9 DMI_MTX_IRX_P0 [13]
MCH_CFG10 CFG_9
DMI DMI_TXP_0 TVA_RTN PEG_TX#_6
[11] MCH_CFG10 B26 AH50 DMI_MTX_IRX_P1 [13] U49
MCH_CFG11 CFG_10 DMI_TXP_1 PEG_TX#_7
T9 A23 AJ45 DMI_MTX_IRX_P2 [13] T54
MCH_CFG12 CFG_11 DMI_TXP_2 PEG_TX#_8
[11] MCH_CFG12 C23 AG45 DMI_MTX_IRX_P3 [13] Y46
MCH_CFG13 CFG_12 DMI_TXP_3 PEG_TX#_9
[11] MCH_CFG13 B24 B34 AB46
MCH_CFG14 CFG_13 TV_DCONSEL_0 PEG_TX#_10
T11 B22 D34 W53
MCH_CFG15 CFG_14 TV_DCONSEL_1 PEG_TX#_11
T12 K24 Y54
MCH_CFG16 CFG_15 PEG_TX#_12
[11] MCH_CFG16 C25 AC49
MCH_CFG17 CFG_16 PEG_TX#_13
T10 L23 AF46
MCH_CFG18 CFG_17 PEG_TX#_14
L33 AD54
GRAPHICS VID

T16 CFG_18 PEG_TX#_15

MCH_CFG19 K32
[11] MCH_CFG19 CFG_19
MCH_CFG20 K34 G33 CRT_BLUE J29 J47 PEG_TXP0 C237 [email protected]/10V_4
[11] MCH_CFG20 CFG_20 GFX_VID_0 GPU_VID0 [30] [17] CRT_BLUE CRT_BLUE PEG_TX_0 TMDSB_DATA2 [18]
G37 F54 PEG_TXP1 C236 [email protected]/10V_4
GFX_VID_1 GPU_VID1 [30] PEG_TX_1 TMDSB_DATA1 [18]
F38 CRT_GREEN G29 N47 PEG_TXP2 C239 [email protected]/10V_4
GFX_VID_2 GPU_VID2 [30] [17] CRT_GREEN CRT_GREEN PEG_TX_2 TMDSB_DATA0 [18]
F36 H52 PEG_TXP3 C242 [email protected]/10V_4
GFX_VID_3 GPU_VID3 [30] PEG_TX_3 TMDSB_CLK [18]
J35 G35 CRT_RED F30 L53
[14] PM_SYNC# PM_SYNC# GFX_VID_4 GPU_VID4 [30] [17] CRT_RED CRT_RED PEG_TX_4

VGA
[3,12,26] H_DPRSTP# F6 R47
PM_EXTTS#0 PM_DPRSTP# PEG_TX_5
J39 E29 R55
[16] PM_EXTTS#0 PM_EXT_TS#_0 D3B CRT_IRTN PEG_TX_6
PM

PM_EXTTS#1 L39 T50

[16] PM_EXTTS#1 PM_EXT_TS#_1 CRT_DDCCLK PEG_TX_7
[3,14,26] DELAY_VR_PWRGOOD AY39 G39 GFX_VR_EN [30] [17] CRT_DDCCLK D36 T52
R65 100_4 RSTIN#_MCH PWROK GFX_VR_EN CRT_DDCDAT CRT_DDC_CLK PEG_TX_8
[13] PCI_PLTRST# BB18 [17] CRT_DDCDAT C35 W47
R280 *0_4 RSTIN# R281 30.1/F_4 HSYNC CRT_DDC_DATA PEG_TX_9
[3,12] PM_THRMTRIP# K28 [17] CRT_HSYNC J33 AA47
THERMTRIP# CRT_IREF CRT_HSYNC PEG_TX_10
[14,26] DPRSLPVR
K36 D32 W55
DPRSLPVR R282 30.1/F_4 VSYNC CRT_TVO_IREF PEG_TX_11
[17] CRT_VSYNC G31 Y52
CRT_VSYNC PEG_TX_12
AK52 CL_CLK0 [14] AB50
CL_CLK PEG_TX_13
AK54 CL_DATA0 [14] AE47
CL_DATA PEG_TX_14
A7 AW40 MPWROK [14,22] AD52
NC_1 CL_PWROK PEG_TX_15
A49 AL53 ICH_CL_RST0# [14]
NC_2 CL_RST# MCH_CLVREF
A52 AL55
ME

NC_3 CL_VREF CANTIGASFF_1p0

A54
NC_4
B54
NC_5
D55
NC_6 DDPC_CTRLCLK
G55 F34 DDPC_CTRLCLK [11]
NC_7 DDPC_CTRLCLK
NC

DDPC_CTRLDATA
BE55
BH55
NC_8 DDPC_CTRLDATA
F32
B38 SDVO_CTRLCLK
DDPC_CTRLDATA [11] SDVO=>Port B
NC_9 SDVO_CTRLCLK SDVO_CTRLCLK [18]
BK55
NC_10 SDVO_CTRLDATA
A37 SDVO_CTRLDATA
CLK_3GPLLREQ#
SDVO_CTRLDATA [18] DDPC=>Port C
BK54 C31
MISC

NC_11 CLKREQ# CLK_3GPLLREQ# [2]

BL54 K42 MCH_ICH_SYNC# [14]
NC_12 ICH_SYNC#
BL52
NC_13
BL49
C NC_14 TSATN# C
BL7 D10
NC_15 TSATN#
BL4
NC_16
BL2
NC_17
BK2
NC_18
BK1
NC_19
BH1
NC_20
BE1
NC_21
G1 C29 ICH_AZ_HDMI_BITCLK [12]
NC_22 HDA_BCLK
B30 ICH_AZ_HDMI_RST# [12]
HDA_RST# ICH_AZ_HDMI_SDIN1_R R283 HM@33_4
D28 ICH_AZ_HDMI_SDIN1 [12]
HDA_SDI
A27
HDA

HDA_SDO ICH_AZ_HDMI_SDOUT [12]

B28 ICH_AZ_HDMI_SYNC [12]
HDA_SYNC

CANTIGASFF_1p0

Check list note : CL_REF=0.35V +1.05V SM_VREF.Default use voltage divider for poor layout cause +SMDDR_VREF not <Checklist ver0.8> CRT setting
meet spec.And Intel circuit PU/PD is 1K,But Check list PU/PD is 10K. If TSATN# is not used, then it must be terminated
CRT_BLUE R74 150/F_4
with a 56-Ω pull-up resistor to VCCP. CRT_GREEN R78 150/F_4
R127 R123 *0_6 +SMDDR_VREF CRT_RED R80 150/F_4 LVDS setting
+1.05V
1K/F_4
(15mils) (20mils) TSATN# R57 56_4 +3V
MCH_CLVREF SMDDR_VREF R125 10K/F_4 +1.5VSUS_GMCH CRT_IREF R98 1K/F_4

+3V L_CTRL_CLK R290 10K_4

C243 R128 L_CTRL_DATA R287 10K_4
R120 PM_EXTTS#0 R113 10K_4 INT_TV_COMP R96 75/F_4
0.1u/10V_4 511/F_6 PM_EXTTS#1 R103 10K_4 INT_TV_Y/G R83 75/F_4
10K/F_4 CLK_3GPLLREQ# R94 10K_4 INT_TV_C/R R95 75/F_4
SM_REXT R79 499/F_4

LVDS_IBG 2.37K/F_4 R119

D D
SM_PWROK only for DDR3.(DDR2 PD only)
R100 1K/F_4 SM_RCOMP_VOH +3VPCU
+1.5VSUS_GMCH +1.5VSUS_GMCH
B1A
R101 C195 C204 U22
SMRCOMPP R90 80.6/F_4 F3B
5

3.01K/F_4 0.01u/25V_4 2.2u/6.3V_6

R378 *short_4 2
[22,27] HWPG_1.5V
4 DDR3_POWER_OK R116 12K/F_4 SM_PWROK
SM_RCOMP_VOL 1
SMRCOMPN R115 80.6/F_4
R117
PROJECT : BU3
3

R104 C198 C196 TC7SH08FU(F)

1K/F_4 0.01u/25V_4 2.2u/6.3V_6

10K/F_6 Quanta Computer Inc.
Size Document Number Rev
Custom D3B
GANTIGA VGA/DMI(2/6)
NB7
Date: Monday, August 10, 2009 Sheet 6 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

A A

[16] M_A_DQ[63:0] [16] M_B_DQ[63:0]

U15D U15E
M_A_DQ0 AP46 BC21 M_A_BS#0 M_B_DQ0 AP54 BJ13 M_B_BS#0
SA_DQ_0 SA_BS_0 M_A_BS#0 [16] SB_DQ_0 SB_BS_0 M_B_BS#0 [16]
M_A_DQ1 AU47 BJ21 M_A_BS#1 M_B_DQ1 AM52 BK12 M_B_BS#1
SA_DQ_1 SA_BS_1 M_A_BS#1 [16] SB_DQ_1 SB_BS_1 M_B_BS#1 [16]
M_A_DQ2 AT46 BJ41 M_A_BS#2 M_B_DQ2 AR55 BK38 M_B_BS#2
SA_DQ_2 SA_BS_2 M_A_BS#2 [16] SB_DQ_2 SB_BS_2 M_B_BS#2 [16]
M_A_DQ3 AU49 M_B_DQ3 AV54
M_A_DQ4 SA_DQ_3 M_A_RAS# M_B_DQ4 SB_DQ_3
AR45 BH22 M_A_RAS# [16] AM54
M_A_DQ5 SA_DQ_4 SA_RAS# M_A_CAS# M_B_DQ5 SB_DQ_4 M_B_RAS#
AN49 SA_DQ_5 SA_CAS# BK20 M_A_CAS# [16] AN53 SB_DQ_5 SB_RAS# BE21 M_B_RAS# [16]
M_A_DQ6 AV50 BL15 M_A_W E# M_B_DQ6 AT52 BH14 M_B_CAS#
SA_DQ_6 SA_WE# M_A_W E# [16] SB_DQ_6 SB_CAS# M_B_CAS# [16]
M_A_DQ7 AP50 M_B_DQ7 AU53 BK14 M_B_W E#
SA_DQ_7 SB_DQ_7 SB_WE# M_B_W E# [16]
M_A_DQ8 AW47 M_B_DQ8 AW53
M_A_DQ9 SA_DQ_8 M_B_DQ9 SB_DQ_8
BD50 SA_DQ_9 AY52 SB_DQ_9
M_A_DQ10 AW49 M_B_DQ10 BB52
SA_DQ_10 M_A_DM[7:0] [16] SB_DQ_10
M_A_DQ11 BA49 AT50 M_A_DM0 M_B_DQ11 BC53
SA_DQ_11 SA_DM_0 SB_DQ_11 M_B_DM[7:0] [16]
M_A_DQ12 BC49 BB50 M_A_DM1 M_B_DQ12 AV52 AP52 M_B_DM0
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AV46 BB46 AW55 AY54
M_A_DQ14 SA_DQ_13 SA_DM_2 M_A_DM3 M_B_DQ14 SB_DQ_13 SB_DM_1 M_B_DM2
BA47 BE39 BD52 BJ49
M_A_DQ15 SA_DQ_14 SA_DM_3 M_A_DM4 M_B_DQ15 SB_DQ_14 SB_DM_2 M_B_DM3
AY50 BB12 BC55 BJ43
M_A_DQ16 SA_DQ_15 SA_DM_4 M_A_DM5 M_B_DQ16 SB_DQ_15 SB_DM_3 M_B_DM4
BF46 SA_DQ_16 SA_DM_5 BE7 BF54 SB_DQ_16 SB_DM_4 BH12
B
A B
M_A_DQ17 BC47 AV10 M_A_DM6 M_B_DQ17 BE51 BD2 M_B_DM5
M_A_DQ18 SA_DQ_17 SA_DM_6 M_A_DM7 M_B_DQ18 SB_DQ_17 SB_DM_5 M_B_DM6
BF50 SA_DQ_18 SA_DM_7 AR9 BH48 SB_DQ_18 SB_DM_6 AY2
M_A_DQ19 M_B_DQ19 M_B_DM7

B
BF48 SA_DQ_19 M_A_DQS[7:0] [16] BK48 SB_DQ_19 SB_DM_7 AJ3
M_A_DQ20 BC43 AR47 M_A_DQS0 M_B_DQ20 BE53
SA_DQ_20 SA_DQS_0 SB_DQ_20 M_B_DQS[7:0] [16]
M_A_DQ21 BE49 BA45 M_A_DQS1 M_B_DQ21 BH52 AR53 M_B_DQS0
MEMORY

M_A_DQ22 SA_DQ_21 SA_DQS_1 M_A_DQS2 M_B_DQ22 SB_DQ_21 SB_DQS_0 M_B_DQS1

BA43 BE45 BK46 BA53
M_A_DQ23 SA_DQ_22 SA_DQS_2 M_A_DQS3 M_B_DQ23 SB_DQ_22 SB_DQS_1 M_B_DQS2
BE47 SA_DQ_23 SA_DQS_3 BC41 BJ47 SB_DQ_23 SB_DQS_2 BH50

MEMORY
M_A_DQ24 BF42 BC13 M_A_DQS4 M_B_DQ24 BL45 BK42 M_B_DQS3
M_A_DQ25 SA_DQ_24 SA_DQS_4 M_A_DQS5 M_B_DQ25 SB_DQ_24 SB_DQS_3 M_B_DQS4
BC39 BB10 BJ45 BH8
M_A_DQ26 SA_DQ_25 SA_DQS_5 M_A_DQS6 M_B_DQ26 SB_DQ_25 SB_DQS_4 M_B_DQS5
BF44 SA_DQ_26 SA_DQS_6 BA7 BL41 SB_DQ_26 SB_DQS_5 BB2
M_A_DQ27 BF40 AN7 M_A_DQS7 M_B_DQ27 BH44 AV2 M_B_DQS6
SA_DQ_27 SA_DQS_7 M_A_DQS#[7:0] [16] SB_DQ_27 SB_DQS_6
M_A_DQ28 BB40 AR49 M_A_DQS#0 M_B_DQ28 BH46 AM2 M_B_DQS7
SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 M_B_DQS#[7:0] [16]
M_A_DQ29 BE43 AW45 M_A_DQS#1 M_B_DQ29 BK44 AT54 M_B_DQS#0
M_A_DQ30 SA_DQ_29 SA_DQS#_1 M_A_DQS#2 M_B_DQ30 SB_DQ_29 SB_DQS#_0 M_B_DQS#1
BF38 BC45 BK40 BB54
M_A_DQ31 SA_DQ_30 SA_DQS#_2 M_A_DQS#3 M_B_DQ31 SB_DQ_30 SB_DQS#_1 M_B_DQS#2
BE41 SA_DQ_31 SA_DQS#_3 BA41 BJ39 SB_DQ_31 SB_DQS#_2 BJ51
M_A_DQ32 BA15 BA13 M_A_DQS#4 M_B_DQ32 BK10 BH42 M_B_DQS#3
M_A_DQ33 SA_DQ_32 SA_DQS#_4 M_A_DQS#5 M_B_DQ33 SB_DQ_32 SB_DQS#_3 M_B_DQS#4
BE11 BA11 BH10 BK8
M_A_DQ34 SA_DQ_33 SA_DQS#_5 M_A_DQS#6 M_B_DQ34 SB_DQ_33 SB_DQS#_4 M_B_DQS#5
SYSTEM

BE15 BA9 BK6 BC3

M_A_DQ35 SA_DQ_34 SA_DQS#_6 M_A_DQS#7 M_B_DQ35 SB_DQ_34 SB_DQS#_5 M_B_DQS#6
BF14 SA_DQ_35 SA_DQS#_7 AN9 BH6 SB_DQ_35 SB_DQS#_6 AW3
M_A_DQ36 BB14 M_B_DQ36 BJ9 AN3 M_B_DQS#7
SA_DQ_36 M_A_A[14:0] [16] SB_DQ_36 SB_DQS#_7

SYSTEM
M_A_DQ37 BC15 BC23 M_A_A0 M_B_DQ37 BL11
SA_DQ_37 SA_MA_0 SB_DQ_37 M_B_A[14:0] [16]
M_A_DQ38 BE13 BF22 M_A_A1 M_B_DQ38 BG5 BJ15 M_B_A0
M_A_DQ39 SA_DQ_38 SA_MA_1 M_A_A2 M_B_DQ39 SB_DQ_38 SB_MA_0 M_B_A1
BF16 BE31 BJ5 BJ33
M_A_DQ40 SA_DQ_39 SA_MA_2 M_A_A3 M_B_DQ40 SB_DQ_39 SB_MA_1 M_B_A2
BF10 SA_DQ_40 SA_MA_3 BC31 BG3 SB_DQ_40 SB_MA_2 BH24
M_A_DQ41 BC11 BH26 M_A_A4 M_B_DQ41 BF4 BA17 M_B_A3
M_A_DQ42 SA_DQ_41 SA_MA_4 M_A_A5 M_B_DQ42 SB_DQ_41 SB_MA_3 M_B_A4
BF8 SA_DQ_42 SA_MA_5 BJ35 BD4 SB_DQ_42 SB_MA_4 BF36
M_A_DQ43 BG7 BB34 M_A_A6 M_B_DQ43 BA3 BH36 M_B_A5
M_A_DQ44 SA_DQ_43 SA_MA_6 M_A_A7 M_B_DQ44 SB_DQ_43 SB_MA_5 M_B_A6
BC7 BH32 BE5 BF34
M_A_DQ45 SA_DQ_44 SA_MA_7 M_A_A8 M_B_DQ45 SB_DQ_44 SB_MA_6 M_B_A7
BC9 BB26 BF2 BK34
M_A_DQ46 SA_DQ_45 SA_MA_8 M_A_A9 M_B_DQ46 SB_DQ_45 SB_MA_7 M_B_A8
BD6 BF32 BB4 BJ37
SA_DQ_46 SA_MA_9 SB_DQ_46 SB_MA_8
DDR

C M_A_DQ47 BF12 BA21 M_A_A10 M_B_DQ47 AY4 BH40 M_B_A9 C

M_A_DQ48 SA_DQ_47 SA_MA_10 M_A_A11 M_B_DQ48 SB_DQ_47 SB_MA_9 M_B_A10
AV6 SA_DQ_48 SA_MA_11 BG25 BA1 SB_DQ_48 SB_MA_10 BH16
M_A_DQ49 BB6 BH34 M_A_A12 M_B_DQ49 AP2 BK36 M_B_A11
SA_DQ_49 SA_MA_12 SB_DQ_49 SB_MA_11

DDR
M_A_DQ50 AW7 BH18 M_A_A13 M_B_DQ50 AU1 BH38 M_B_A12
M_A_DQ51 SA_DQ_50 SA_MA_13 M_A_A14 M_B_DQ51 SB_DQ_50 SB_MA_12 M_B_A13
AY6 SA_DQ_51 SA_MA_14 BE25 AT2 SB_DQ_51 SB_MA_13 BJ11
M_A_DQ52 AT10 M_B_DQ52 AT4 BL37 M_B_A14
M_A_DQ53 SA_DQ_52 M_B_DQ53 SB_DQ_52 SB_MA_14
AW11 SA_DQ_53 AV4 SB_DQ_53
M_A_DQ54 AU11 M_B_DQ54 AU3
M_A_DQ55 SA_DQ_54 M_B_DQ55 SB_DQ_54
AW9 SA_DQ_55 AR3 SB_DQ_55
M_A_DQ56 AR11 M_B_DQ56 AN1
M_A_DQ57 SA_DQ_56 M_B_DQ57 SB_DQ_56
AT6 AP4
M_A_DQ58 SA_DQ_57 M_B_DQ58 SB_DQ_57
AP6 AL3
M_A_DQ59 SA_DQ_58 M_B_DQ59 SB_DQ_58
AL7 SA_DQ_59 AJ1 SB_DQ_59
M_A_DQ60 AR7 M_B_DQ60 AK4
M_A_DQ61 SA_DQ_60 M_B_DQ61 SB_DQ_60
AT12 AM4
M_A_DQ62 SA_DQ_61 M_B_DQ62 SB_DQ_61
AM6 SA_DQ_62 AH2 SB_DQ_62
M_A_DQ63 AU7 M_B_DQ63 AK2
SA_DQ_63 SB_DQ_63
CANTIGASFF_1p0 CANTIGASFF_1p0

D D

PROJECT : BU3
Quanta Computer Inc.
Size Document Number Rev
Custom D3B
GANTIGA DDRII(3/6)
NB7
Date: Monday, August 10, 2009 Sheet 7 of 34
1 2 3 4 5 6 7 8
 5 4 3 2 1

DDR3-800 3.1625A UMA 9.6A

DDR3-1066 4.14A U15G (Plane or shape)
(Shape or 200mils)
+1.05VGFX_CORE_INT
Ivcc internal VGA 2.2A +1.5VSUS_GMCH
(Shape or 120mils) +1.05V_VCC_GMCH F3B +1.05V

U15F T32 R293 *short_1206

+VCC_SM_BB36 VCC_AXG_NCTF_1
BB36 U31
+VCC_SM_BE35 VCC_SM_1 VCC_AXG_NCTF_2
BE35 T31
D +1.05V_VCC_GMCH VCC_SM_2 VCC_AXG_NCTF_3 C209 C205 C208 C192 + C189 D
AW34 VCC_SM_3 VCC_AXG_NCTF_4 R31
AW32 VCC_SM_4 VCC_AXG_NCTF_5 U29
C226 C223 BK30 T29 0.1u/10V_4 0.22u/10V_4 0.22u/10V_4 10u/6.3V_8 220u/2.5V_3528
VCC_SM_5 VCC_AXG_NCTF_6
BH30 VCC_SM_6 VCC_AXG_NCTF_7 R29
AT41 0.1u/10V_4 0.1u/10V_4 BF30 U28
VCC_1 VCC_SM_7 VCC_AXG_NCTF_8
AR41 VCC_2 BD30 VCC_SM_8 VCC_AXG_NCTF_9 U27
AN41 VCC_3 BB30 VCC_SM_9 VCC_AXG_NCTF_10 T27 Layout Note:
AJ41 AW30 R27
AH41
VCC_4
BL29
VCC_SM_10 VCC_AXG_NCTF_11
U25
Inside GMCH cavity.
VCC_5 VCC_SM_11 VCC_AXG_NCTF_12
AD41 BJ29 T25
VCC_6 VCC_SM_12 VCC_AXG_NCTF_13
AC41 BG29 R25
VCC_7 VCC_SM_13 VCC_AXG_NCTF_14
Y41 VCC_8 BE29 VCC_SM_14 VCC_AXG_NCTF_15 U24
W41 +VCC_SM_BC29 BC29 U22
VCC_9 VCC_SM_15 VCC_AXG_NCTF_16
AT40 BA29 T22
VCC_10 VCC_SM_16 VCC_AXG_NCTF_17

POWER
AM40 AY29 R22
VCC_11 C210 VCC_SM_17 VCC_AXG_NCTF_18
AL40 BK28 U21
VCC_12 VCC_SM_18 VCC_AXG_NCTF_19
BH28 T21
0.1u/10V_4 VCC_SM_19 VCC_AXG_NCTF_20
AJ40 BF28 R21
VCC_13 VCC_SM_20 VCC_AXG_NCTF_21 +1.5VSUS_GMCH +1.5VSUS
AH40 BD28 AM19
VCC_14 VCC_SM_21 VCC_AXG_NCTF_22 F3B
VCC CORE

AG40 BB28 AL19

VCC_15 VCC_SM_22 VCC_AXG_NCTF_23 R82 0_1206
AE40 VCC_16 BL27 VCC_SM_23 VCC_AXG_NCTF_24 AH19
AD40 VCC_17 BJ27 VCC_SM_24 VCC_AXG_NCTF_25 AG19
AC40 BG27 AE19
VCC_18 VCC_SM_25 VCC_AXG_NCTF_26 C176 C175 C173 + C154
AA40 BE27 AD19

VCC SM
VCC_19 VCC_SM_26 VCC_AXG_NCTF_27
Y40 BC27 AC19
VCC_20 VCC_SM_27 VCC_AXG_NCTF_28 0.1u/10V_4 10u/6.3V_8 10u/6.3V_8 *220u/2.5V_3528
AN35 BA27

VCC GFX NCTF

W19
VCC_21 VCC_SM_28 VCC_AXG_NCTF_29
AM35 VCC_22 AY27 VCC_SM_29 VCC_AXG_NCTF_30 U19
AJ35 AW26 AM18
VCC_23 +VCC_SM_BF24 VCC_SM_30 VCC_AXG_NCTF_31
AH35 VCC_24 BF24 VCC_SM_31 VCC_AXG_NCTF_32 AL18
AD35 +VCC_SM_BL19 BL19 AJ18
VCC_25 +VCC_SM_BB16 VCC_SM_32 VCC_AXG_NCTF_33
AC35 BB16 AH18
VCC_26 VCC_SM_33 VCC_AXG_NCTF_34
W35 VCC_27 VCC_AXG_NCTF_35 AG18
AM34 +1.05VGFX_CORE_INT AE18
VCC_28 C165 C143 C137 VCC_AXG_NCTF_36
C AL34 VCC_29 VCC_AXG_NCTF_37 AD18 C
AJ34 AC18
VCC_30 +1.05V_VCC_GMCH 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VCC_AXG_NCTF_38
AH34 W32 AA18
AG34
VCC_31
VCC_32
AG31
VCC_AXG_1
VCC_AXG_2
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
Y18 E3A +1.05V
AE34 AE31 W18
VCC_33 VCC_AXG_3 VCC_AXG_NCTF_41 +1.05VGFX_CORE_INT
AD34 AD31 U18
VCC_34 VCC_AXG_4 VCC_AXG_NCTF_42 R66 40@0_1206
AT38 AC31 T18
VCC_NCTF_1 VCC_AXG_5 VCC_AXG_NCTF_43
POWER

AC34 AR38 AA31 R18

VCC_35 VCC_NCTF_2 VCC_AXG_6 VCC_AXG_NCTF_44 R58 40@0_1206
AA34 AN38 Y31
VCC_36 VCC_NCTF_3 VCC_AXG_7
AM38 W31
VCC_NCTF_4 VCC_AXG_8
Y34
VCC_37 VCC_NCTF_5
AL38 AH29
VCC_AXG_9 BOM Note:
W34 AG38 AG29 C172 C169 C160 C159 C180 C184
AM32
VCC_38 VCC_NCTF_6
AE38 AE29
VCC_AXG_10 for reader stand by
VCC_39 VCC_NCTF_7 VCC_AXG_11
AL32
VCC_40 VCC_NCTF_8
AA38 AD29
VCC_AXG_12 VCC_AXG_62
AJ16 0.47u/6.3V_4 1u/10V_6 10u/6.3V_8 10u/6.3V_8 0.1u/10V_4 0.1u/10V_4 GS40 used 40@
AJ32 Y38 AC29 AH16 GS45 used 45@
VCC_41 VCC_NCTF_9 VCC_AXG_13 VCC_AXG_63
AH32 W38 AA29 AD16
VCC_42 VCC_NCTF_10 VCC_AXG_14 VCC_AXG_64
AE32 U38 Y29 AC16
VCC_43 VCC_NCTF_11 VCC_AXG_15 VCC_AXG_65
AD32 T38 W29 AA16
VCC_44 VCC_NCTF_12 VCC_AXG_16 VCC_AXG_66
AA32 R38 AH28 U16
VCC_45 VCC_NCTF_13 VCC_AXG_17 VCC_AXG_67
AM31 VCC_46 VCC_NCTF_14 AT37 AG28 VCC_AXG_18 VCC_AXG_68 T16
AL31 AR37 AE28 R16

VCC GFX
VCC_47 VCC_NCTF_15 VCC_AXG_19 VCC_AXG_69
AJ31 AN37 AA28 AM15
VCC_48 VCC_NCTF_16 VCC_AXG_20 VCC_AXG_70
AH31 VCC_49 VCC_NCTF_17 AM37 AH27 VCC_AXG_21 VCC_AXG_71 AL15
AM29 AL37 AG27 AJ15
VCC_50 VCC_NCTF_18 VCC_AXG_22 VCC_AXG_72
AL29 AJ37 AE27 AH15
VCC_51 VCC_NCTF_19 VCC_AXG_23 VCC_AXG_73
AM28 AH37 AD27 AG15
VCC_52 VCC_NCTF_20 VCC_AXG_24 VCC_AXG_74
AL28 VCC_53 VCC_NCTF_21 AG37 AC27 VCC_AXG_25 VCC_AXG_75 AE15
AJ28 AE37 AA27 AA15 +1.05VGFX_CORE_INT
AM27
VCC_54
VCC_55
VCC_NCTF_22
VCC_NCTF_23
AD37 Y27
VCC_AXG_26
VCC_AXG_27
VCC_AXG_76
VCC_AXG_77
Y15 F3B
AL27 VCC_56 VCC_NCTF_24 AC37 W27 VCC_AXG_28 VCC_AXG_78 W15
AM25 AA37 AH25 U15
VCC_57 VCC_NCTF_25 VCC_AXG_29 VCC_AXG_79
VCC NCTF

AL25 Y37 AD25 T15

VCC_58 VCC_NCTF_26 VCC_AXG_30 VCC_AXG_80 + C151 + C158
AJ25 W37 AC25
VCC_59 VCC_NCTF_27 VCC_AXG_31
AM24 U37 W25
VCC_60 VCC_NCTF_28 VCC_AXG_32 220u/2.5V_3528 40@220u/2.5V_3528
B N36 T37 AJ24 B
VCC_61 VCC_NCTF_29 VCC_AXG_33
R37 AH24
VCC_NCTF_30 VCC_AXG_34
VCC_NCTF_31 AT35 AG24 VCC_AXG_35
AR35 AE24
VCC_NCTF_32 VCC_AXG_36
VCC_NCTF_33
U35 AD24
VCC_AXG_37 Close to GMCH
VCC_NCTF_34 AT34 AC24 VCC_AXG_38
AR34 AA24
VCC_NCTF_35 VCC_AXG_39
VCC_NCTF_36 U34 Y24 VCC_AXG_40
T34 W24
VCC_NCTF_37 VCC_AXG_41
R34 AM22
VCC_NCTF_38 VCC_AXG_42
AL22 VCC_AXG_43
AJ22
VCC_AXG_44
AH22
VCC GFX
VCC_AXG_45
AG22 VCC_AXG_46
AE22
VCC_AXG_47
AD22
VCC_AXG_48
AC22
VCC_AXG_49 VCCSM_LF1
AA22 VCC_AXG_50 VCC_SM_LF1 AU45
AM21
VCC SM LF BF52 VCCSM_LF2
VCC_AXG_51 VCC_SM_LF2 VCCSM_LF3
AL21 BB38
VCC_AXG_52 VCC_SM_LF3 VCCSM_LF4
AJ21 VCC_AXG_53 VCC_SM_LF4 BA19
AH21 BE9 VCCSM_LF5
+1.05VGFX_CORE_INT VCC_AXG_54 VCC_SM_LF5 VCCSM_LF6
AD21 AU9
VCC_AXG_55 VCC_SM_LF6 VCCSM_LF7
AC21 AL9
VCC_AXG_56 VCC_SM_LF7
AA21
CANTIGASFF_1p0 VCC_AXG_57
Y21
R61 VCC_AXG_58 C119 C120 C121 C156 C202 C231 C229
W21
VCC_AXG_59
AM16 VCC_AXG_60
10/F_6 AL16 0.1u/10V_4 0.1u/10V_4 0.22u/10V_4 0.22u/10V_4 0.47u/6.3V_4 1u/10V_6 1u/10V_6
VCC_AXG_61

VCC_AXG_SENSE AG13
[30] VCC_AXG_SENSE VCC_AXG_SENSE
VSS_AXG_SENSE AE13
[30] VSS_AXG_SENSE VSS_AXG_SENSE
A A

R39

10/F_6

CANTIGASFF_1p0

UMA: Places R721, R726 to 10 ohm.

PROJECT : BU3
Quanta Computer Inc.
Size Document Number Rev
Custom D3B
GANTIGA VCC/NCTF(4/6)
NB7
Date: Monday, August 10, 2009 Sheet 8 of 34
5 4 3 2 1
 5 4 3 2 1

C2A +3V_A_CRT_DAC
U23
[19,22,27,28,29,31] MAINON 1 4
SHDN VO
+3V +3V_A_CRT_DAC +5VPCU 2
C2A GND
L7 BLM18PG181SN1D_6 3 5
+3V_A_CRT_DAC VIN SET +1.05V_VCCP_GMCH +1.05V
C389 73mA(20mils) *G913C 852mA(50mils) R41 *short_8
10u/6.3V_8
C145 C115 C122 C138
C182 C191 + C113
+1.05V 0.47u/6.3V_4 2.2u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6
D 0.1u/10V_4 0.01u/25V_4 *220u/2.5V_3528 F3B D
L17 10uh_8 +1.05VM_DPLLA

+3V
+ C228 C224
U15H
79mA(20mils) +3V_TV_DAC R91 *short_6
220u/2.5V_3528 0.1u/10V_4
C2A 5mA(10mils) C177 C171 F3B
R13
+1.05V VTT_1 0.01u/25V_4 0.1u/10V_4
T12
VTT_2
J31 R11
L18 10uh_8 +1.05VM_DPLLB C187 C183 C190 VCCA_CRT_DAC VTT_3
T10
VTT_4
R9
22u/6.3V_8 0.1u/10V_4 0.01u/25V_4 VTT_5 +1.5V
T8
+ C232 C227 VTT_6
L31
VCCA_DAC_BG VTT_7
R7 50mA(15mils)

CRT
M33 T6 +1.5V_VCC_HDA R105 HM@0_6
220u/2.5V_3528 0.1u/10V_4 VSSA_DAC_BG VTT_8
R5
VTT_9
VTT_10
T4
C199
FOR IHDMI HDA I/F only
64mA(20mils) VTT_11
R3
J45 T2
+1.05V VCCA_DPLLA VTT_12 [email protected]/10V_4
F3B 64mA(20mils) VTT_13
R1

VTT
L49
VCCA_DPLLB
24mA(20mils)

PLL
R48 *short_6 +1.05VM_HPLL AF10
VCCA_HPLL +1.5V
139.2mA(20mils) L8
C116 C139
AE1
VCCA_MPLL VCCA_TV_DAC
K30 2.7mA(15mils) +1.5V_QDAC

TV
100mA(20mils) BLM18PG181SN1D_6
4.7u/6.3V_6 0.1u/10V_4 C194 C193

A PEG A LVDS
C214 1000p/50V_4 +1.8VSUS_TXLVDS U43 +1.5V_TVDAC R284 *short_6
VCCA_LVDS1 0.01u/25V_4 0.1u/10V_4
U41 A31
VCCA_LVDS2 VCC_HDA F3B

D TV/CRT HDA
V44 C346 C347
C
L4 BLM18PG181SN1D_6 +1.05VM_MPLL +1.5V VSSA_LVDS C
414uA(10mils) 0.01u/25V_4 0.1u/10V_4
N34
C131 +1.5V_VCCA_PEG_BG VCCD_QDAC
R49
AJ43
VCCA_PEG_BG 35mA(15mils)
N32
0.1u/10V_4 C215 +1.05VM_PEGPLL VCCD_TVDAC
*0.5/F_4 +1.05V
C108 0.1u/10V_4
+1.05VM_MPLL_RC
AG43
VCCA_PEG_PLL 324mA(30mils) +1.05VM_AXF R62 *short_8

*22u/6.3V_8 AW24
VCCA_SM_1
C150 C144 F3B
AU24
AW22
AU22
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
POWER 1u/6.3V_4 *10u/6.3V_6

AU21
+1.05V VCCA_SM_5 +1.5VSUS_GMCH
AW20
VCCA_SM_6 L6
R59 *short_8+1.05VM_A_SM
720mA(40mils) AU19
VCCA_SM_7 +1.5VSUS_VCC_SM_CK
AW18
VCCA_SM_8

A SM
AU18 DDR3-800 143.75mA 1uh_8
F3B +
C135 C153 C162 C164 AW16
VCCA_SM_9
VCCA_SM_10 DDR3-1066 149.5mA
AU16 R71
*100u/6.3V_3528 10u/6.3V_8 4.7u/6.3V_6 1u/6.3V_4 VCCA_SM_11 C152
AT16 (20mils)
VCCA_SM_12 1/F_4
AR16
VCCA_SM_13 0.1u/10V_4
AU15
VCCA_SM_14 C148
AT15
VCCA_SM_15 +1.5VSUS_SMCK_RC
AR15
VCCA_SM_16
AW14 M25
+1.05V F3B VCCA_SM_17 VCC_AXF_1
VCC_AXF_2
N24 10u/6.3V_8
+1.05V

AXF
R112 *short_6+1.05VM_A_SM_CK
26mA(20mils) AT24
VCCA_SM_NCTF_1 VCC_AXF_3
M23
AR24
VCCA_SM_NCTF_2
AT22
VCCA_SM_NCTF_3 +1.8V
AR22

2
C211 C181 C174 VCCA_SM_NCTF_4 L9
AT21
VCCA_SM_NCTF_5 80mA(20mils) +1.8VSUS_TXLVDS D18
B AR21 BK24 B
10u/6.3V_8 *2.2u/6.3V_6 0.1u/10V_4 VCCA_SM_NCTF_6 VCC_SM_CK_1 0.1uh_8
AT19 BL23
VCCA_SM_NCTF_7 VCC_SM_CK_2

SM CK
AR19 BJ23
VCCA_SM_NCTF_8 VCC_SM_CK_3 C203 C206 CH751H-40PT
AT18 BK22

1
VCCA_SM_NCTF_9 VCC_SM_CK_4
AR18
VCCA_SM_NCTF_10 1000p/50V_4 10u/6.3V_8

T41 R286 10_4 +1.05V_SD

VCC_TX_LVDS
+1.05V
AU27
VCCA_SM_CK_4 105.3mA(20mils) +3V_VCC_HV R288 *short_6
AU28 C33 +3V
VCCA_SM_CK_3 VCC_HV_1
L5 BLM18PG181SN1D_6 +1.05VM_MCH_PLL2
157.2mA(20mils) AU29
VCCA_SM_CK_2 VCC_HV_2
A33
C349
AU31
VCCA_SM_CK_1 F3B
HV
AT31
VCCA_SM_CK_NCTF_1 0.1u/10V_4
AR31
C118 VCCA_SM_CK_NCTF_2
AT29 AB44
+1.05V +1.05VM_PEGPLL VCCA_SM_CK_NCTF_3 VCC_PEG_1 +1.05V_VCC_PEG +1.05V
AR29 Y44
0.1u/10V_4 VCCA_SM_CK_NCTF_4 VCC_PEG_2
AT28
VCCA_SM_CK_NCTF_5 VCC_PEG_3
AC43 1.782A(100mils)
PEG
L10 BLM18PG181SN1D_6 AR28 AA43 R131 *short_8
VCCA_SM_CK_NCTF_6 VCC_PEG_4
AT27
VCCA_SM_CK_NCTF_7 +1.05V_VCC_PEG
R126 C218
AR27
VCCA_SM_CK_NCTF_8 456mA(30mils) C222 C244 F3B
AM44 +1.05V_VCC_DMI R130 *short_8 + C247
1/F_4 0.1u/10V_4 VCC_DMI_1 4.7u/6.3V_6 10u/6.3V_8
AN43
C246 VCC_DMI_2 C216 *220u/2.5V_3528
AL43
VCC_DMI_3 F3B
DMI

+1.05VM_PEGPLL_RC AH12
VCCD_HPLL 0.1u/10V_4
10u/6.3V_8
50mA(20mils)
AE43
VCCD_PEG_PLL
+1.8V F3B 30mA(20mils) VTTLF1
K14 +VTTLF_CAP1
VTTLF

M46 Y12 +VTTLF_CAP2

R111 *short_6+1.8VSUS_DLVDS VCCD_LVDS_1 VTTLF2 +VTTLF_CAP3
L45 P2
LVDS

VCCD_LVDS_2 VTTLF3
C117 C146 C142
A A
C220
CANTIGASFF_1p0 0.47u/6.3V_4 0.47u/6.3V_4 0.47u/6.3V_4
1u/6.3V_4

PROJECT : BU3
Quanta Computer Inc.
Size Document Number Rev
Custom D3B
GANTIGA POWER(5/6)
NB7
Date: Monday, August 10, 2009 Sheet 9 of 34
5 4 3 2 1
 5 4 3 2 1

U15J
U15I
AN25 VSS_199 VSS_300 AM8
BA55 VSS_1 VSS_100 C43 AG25 VSS_200 VSS_301 AK8
AU55 VSS_2 VSS_101 A43 AE25 VSS_201 VSS_302 AH8
AN55 VSS_3 VSS_102 BD42 AA25 VSS_202 VSS_303 AF8
AJ55 VSS_4 VSS_103 H42 Y25 VSS_203 VSS_304 AD8
AE55 VSS_5 VSS_104 BG41 E25 VSS_204 VSS_305 AB8
AA55 VSS_6 VSS_105 AY41 A25 VSS_205 VSS_306 Y8
U55 VSS_7 VSS_106 AU41 BD24 VSS_206 VSS_307 V8
D N55 AM41 AN24 P8 D
VSS_8 VSS_107 VSS_207 VSS_308
BD54 VSS_9 VSS_108 AL41 AL24 VSS_208 VSS_309 M8
BG53 VSS_10 VSS_109 AG41 H24 VSS_209 VSS_310 K8
AJ53 VSS_11 VSS_110 AE41 BG23 VSS_210 VSS_311 H8
AE53 VSS_12 VSS_111 AA41 AY23 VSS_211 VSS_312 BJ7
AA53 VSS_13 VSS_112 R41 E23 VSS_212 VSS_313 E7
U53 VSS_14 VSS_113 M41 BD22 VSS_213 VSS_314 BF6
N53 E41 BB22 BC5
VSS_15 VSS_114 VSS_214 VSS_315
J53 VSS_16 VSS_115 BD40 AN22 VSS_215 VSS_316 BA5
G53 AU40 Y22 AW5
VSS_17 VSS_116 VSS_216 VSS_317
E53 VSS_18 VSS_117 AR40 W22 VSS_217 VSS_318 AU5
K52 VSS_19 VSS_118 AN40 H22 VSS_218 VSS_319 AR5
BG51 W40 BL21 AN5
VSS_20 VSS_119 VSS_219 VSS_320
BA51 VSS_21 VSS_120 U40 BG21 VSS_220 VSS_321 AL5
AW51 T40 AY21 AJ5
VSS_22 VSS_121 VSS_221 VSS_322
AU51 R40 AN21 AG5
VSS_23 VSS_122 VSS_222 VSS_323
AR51 VSS_24 VSS_123 K40 AG21 VSS_223 VSS_324 AE5
AN51 H40 AE21 AC5
VSS_25 VSS_124 VSS_224 VSS_325
AL51 BL39 M21 AA5
VSS_26 VSS_125 VSS_225 VSS_326
AJ51 VSS_27 VSS_126 BG39 E21 VSS_226 VSS_327 W5
AG51 BA39 A21 U5
VSS_28 VSS_127 VSS_227 VSS_328
AE51 VSS_29 VSS_128 E39 BD20 VSS_228 VSS_329 N5
AC51 C39 H20 L5
AA51
W51
VSS_30
VSS_31
VSS_32
VSS_129
VSS_130
VSS_131
A39
BD38
BG19
AY19
VSS_229
VSS_230
VSS_231
VSS VSS_330
VSS_331
VSS_332
J5
G5
U51 AU38 M19 C5
R51
N51
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
H38
BG37
E19
BD18
VSS_232
VSS_233
VSS_234
VSS_333
VSS_334
VSS_335
BH4
BE3
L51 AU37 N18 U3
VSS_36 VSS_135 VSS_235 VSS_336
J51 M37 H18 E3
C VSS_37 VSS_136 VSS_236 VSS_337 C
G51 VSS_38 VSS_137 E37 BL17 VSS_237 VSS_338 BC1
C51 BD36 BG17 AW1
VSS_39 VSS_138 VSS_238 VSS_339
BK50 VSS_40 VSS_139 AW36 AY17 VSS_239 VSS_340 AR1
AM50 VSS_41 VSS_140 H36 M17 VSS_240 VSS_341 AL1
K50 VSS_42 VSS_141 BL35 E17 VSS_241 VSS_342 AG1
BG49 VSS_43 VSS_142 BG35 A17 VSS_242 VSS_343 AC1
E49 AY35 BD16 W1
VSS_44 VSS_143 VSS_243 VSS_344
C49 AU35 AN16 N1
VSS_45 VSS_144 VSS_244 VSS_345
BD48 AL35 AG16 J1
VSS_46 VSS_145 VSS_245 VSS_346
BB48 AG35 AE16 AU43
VSS_47 VSS_146 VSS_246 VSS_347
AY48 AE35 Y16 BB42
VSS_48 VSS_147 VSS_247 VSS_348
AV48 AA35 W16 AW38
VSS_49 VSS_148 VSS_248 VSS_349
AT48 Y35 N16 BA35
VSS_50 VSS_149 VSS_249 VSS_350
AP48 VSS_51 VSS_150 M35 H16 VSS_250 VSS_351 L29
AM48 VSS_52 VSS_151 E35 BG15 VSS_251 VSS_352 N28
AK48 A35 AY15 N22
VSS_53 VSS_152 VSS_252 VSS_353
AH48 BD34 AN15 N20
VSS_54 VSS_153 VSS_253 VSS_354
AF48 AU34 AD15 N14
VSS_55 VSS_154 VSS_254 VSS_355
AD48 AN34 AC15 AL13
VSS_56 VSS_155 VSS_255 VSS_356
AB48 VSS_57 VSS_156 H34 R15 VSS_256 VSS_357 B10
Y48 VSS_58 VSS_157 BL33 M15 VSS_257 VSS_358 AN13
V48 BG33 E15
VSS_59 VSS_158 VSS_258
T48 AY33 BD14 N42
VSS_60 VSS_159 VSS_259 VSS_359
P48 VSS_61 VSS_160 E33 H14 VSS_260 VSS_360 N40
M48 VSS_62 VSS_161 BD32 BL13 VSS_261 VSS_361 N38
K48 VSS_63 VSS_162 AU32 BG13 VSS_262 VSS_362 M39
H48 AN32 AY13
VSS_64 VSS_163 VSS_263
BL47 AG32 AU13
VSS_65 VSS_164 VSS_264
BG47 AC32 AR13 AJ38
VSS_66 VSS_165 VSS_265 VSS_NCTF_1
E47 Y32 AJ13 AH38
B VSS_67 VSS_166 VSS_266 VSS_NCTF_2 B
C47 H32 AC13 AD38
VSS_68 VSS_167 VSS_267 VSS_NCTF_3
A47 B32 AA13 AC38
VSS_69 VSS_168 VSS_268 VSS_NCTF_4
BD46 BJ31 W13 T35
VSS_70 VSS_169 VSS_269 VSS_NCTF_5
AY46 BG31 U13 R35
VSS_71 VSS_170 VSS_270 VSS_NCTF_6

VSS NCTF
AM46 VSS_72 VSS_171 AY31 M13 VSS_271 VSS_NCTF_7 AT32
AK46 AN31 E13 AR32
VSS_73 VSS_172 VSS_272 VSS_NCTF_8
AH46 M31 A13 U32
VSS_74 VSS_173 VSS_273 VSS_NCTF_9
BG45 VSS_75 VSS_174 E31 BD12 VSS_274 VSS_NCTF_10 R32
AE45 N30 AV12 T28
VSS_76 VSS_175 VSS_275 VSS_NCTF_11
AC45 H30 AP12 R28
VSS_77 VSS_176 VSS_276 VSS_NCTF_12
AA45 AN29 AM12 AT25
VSS_78 VSS_177 VSS_277 VSS_NCTF_13
W45 VSS_79 VSS_178 AJ29 AK12 VSS_278 VSS_NCTF_14 AR25
R45 VSS_80 VSS_179 M29 AB12 VSS_279 VSS_NCTF_15 T24
N45 A29 V12 R24
VSS_81 VSS_180 VSS_280 VSS_NCTF_16
E45 AW28 P12 AN19
VSS_82 VSS_181 VSS_281 VSS_NCTF_17
BD44 VSS_83 VSS_182 AN28 H12 VSS_282 VSS_NCTF_18 AJ19
BB44 AD28 BG11 AA19
VSS_84 VSS_183 VSS_283 VSS_NCTF_19
AV44 VSS_85 VSS_184 AC28 AG11 VSS_284 VSS_NCTF_20 Y19
AK44 VSS_86 VSS_185 Y28 E11 VSS_285 VSS_NCTF_21 T19
AH44 W28 BD10 R19
VSS_87 VSS_186 VSS_286 VSS_NCTF_22
AF44 VSS_88 VSS_187 H28 AY10 VSS_287 VSS_NCTF_23 AN18
AD44 VSS_89 VSS_188 F28 AP10 VSS_288
K44 AN27 H10
VSS_90 VSS_189 VSS_289
H44 AJ27 BL9
VSS_91 VSS_190 VSS_290
BL43 M27 BG9
VSS_92 VSS_191 VSS_291
BG43 BF26 E9
VSS_93 VSS_192 VSS_292
AY43 BD26 A9 BL55
VSS_94 VSS_193 VSS_293 VSS_SCB_1
AR43 VSS_95 VSS_194 N26 BD8 VSS_294 VSS SCB VSS_SCB_2 BL1
W43 H26 BB8 A55
VSS_96 VSS_195 VSS_295 VSS_SCB_3
R43 VSS_97 VSS_196 BJ25 AY8 VSS_296 VSS_SCB_4 D1
A M43 AY25 AV8 B55 A
VSS_98 VSS_197 VSS_297 VSS_SCB_5
E43 AU25 AT8 B2
VSS_99 VSS_198 VSS_298 VSS_SCB_6
AP8 A4
VSS_299 VSS_SCB_7
CANTIGASFF_1p0

CANTIGASFF_1p0
PROJECT : BU3
Quanta Computer Inc.
Size Document Number Rev
Custom D3B
GANTIGA VSS(6/6)
NB7
Date: Monday, August 10, 2009 Sheet 10 of 34
5 4 3 2 1
 5 4 3 2 1

North Bridge Strap Pin Configuration Table

(See DG 2.0 P306 Table 187)

(See NB EDS 1.0 P187 Table 74)

Pin Name Strap description Configuration PU<4.02K> PD <2.21K> Note

D D

CFG[2:0] FSB Frequency Select [000]= FSB 1066MHz [010] = FSB 800MHz [011] = FSB 667MHz See Page 2 FSB selection table

CFG[4:3] Reserved

CFG5 DMI X2 Select 0 = DMI X2 R97 *2.2K_4

[6] MCH_CFG5
1 = DMI X4(Default)

iTPM Host Interface 0 = iTPM Host Interface is enabled R70 *2.2K/F_4

CFG6 [6] MCH_CFG6
1 = iTPM Host Interface is disabled(Default)

0 = AMT Firmware will use TLS cipher suite with no confidentiality R72 *2.2K/F_4
CFG7 ME TLS Confidentiality [6] MCH_CFG7
1 = AMT Firmware will use TLS cipher suite with confidentiality(Default)

CFG8 Reserved

CFG9 PCI Express Graphics 0 = Reverse Lanes R73 *2.2K_4

[6] MCH_CFG9
Lane Reversal 1 = Normal operation(Default)

C CFG10 PCIE Loopback enable 0 = Enabled R75 *2.2K/F_4 C

[6] MCH_CFG10
1 = Disabled (Default)

CFG11 Reserved

ALLZ 0 = ALLZ mode enable R64 *2.2K/F_4

CFG12 [6] MCH_CFG12
1 = disable(Default)

XOR 0 = XOR mode enable R77 *2.2K/F_4

CFG13 [6] MCH_CFG13
1 = disable(Default)

CFG[15:14] Reserved

CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable R81 *2.2K_4

[6] MCH_CFG16
1 = Dynamic ODT Enable(Default)

CFG[18:17] Reserved

DMI Lane Reversal 0 = Normal (Default) R93 *4.02K/F_4

CFG19 [6] MCH_CFG19 +3V
B
1 = Lanes Reversed B

0 = Only Digital Display port (SDVO/DP/iHDMI) or PCIE is

Digital Display Port
operational (Default) R92 *4.02K/F_4
CFG20 (SDVO/DP/iHDMI) [6] MCH_CFG20 +3V
1 = Digital Display port (SDVO/DP/iHDMI) and PCIE are operating
Concurrent with PCIE
simultaneously via PEG port

SDVO Present 0 = No SDVO/HDMI/DP Device Present(Default) Strap on P18

SDVO_CTRLDATA
1 = SDVO/HDMI/DP Device present SDVO_CTRLDATA
L_DDC_DATA Local Flat Panel(LFP) Present 0 = LFP Disable(Default) Strap on P17
1 = LFP Card Present;PCIE disable INT_LVDS_EDIDDATA
DDPC_CTRLDATA Digital Display Present 0 = Digital display(HDMI/DP) device absent(Default) R109 *1.5K/F_4
[6] DDPC_CTRLDATA +3V
1 = Digital display(HDMI/DP) device present

R114 *1.5K/F_4 +3V

[6] DDPC_CTRLCLK
Enable iTPM Table
PAGE Net Name PU & PD NOTE
A 11 A
MCH_CFG_6 PD 10K to GND NB Strap pin
13 SPI_MOSI PU 20K to +3V_S5 SB Strap pin
14 CLGPIO5 PU 10K to +3V_S5 SB Strap pin

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
NB (7/7)- STRAP PIN
Date: Monday, August 10, 2009 Sheet 11 of 34
5 4 3 2 1
 1 2 3 4 5 6 7 8

RTC CRYSTAL ICH_RTCX1 F25

U20A
H3
RTCX1 FWH0/LAD0 LAD0 [20,22]
ICH_RTCX2 G25 J3
RTCX2 FWH1/LAD1 LAD1 [20,22]
K5 LAD2 [20,22]
ICH_RTCRST# FWH2/LAD2 +1.05V_ICH_IO
G24 L3 LAD3 [20,22]
ICH_SRTCRST# RTCRST# FWH3/LAD3
C24

RTC
LPC
C365 15p/50V_4 ICH_RTCX1 ICH_INTRUDER# SRTCRST#
C23 INTRUDER# FWH4/LFRAME# J2 LFRAME# [20,22]

2
1
ICH_INTVRMEN E25 H1
INTVRMEN LDRQ0# PAD T96
Y4 R311 D25 J1 LDRQ#1 [20] R174 R169 R318
LAN100_SLP LDRQ1#/GPIO23
32.768KHZ 10M_6 G22 N3 GATEA20 GATEA20 [22] *56_4 *56_4 56_4
GLAN_CLK A20GATE
AB23 H_A20M# [3]
3
4
C359 15p/50V_4 ICH_RTCX2 A20M#
D14
LAN_RSTSYNC H_DPRSTP#
A AE23 H_DPRSTP# [3,6,26] A
DPRSTP# H_DPSLP#
32.768KHZ A14 AE24

LAN / GLAN
LAN_RXD0 DPSLP# H_DPSLP# [3]
D12 LAN_RXD1
B14 AD25 H_FERR#_R R316 56_4 H_FERR# [3]
LAN_RXD2 FERR#
D13 LAN_TXD0 CPUPWRGD AE22 H_PWRGOOD [3]
C13 LAN_TXD1
A13 LAN_TXD2 IGNNE# AD23 H_IGNNE# [3]

CPU
ICH_GPIO56 D15 AE21 +1.05V_ICH_IO
GPIO56 INIT# H_INIT# [3]
AD24 H_INTR [3]
INTR RCIN#
H22 L1 RCIN# [22]
RESET JUMP GLAN_COMP

ACZ_BIT_CLK
H21

AE7
GLAN_COMPI
GLAN_COMPO
RCIN#

NMI AD21
AC21
H_NMI [3]
R159
HDA_BIT_CLK SMI# H_SMI# [3]
ACZ_SYNC AB7 56_4
[13] ACZ_SYNC HDA_SYNC
AC25 H_STPCLK# [3]
ACZ_RST# STPCLK#
An RC delay circuit with a time delay in the range AA7
HDA_RST#
of 18 ms to 25 ms should be provided AC23 H_THERMTRIP_R R163 54.9/F_4 R158 *0_4 PM_THRMTRIP# [3,6]
+VCCRTC THRMTRIP#
[21] ACZ_SDIN0_AUDIO AB6
HDA_SDIN0
[6] ICH_AZ_HDMI_SDIN1 AE6 AC22 T35
R186 20K_6 ICH_RTCRST# HDA_SDIN1 TP11
T56 AC6

IHDA
HDA_SDIN2
T60 AA5
C272 G1 HDA_SDIN3 SATA_RXN4_C
ICH_SATA_LED# SATA4RXN
AD12 T92
ACZ_SDOUT AC7 AE12 SATA_RXP4_C T93
1u/6.3V_4 *SHORT_ PAD HDA_SDOUT SATA4RXP SATA_TXN4_C
0 PCIe Lane Reversed SATA4TXN AB12 T48
AD8 AA12 SATA_TXP4_C T47
[14,20] CPUSB# HDA_DOCK_EN#/GPIO33 SATA4TXP
1 PCIe Straight(default) T55 AB8
HDA_DOCK_RST#/GPIO34
AC11 SATA_RXN5_C T51
SATA5RXN SATA_RXP5_C
[21] SATA_LED# AC9 AD11 T50
+VCCRTC SATALED# SATA5RXP SATA_TXN5_C
AB10 T53
SATA_RXN0_C SATA5TXN SATA_TXP5_C
AE14 SATA0RXN SATA5TXP AA10 T54
R181 20K_6 ICH_SRTCRST# SATA_RXP0_C AD14 SATA0RXP

SATA
SATA_TXN0_C AC15 AC16
C268 G2 SATA_TXP0_C SATA0TXN SATA_CLKN CLK_PCIE_SATA# [2]
AD15 AB16
B SATA0TXP SATA_CLKP CLK_PCIE_SATA [2] B
1u/6.3V_4 *SHORT_ PAD SATA_RXN1_C AD13 AD10
SATA_RXP1_C SATA1RXN SATARBIAS# SATABIAS R359 24.9/F_4
AC13 SATA1RXP SATARBIAS AE10
SATA_TXN1_C AA14
SATA_TXP1_C SATA1TXN
AB14
SATA1TXP
Place within 500mils of ICH9 ball
ICH9MSFF REV 1.0

+VCCRTC +3V_S5

C289 0.01u/25V_4 SATA_RXN0_C +3V

[19] SATA_RXN0
R214 10K_4 ICH_GPIO56 C285 0.01u/25V_4 SATA_RXP0_C
[19] SATA_RXP0
R195 1M_4 ICH_INTRUDER# C282 0.01u/25V_4 SATA_TXN0_C
+1.5V_PCIE_ICH [19] SATA_TXN0
C288 0.01u/25V_4 SATA_TXP0_C GATEA20 R375 8.2K_4
[19] SATA_TXP0
C294 *0.01u/25V_4 SATA_RXN1_C
[19] SATA_RXN1
R168 332K/F_4 ICH_INTVRMEN R162 24.9/F_4 GLAN_COMP C300 *0.01u/25V_4 SATA_RXP1_C RCIN# R249 10K_4
[19] SATA_RXP1
(DG 1.0 Table-292) C297 *0.01u/25V_4 SATA_TXN1_C
[19] SATA_TXN1
C301 *0.01u/25V_4 SATA_TXP1_C
[19] SATA_TXP1
Internal VRM enabled for 24.9 Ohm pull up to 1.5V for
VccSus1_05, VccSus1_5, GLAN_COMPI/O is required, no R385 *0_4 USBP11- [13]
VccCL1_5, VccLAN1_05 and matter intel LAN is used or not. R386 *0_4
VccCL1_05. C2A USBP11+ [13]

C
HD Audio Interface RTC BATTERY C

R229 HM@33_4
ICH_AZ_HDMI_SYNC [6]
ACZ_SYNC R230 33_4
ACZ_SYNC_AUDIO [21]

+3VPCU +VCCRTC
(20mils)
R241 HM@33_4
ICH_AZ_HDMI_BITCLK [6]
R238 HM@33_4
ICH_AZ_HDMI_RST# [6]
D14 CH500H-40PT (30mils)
C321 *10p/50V_4 ACZ_RST# R239 33_4
ACZ_RST#_AUDIO [21]
(20mils)
R_3VRTC D12 CH500H-40PT
ACZ_BIT_CLK R244 BK1005HM121-T(300MA,120)
BIT_CLK_AUDIO [21]
C286
C324 22p/50V_4
R222 HM@33_4 1u/10V_6
ICH_AZ_HDMI_SDOUT [6]
R216
F3B ACZ_SDOUT R223 33_4
ACZ_SDOUT_AUDIO [21]
1K_4

RTC_N02 (20mils)
1 3 R220 2K/F_4 R221 2K/F_4 (20mils) +5VPCU
Q21
South Bridge Strap Pin (1/3)

2
MMBT3904-7-F R237

6.8K/F_4
Pin Name Strap description Sampled Configuration PU/PD (20mils)

1
CN10 RTC_N03 R228 15K/F_4
0 = The Flash Descriptor Security will be overridden.
HDA_DOCK_EN/ Flash Descriptor Security 1 = The security measures defined This strap should only be enabled in manufacturing
PWROK environments using an external pull-up resistor.
GPIO33 Override Strap in the Flash Descriptor will be in effect
D D
AAA-BAT-046-K03
2
PCI Express Lane Reversal Internal PU
SATALED# PWROK
(Lanes 1-4)

ICH_TP3 HDA_SDOUT Description

XOR Chain Entrance PWROK [14] ICH_TP3
ICH_TP3 R196 *1K_4
PROJECT : BU3
0 0 RSVD
0 1 Enter XOR Chain
Quanta Computer Inc.
+1.5V_HDA_IO_ICH
XOR Chain Entrance /PCI Express*
HDA_SDOUT Port Config 1 bit 1(Port 1-4) PWROK 1 0 Normal opration(Default) R224 *1K_4 ACZ_SDOUT Size Document Number Rev
Custom D3B
ICH9-M CPU/SATA/IDE(1/4)
1 1 Set PCIE port config bit 1 NB7
Date: Monday, August 10, 2009 Sheet 12 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

ICH9
A U20B U20D A

A11 G4 REQ0# PCIE_RXN1_C T25 V25

AD0 REQ0# T83 PERN1 DMI0RXN DMI_MTX_IRX_N0 [6]
GNT0# PCIE_RXP1_C
B12 PCI E1 T24 V24

Direct Media Interface

A10
AD1
AD2
GNT0#
REQ1#/GPIO50
A9 REQ1#
T71
B1A T84
T34
PCIE_TXN1_C R24
PERP1
PETN1
DMI0RXP
DMI0TXN
U24
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
[6]
[6]
C12 E12 GNT1# T46 PCIE_TXP1_C R23 U23
AD3 GNT1#/GPIO51 T33 PETP1 DMI0TXP DMI_MRX_ITX_P0 [6]
A8 B11 REQ2#
AD4 REQ2#/GPIO52 GNT2# PCIE_RXN2_C
A12 AD5 GNT2#/GPIO53 C10 T94 T79 P25 PERN2 DMI1RXN W23 DMI_MTX_IRX_N1 [6]
E10 D6 REQ3# PCIE_RXP2_C P24 W24
C11
AD6
AD7
REQ3#/GPIO54
GNT3#/GPIO55
C6 GNT3# T63
B1A T80
T24
PCIE_TXN2_C P21
PERP2
PETN2
DMI1RXP
DMI1TXN
V21
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
[6]
[6]
B9 PCIE_TXP2_C P22 V22
D8
AD8
AD9 C/BE0# D10 D3A T26 PETP2 DMI1TXP DMI_MRX_ITX_P1 [6]
A4 A5 N23 Y24
E8
AD10 C/BE1#
E6 B1A [20] PCIE_RXN3
N24
PERN3 DMI2RXN
Y25
DMI_MTX_IRX_N2 [6]

PCI-Express
AD11 C/BE2# [20] PCIE_RXP3 PCIE_TXN3_C PERP3 DMI2RXP DMI_MTX_IRX_P2 [6]
A3 C9 C386 1 2 *[email protected]/10V_4 M21 Y21
D9
AD12
AD13
C/BE3#
IRDY#
3G CARD [20]
[20]
PCIE_TXN3
PCIE_TXP3
C382 1 2 *[email protected]/10V_4 PCIE_TXP3_C M22
PETN3
PETP3
DMI2TXN
DMI2TXP
Y22
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
[6]
[6]
C8 C3
AD14 IRDY# PCI_PAR PCIE_RXN4_C
C2 B1 T70 T82 M25 AB24 DMI_MTX_IRX_N3 [6]
AD15 PAR PCI_RST#_G PCIE_RXP4_C PERN4 DMI3RXN
D7 T3 M24 AB25
B3
AD16
AD17
PCIRST#
DEVSEL#
A7 DEVSEL# T66 B1A T86
T32
PCIE_TXN4_C L24
PERP4
PETN4
DMI3RXP
DMI3TXN
AA23
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
[6]
[6]
D11 D4 PERR# Place TX DC blocking caps close ICH9. PCIE_TXP4_C L23 AA24
AD18 PERR# T37 PETP4 DMI3TXP DMI_MRX_ITX_P3 [6]
B6 C5 LOCK#
AD19 PLOCK# SERR#
D5 H5 [23] PCIE_RXN5 K24 T21 CLK_PCIE_ICH# [2]
AD20 SERR# STOP# PERN5 DMI_CLKN
D3 AD21 STOP# A6 [23] PCIE_RXP5 K25 PERP5 DMI_CLKP T22 CLK_PCIE_ICH [2]
F4 A2 TRDY# C362 1 2 0.1u/10V_4 PCIE_TXN5_C K21
E3
AD22
AD23
TRDY#
FRAME# B8 FRAME# LAN [23]
[23]
PCIE_TXN5
PCIE_TXP5
C363 1 2 0.1u/10V_4 PCIE_TXP5_C K22
PETN5
PETP5 DMI_ZCOMP AB21
DMI_COMP
R165 24.9/F_4 Place within 500mils of ICH9
E4 AD24 DMI_IRCOMP AB22 1 2 +1.5V_PCIE_ICH
B2 A21 PCI_PLTRST# H24
AD25 PLTRST# [20] PCIE_RXN6 PERN6/GLAN_RXN
C4 B5 CLK_PCI_ICH H25 AE2 USBP0- [21]
AD26 PCICLK CLK_PCI_ICH [2] [20] PCIE_RXP6 PCIE_TXN6_C PERP6/GLAN_RXP USBP0N
C1 T1 C360 1 2 0.1u/10V_4 J24 AD1 USB
D1
AD27
AD28
PME# T69 WLAN [20]
[20]
PCIE_TXN6
PCIE_TXP6
C361 1 2 0.1u/10V_4 PCIE_TXP6_C J23
PETN6/GLAN_TXN
PETP6/GLAN_TXP
USBP0P
USBP1N
AD3
USBP0+
USBP1-
[21]
[21]
E2 AD29 USBP1P AD4 USBP1+ [21] USB
J4 T87 E24 AC2 USBP2- [21]
AD30 SPI_CLK USBP2N
H2
AD31 T30 E23
SPI_CS0# USBP2P
AC3 USBP2+ [21] BT
SPI_CS1# F23 AC5 USBP3- [17]
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
Interrupt I/F USBP3P
AB4 USBP3+ [17] CCD
B
INTA#_R F1 G3 INTE# SPI_MOSI F22 AB2 USBP4- [21] B
PIRQA# PIRQE#/GPIO2 SPI_MOSI USBP4N

SPI
INTB#_R F5 G1 INTF# G23 AB1 USBP4+ [21] Cardreader for 13"
PIRQB# PIRQF#/GPIO3 T28 SPI_MISO USBP4P
INTC#_R F2 F3 INTG# AA3 USBP5-
PIRQC# PIRQG#/GPIO4 USBP5N T100
INTD#_R C7
PIRQD# PIRQH#/GPIO5
H4 INTH#
[21,22] USBOC0#
USBOC0#
USBOC1#
P4
N4
OC0#/GPIO59 USBP5P
AA2
Y1
USBP5+
T99
USBP6- [20]
F3B
[21,22] USBOC1# OC1#/GPIO40 USBP6N
ICH9MSFF REV 1.0 USBOC2# N1 Y2 3G
USBOC3# P5
OC2#/GPIO41 USB USBP6P
W2 USBP7-_R
USBP6+ [20]
R388 *3G@0_4
USBOC4# P1
OC3#/GPIO42
OC4#/GPIO43
USBP7N
USBP7P W3 USBP7+_R R389 *3G@0_4
USBP7- [20]
USBP7+ [20] B1A D3A
SIM
USBOC5# P2 V1 USBP8-
OC5#/GPIO29 USBP8N T97
USBOC6# M3 V2 USBP8+
OC6#/GPIO30 USBP8P T95
USBOC7# M2 Y5 USBP9- [18] USB&SLEEP CHARAGE
USBOC8# OC7#/GPIO31 USBP9N
P3 Y4 USBP9+ [18]
USBOC9# OC8#/GPIO44 USBP9P
[18,22] USBOC9# R1 OC9#/GPIO45 USBP10N U3 USBP10- [20]
USBOC10# R4 U2 USBP10+ [20] WLAN
USBOC11# OC10#/GPIO46 USBP10P
R2 OC11#/GPIO47 USBP11N V4 USBP11- [12]
USBRBIAS AE5
USBP11P V5 USBP11+ [12] USB-ODD C2A
PCI_PLTRST# USBRBIAS
PCI_PLTRST# [6] AD5
USBRBIAS#

2
ICH9MSFF REV 1.0
R226
+3V_S5 22.6/F_4

1
C303

0.1u/10V_4
5

2
4 PLTRST# [20,21,22,23]
1
R202
R201
3

U12
C 100K_4 *100K_6 C
TC7SH08FU(F)

South Bridge Strap Pin (2/3) PCI PULL-UP USBOC# PULL-UP

Pin Name Strap description Sampled Configuration PU/PD RP4
+3V

6 5
+1.5V_HDA_IO_ICH
PCI Express Port 0 = Default 7 4 REQ2#
HDA_SYNC PWROK 8 3 REQ1#
Config 1 bit 0 (Port 1-4) 1 = Setting bit 0 R231 *1K_4 REQ3# 9 2 REQ0# +3V_S5
ACZ_SYNC [12] RP5
+3V 10 1 IRDY#
USBOC7# 6 5
PCI Express Port 0 = Setting bit 2 8.2KX8 USBOC4# 7 4 USBOC3#
GNT2# / GPIO53 PWROK GNT2# R370 *1K_4 +3V_S5 USBOC5# 8 3 USBOC1#
Config 2 bit 2 (Port 5-6) 1 = Default USBOC6# 9 2 USBOC2#
10 1 USBOC0#

GNT1# / GPIO51 ESI Strap(Server Only) PWROK 0 = DMI for ESI-compatible 10KX8 +3V_S5
1 = Default +3V
RP18
RP20
6 5 USBOC10# 8 7
0 = "top-block swap" mode DEVSEL# 7 4 SERR# USBOC11# 6 5
GNT3# / GPIO55 Top-Block Swap Override PWROK GNT3# R218 *1K_4 PERR# 8 3 STOP# USBOC8# 4 3
1 = Default LOCK# 9 2 TRDY# USBOC9# 2 1
D
+3V 10 1 FRAME# D
10KX4
0 = INT TPM disable(Default) 8.2KX8
SPI_MOSI Integrated TPM Enable CLPWROK SPI_MOSI R314 *20K_4
1 = INT TPM enable
+3V
Boot Location RP19
PCI_GNT#0 SPI_CS#1
GNT0# Boot BIOS Selection 0 PWROK GNT0# R246 *1K_4 INTF# 6 5

0 1 SPI(Default)
INTE#
INTH#
7
8
4
3
INTC#_R
INTA#_R PROJECT : BU3
INTG# 9
10
2
1
INTB#_R
INTD#_R
Quanta Computer Inc.
+3V
SPI_CS1# / 1 0 PCI
Boot BIOS Selection 1 CLPWROK SPI_CS1# R164 *1K_4 8.2KX8 Size Document Number Rev
GPIO58 / CLGPIO6 Custom ICH9-M (USB/PCIE/DMI) D3B
NB7
Date: Monday, August 10, 2009 Sheet 13 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+3V_S5

R358

R369
2.2K_4

2.2K_4
SCLK

SDATA
ICH9 U20C
[2,23] SCLK C18 SMBCLK AE19 BOARD_ID3
R171 10K_4 USB_BUS_SW3 SATA0GP/GPIO21 BOARD_ID2
[2,23] SDATA C15 SMBDATA SATA1GP/GPIO19 AA18 T91
USB_BUS_SW3 B21 LINKALERT#/GPIO60/CLGPIO4 AE20 BOARD_ID9

SATA
[18] USB_BUS_SW3 SATA4GP/GPIO36

GPIO
SMB
R354 10K_4 SMB_CLK_ME SMB_CLK_ME E18 SMLINK0 AA20 ICH_GPIO37
SMB_DATA_ME SATA5GP/GPIO37
A24 SMLINK1
R346 10K_4 SMB_DATA_ME K1 CLK_ICH_14M
CLK14 CLK_ICH_14M [2]
RI# C20 AB5 CLK_ICH_48M

Clocks
RI# CLK48 CLK_ICH_48M [2]
R353 10K_4 RI#
A RSV_LPCPD# ICH_SUSCLK A
T59 T5 SUS_STAT#/LPCPD# SUSCLK R3 T64
R332 10K_4 ITP_DBRESET# ITP_DBRESET# C25
[3] ITP_DBRESET# SYS_RESET#
SLP_S3# D18 SUSB# [22]
R197 10K_4 SMB_ALERT# L2 B20
[6] PM_SYNC# PMSYNC#/GPIO0 SLP_S4# SUSC# [22]
SLP_S5# D16 T42
R200 10K_4 PCIE_WAKE# SMB_ALERT# A23 SMBALERT#/GPIO11
S4_STATE#/GPIO26 E14 T52
R368 8.2K_4 PM_BATLOW# H_STP_PCI# B15
[2] H_STP_PCI# STP_PCI#/GPIO15
H_STP_CPU# ICH_PWRGD

SYS GPIO
[2] H_STP_CPU# A20 STP_CPU#/GPIO25 PW ROK D23
R376 *10K_4 DNBSWON#
CLKRUN# M5 M1 DPRSLPVR
[22] CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 DPRSLPVR [6,26]
R194 *10K_4 USB_BUS_SW1
PCIE_WAKE# PM_BATLOW#

Power MGT
[20,23] PCIE_WAKE# C21 W AKE# BATLOW # C16
R363 10K_4 USB_BUS_SW0 SERIRQ L4
[20,22] SERIRQ THERM_ALERT# SERIRQ
[3] THERM_ALERT# AD20 THRM# PW RBTN# U4 DNBSWON# [22]
R210 *10K_4 HDPACT
VR_PWRGD_CLKEN B24 D22 PM_LAN_ENABLE_R R350 *0_4 PM_RSMRST#_R
R382 10K_4 SCI# VRMPW RGD LAN_RST#
B1A T41
A19 TP12 RSMRST# D19 PM_RSMRST#_R

KBSMI#_ICH AE16 U1
GPIO1 CK_PW RGD CLK_PWRGD [2]
+3V AE18 GPIO6 MPWROK
AD18 GPIO7 CLPW ROK T4 MPWROK [6,22]
SCI# B25
[22] SCI# GPIO8
R366 *10K_4 H_STP_PCI# BOARD_ID1 C14 B23 T29
T45 GPIO12 SLP_M#
[18] USB_BUS_SW2 D20 GPIO13
R356 *10K_4 H_STP_CPU# BOARD_ID0 AE17 C22
T40 GPIO17 CL_CLK0 CL_CLK0 [6]
BOARD_ID6 K3 A18
T98 GPIO18 CL_CLK1 CL_CLK1 [20]
R371 8.2K_4 CLKRUN# AC8
BOARD_ID4 GPIO20
B [18] BOARD_ID4 AC19 SCLOCK/GPIO22 CL_DATA0 E22 CL_DATA0 [6] B
R372 10K_4 SERIRQ

Controller Link
D17 B18

GPIO
GPIO27 CL_DATA1 CL_DATA1 [20]
E20 GPIO28
R178 8.2K_4 THERM_ALERT# ICH_GPIO35 M4 F21 CL_VREF0_SB
ICH_GPIO38 SATACLKREQ#/GPIO35 CL_VREF0 CL_VREF1_SB
AB18 SLOAD/GPIO38 CL_VREF1 A17
R347 10K_4 KBSMI#_ICH HDPLOC AC18
[19] HDPLOC SDATAOUT0/GPIO39
BOARD_ID7 AB19 C17
T89 SDATAOUT1/GPIO48 CL_RST0# ICH_CL_RST0# [6]
R336 *10K_4 SCI# DMI_TERM_SEL AC20 B17
GPIO49 CL_RST1# ICH_CL_RST1# [20]
CLGPIO5 A16
R374 10K_4 ICH_GPIO35 GPIO57/CLGPIO5 USB_BUS_SW1
MEM_LED/GPIO24 A22 USB_BUS_SW1 [18]
PCBEEP K4 E16 HDPACT
[21] PCBEEP SPKR GPIO10/SUS_PW R_ACK HDPACT [19]
R190 *10K_4 MCH_ICH_SYNC# MCH_ICH_SYNC# AB20 A15 USB_BUS_SW0
[6] MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT USB_BUS_SW0 [18]
C19 D21 HDPINT
[12] ICH_TP3 TP3 W OL_EN/GPIO9 HDPINT [19]

MISC
R179 10K_4 ICH_GPIO37 T39 AB17 TP8
T43 AC17 TP9
R51 10K_4 HDPLOC T90 AD17 TP10
R352 10K_4 ICH_GPIO38 ICH9MSFF REV 1.0

R351 *short_4PM_LAN_ENABLE_R

F3B
C2A C2A E3A+3V +3V
R167 *0_4

+3V_S5 +3V_S5 +3V_S5 +3V +3V +3V +3V

2

C C278 0.1u/10V_4 C
1

R365 R156 R191 R173 R391 R166

R343 R360 10K_4 GS@10K_4 *10K_4 47K_4 PM_RSMRST#_R 3 1 RSMRST# [22]
*10K_4 *10K_4 *3.24K/F_6 3.24K/F_6
Q19 MMBT3906_NL
1

+3V_S5
2

2
HDPINT CLGPIO5 CL_VREF1_SB CL_VREF0_SB BOARD_ID4 BOARD_ID9 BOARD_ID3 CPUSB# U11 R177
CPUSB# [12,20]
1 5 10K_4 R170 4.7K_4
1

R362 C378 R160 C260 VR_PWRGD_CK410# 2

[26] VR_PWRGD_CK410#
1

2
R345 R361 3 4 VR_PWRGD_CLKEN D11
R192 R180 R392
*10K_4 100K_4 *453/F_4 *0.47u_10V_4 453/F_4 0.1u/10V_4 *10K_4 *GS@10K_4 10K_4 74LVC1G04GW 3 BAV99
2

10 R198
2

10
100K_4

1
Board ID ID9 ID4 CPUSB# ID3

2
W/ G-SENSOR H
W/O G-SENSOR L D13
3 BAV99
W/ HDMI L
W/O HDMI H
R215

1
W/ 3G H 2.2K_4
W/O 3G L
South Bridge Strap Pin (3/3)
+3V_S5
FOR 11" H
Pin Name Strap description Sampled Configuration PU/PD FOR 13" L C326 0.1u/10V_4

D D

GPIO20 Reserved PWROK

5
DELAY_VR_PWRGOOD 1
[3,6,26] DELAY_VR_PWRGOOD
4 ICH_PWRGD

PCBEEP No Reboot PWROK

0 = Default PCBEEP R245 *1K_4 +3V
MPWROK 2
U13 PROJECT : BU3
3

1 = No Reboot mode R242 Quanta Computer Inc.

TC7SH08FU(F)
R243 100K_4 10K_4
0 = for desktop applications Size Document Number Rev
DMI Termination 1 = for mobile applications
GPIO49 PWROK DMI_TERM_SEL R172 *1K_4 Custom
ICH9-M (PM,GPIO,SMB) D3B
Voltage Internal PU NB7
Date: Monday, August 10, 2009 Sheet 14 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

F3B U20E

+5V +3V +VCCRTC 1.634A (80mils) B4

B7
VSS[001] VSS[107]
U5
U10
U20F +1.05V_ICH R251 1 2 *short_1206 +1.05V
D3A +1.05V +1.5V
B10
VSS[002]
VSS[003]
VSS[108]
VSS[109]
W11
G17 L11 B13 U14
VCCRTC VCC1_05[01] VSS[004] VSS[110]
L12 B16 W16
VCC1_05[02] VSS[005] VSS[111]

1
C283 C274 G7 L13 C296 C295 B19 U21
B1A R227 D16 0.1u/10V_4 0.1u/10V_4 V5REF VCC1_05[03]
VCC1_05[04] L14 0.022u/16V_4 0.022u/16V_4 D21 *CH751H-40PT B22
VSS[006]
VSS[007]
VSS[112]
VSS[113] U22
U7 L15 2 1 R387 *0_8 D2 U25

2
100/F_6 V5REF_SUS VCC1_05[05] 16 16 VSS[008] VSS[114]
M11 D24 V3
CH751H-40PT VCC1_05[06] VSS[009] VSS[115]
J19 M15 E5 V8
2mA (15mils)
2

1
VCC1_5_B[01] VCC1_05[07] VSS[010] VSS[116]
K18 VCC1_5_B[02] VCC1_05[08] N11 E7 VSS[011] VSS[117] V19
+5V_ICH_V5REF_RUN K19 N15 E9 V23
VCC1_5_B[03] VCC1_05[09] VSS[012] VSS[118]
L18 VCC1_5_B[04] VCC1_05[10] P11 E11 VSS[013] VSS[119] W1

1
A +5V_S5 +3V_S5 L19 P15 E13 W4 A
C315 VCC1_5_B[05] VCC1_05[11] +1.5V VSS[014] VSS[120]
M18 VCC1_5_B[06] VCC1_05[12] R11 23mA (15mils) E15 VSS[015] VSS[121] W5
1u/10V_6 M19 R12 E17 W7

2
VCC1_5_B[07] VCC1_05[13] +1.5V_ICH_VCCDMIPLL L16 1uh_8 VSS[016] VSS[122]
N18 R13 E19 W9
VCC1_5_B[08] VCC1_05[14] VSS[017] VSS[123]
2

N19 R14 E21 W15

VCC1_5_B[09] VCC1_05[15] VSS[018] VSS[124]

2
D17 P18 R15 C266 C265 F24 W19
R252 VCC1_5_B[10] VCC1_05[16] 0.01u/25V_4 10u/6.3V_8 VSS[019] VSS[125]
R18 G2 W21
10_6 VCC1_5_B[11] VSS[020] VSS[126]
T18 G5 W22

1
CH751H-40PT VCC1_5_B[12] VSS[021] VSS[127]
T19 G10 W25
2mA (15mils)
1

VCC1_5_B[13] VSS[022] VSS[128]

U18 G13 Y3

CORE
+5V_ICH_V5REF_SUS VCC1_5_B[14] +1.05V VSS[023] VSS[129]
U19 VCC1_5_B[15] G16 VSS[024] VSS[130] Y23
48mA (15mils) G19 AA1
F3B VSS[025] VSS[131]
2

G21 VSS[026] VSS[132] AA4

C310 +1.05V_ICH_DMI R155 *short_6 H10 AA6
0.1u/10V_4 +1.05V VSS[027] VSS[133]
H12 AA8
1

C284 +1.05V_ICH_IO VSS[028] VSS[134]

H18 AA11
R342 *short_6 VSS[029] VSS[135]
H23 VSS[030] VSS[136] AA13
P19 1u/6.3V_4 J5 AA15
VCCDMIPLL VSS[031] VSS[137]
FB_330ohm+-25%_100mHz_ J9 VSS[032] VSS[138] AA16

1
T17 C376 C375 J10 AA17
1.5A_0.09 ohm DC VCC_DMI[1] 0.1u/10V_4 4.7u/6.3V_6 VSS[033] VSS[139]
+1.5V +1.5V_PCIE_ICH VCC_DMI[2]
U17 2mA (15mils) J11
J12
VSS[034] VSS[140]
AA19
AA21

2
+1.05V_ICH_IO +3V VSS[035] VSS[141]
L14 BLM21P221SGPT_8
0.646A (40mils) V_CPU_IO[1] V16
U16
J13
J15
VSS[036] VSS[142] AA22
AA25
F3B
V_CPU_IO[2] F3B J21
VSS[037] VSS[143]
AB3
+
C269 1 VCC3_3[01] V18 (15mils) +3V_DMI_ICH R175 *short_6 J22
VSS[038]
VSS[039]
VSS[144]
VSS[145] AB9
C273 J25 AB11
(15mils) +3V_SATA_ICH 308mA VSS[040] VSS[146]

VCCA3GP
*100u/6.3V_3528 10u/6.3V_8 AE9 K2 AB13
2

VCC3_3[02] VSS[041] VSS[147]

2
C309 C271
(20mils) K9 VSS[042] VSS[148] AB15
K10 AC24
0.1u/10V_4 (20mils) 0.1u/10V_4 for K11
VSS[043] VSS[149]
AC1

1
+3V_VCCPCORE_ICH R217 *short_6 VSS[044] VSS[150]
AA9 K12 AC4
B VCC3_3[03]
V14 VCC3_3 K13
VSS[045] VSS[151]
AC10 B
VCC3_3[04] (20mils) VSS[046] VSS[152]

1
10uH+-20%_100mA 47mA (15mils) W14 K15 AC12
+1.5V F3B VCC3_3[05] +3V_PCI_ICH C291 R212 *short_6 K17
VSS[047]
VSS[048]
VSS[153]
VSS[154]
AC14

VCCP_CORE
L15 10uh_8 0.1u/10V_4 K23 AD2

2
R161 +1.5V_SATA_ICH
*short_8 +1.5V_APLL_ICH VSS[049] VSS[155]
2 1 VCC3_3[06] G8 L5 VSS[050] VSS[156] AD6

2
H7 L9 AD9
VCC3_3[07] VSS[051] VSS[157]
2

H8 C311 C320 R240 *short_6 L10 AD16

C259 C280 VCC3_3[08] 0.1u/10V_4 *0.1u/10V_4 VSS[052] VSS[158]
L16 AD19

1
10u/6.3V_8 0.1u/10V_4 VSS[053] VSS[159]
L17 AD22
1

VSS[054] VSS[160]
L21 AE3
11mA (15mils) +1.5V_HDA_IO_ICH F3B +1.5VSUS +1.5V L22
VSS[055]
VSS[056]
VSS[161]
VSS[162] AE4

PCI
L25 AE11
+1.5V_HDA_IO_ICH R373 *short_6 VSS[057] VSS[163]
VCCHDA AD7 M9 VSS[058] VSS[164] AE13

W17 V10 +1.5VSUS_VCCSUSHDA

11mA (15mils) R357 *short_6
M10
M12
VSS[059] VSS[165]
AE15
V17
VCCSATAPLL VCCSUSHDA VSS[060] VSS[166]
(30mils) M13
VSS[061] VSS[167]
AE8

2
U13 T7 TP_VCCSUS1.05_1 T62 M14 V9
VCC1_5_A[01] VCCSUS1_05[1] TP_VCCSUS1.05_2 C377 C381 VSS[062] VSS[168]
V13 H15 T57 M16 J16
VCC1_5_A[02] VCCSUS1_05[2] 0.1u/10V_4 0.1u/10V_4 VSS[063] VSS[169]
W13 M17

1
VCC1_5_A[03] VSS[064]
2

ARX

H16 TP_VCCSUS1.5_1 T44 M23

C287 VCCSUS1_5[1] VSS[065]
N2
0.1u/10V_4 TP_VCCSUS1.5_2 VSS[066]
V7 T58 N5
1

VCCSUS1_5[2] VSS[067]
N9
VSS[068]
N10
+3V_S5 VSS[069]
(30mils) G14 N12
U12
VCC1_5_A[04]
VCCSUS3_3[01]
VCCSUS3_3[02]
G15 (15mils) F3B 212mA (40mils) N13
VSS[070]
VSS[071]
V12 H14 +3V_S5_ICH R211 *short_6 N14
VCCPSUS

VCC1_5_A[05] VCCSUS3_3[03] VSS[072]

2

W12
VCC1_5_A[06] for VCCSUS3_3 N16
VSS[073]

1
ATX

C307 C298 N17

0.1u/10V_4 0.1u/10V_4 VSS[074]
N21
1

VSS[075]
W8 N22

2
VCCSUS3_3[04] VSS[076]
N25
C VSS[077] C
VCCSUS3_3[05] J7 P9 VSS[078]
VCCSUS3_3[06] J8 P10 VSS[079]
W10 K7 P12
(30mils)
VCC1_5_A[07] VCCSUS3_3[07]
VCCSUS3_3[08] K8
(20mils) F3B P13
VSS[080]
VSS[081]
U15 L7 P14
VCC1_5_A[08] VCCSUS3_3[09] VSS[082]
2

V15 L8 +V3_S5_USB_ICH R225 *short_8 P16

C299 VCC1_5_A[09] VCCSUS3_3[10] VSS[083]
M7 P17
VCCSUS3_3[11] VSS[084]
1

1
0.1u/10V_4 W18 M8 C312 C306 C313 P23
1

VCC1_5_A[10] VCCSUS3_3[12] 0.022u/16V_4 0.1u/10V_4 0.1u/10V_4 VSS[085]

N7 R5
VCCPUSB

VCCSUS3_3[13] VSS[086]
G9 N8 R7
F3B
2

2
VCC1_5_A[11] VCCSUS3_3[14] VSS[087]
H9 VCC1_5_A[12] VCCSUS3_3[15] P7 R8 VSS[088]
R377 *short_8 +1.5V_USB_ICH
11mA (15mils) V11
VCCSUS3_3[16]
P8 R9
R10
VSS[089]
VCC1_5_A[13] VSS[090]
U11 R16
VCC1_5_A[14] VSS[091]
2

R17 VSS[092]
C305 R19
0.1u/10V_4 TP_VCCCL1.05 VSS[093]
U8 G18 T49 R21 A1
1

VCCUSBPLL VCCCL1_05 VSS[094] VSS_NCTF[01]

(30mils) R22 A25
+VCCCL1_5 VSS[095] VSS_NCTF[02]
T9 H17 R25 AE1
VCC1_5_A[15] VCCCL1_5 VSS[096] VSS_NCTF[03]
2

USB CORE

U9 T2 AE25
C304 VCC1_5_A[16] +3V_ICH R213 *short_6 +3V C290 VSS[097] VSS_NCTF[04]
J14 T8
0.1u/10V_4 VCCCL3_3[1] VSS[098]
K14 T10
1

VCCCL3_3[2] 1u/6.3V_4 VSS[099]

T11
C302 VSS[100]
+3V 2 1 0.1u/10V_4
(20mils) VCCLAN1_05_INT_ICH G11 F3B T12
T13
VSS[101]
VCCLAN1_05[1] VSS[102]
H11 T14
VCCLAN1_05[2] VSS[103]
19mA (15mils) G12
T15
T16
VSS[104]
VCCLAN3_3[1] VSS[105]
23mA (15mils) H13
VCCLAN3_3[2]
T23
VSS[106]
2

C293 +1.5V
0.1u/10V_4 L13 1uh_8 +1.5V_ICH_GLANPLL_R_L J17 ICH9MSFF REV 1.0
VCCGLANPLL
1

GLAN POWER

D C281 D
H19
C262 VCCGLAN1_5[1]
J18 VCCGLAN1_5[2]
10u/6.3V_8 2.2u/6.3V_6
+1.5V_PCIE_ICH
80mA (15mils)
K16
VCCGLAN3_3
C279
10u/6.3V_8
ICH9MSFF REV 1.0
PROJECT : BU3
F3B Quanta Computer Inc.
1mA (15mils) Size Document Number Rev
R199 *short_6+3.3V_GLAN_ICH Custom ICH9-M (POWER,GND) D3B
+3V
NB7
Date: Monday, August 10, 2009 Sheet 15 of 34
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

DDRIII +SMDDR_VTERM +SMDDR_VTERM

TERMINATOR DECOUPLING CAPACITOR
SMDDR_VREF_DIMM +3V
9.12A(VCC plane from source)
+1.5VSUS +1.5VSUS

C49 C33 C35 C37 C38 C39 C112 C248 C54 C55 C157 C125 C141 C126 C136 C163

10u/6.3V_8 10u/6.3V_8 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 0.1u/10V_4 2.2u/6.3V_6 2.2u/6.3V_6 0.1u/10V_4 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8

Close to DIMM0 Close to DIMM0

+1.5VSUS +1.5VSUS

A +SMDDR_VTERM SMDDR_VREF_DIMM +3V A

+ C186
F3B C147 C134 C168
+ C149
F3B C161 C140 C133

C51 C56 C57 C58 C59 C249 C110 C53 C50 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8
*220u/2.5V_3528 *220u/2.5V_3528
10u/6.3V_8 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 0.1u/10V_4 2.2u/6.3V_6 2.2u/6.3V_6 0.1u/10V_4

Close to DIMM1 Close to DIMM1 Close to DIMM0 Close to DIMM1

+3V SMDDR_VREF_DIMM +1.5VSUS CN20 +1.5VSUS SMDDR_VREF_DIMM +3V SMDDR_VREF_DIMM +1.5VSUS CN19 +1.5VSUS SMDDR_VREF_DIMM
M_B_DM[0..7] [7]
M_A_DM[0..7] [7] M_B_DQ[0..63] [7]
M_A_DQ[0..63] [7] 75 76 M_B_DQS[0..7] [7] 75 76
VDD1 VDD2 VDD1 VDD2
M_A_DQS[0..7] [7] 81 82 M_B_DQS#[0..7] [7] 81 82
VDD3 VDD4 VDD3 VDD4
M_A_DQS#[0..7] [7] 87 88 M_B_A[14:0] [7] 87 88
VDD5 VDD6 VDD5 VDD6
M_A_A[14:0] [7] 93 94 93 94
VDD7 VDD8 VDD7 VDD8
99 100 99 100
VDD9 VDD10 VDD9 VDD10
105 106 105 106
VDD11 VDD12 VDD11 VDD12
111 112 111 112
VDD13 VDD14 VDD13 VDD14
117 118 117 118
VDD15 VDD16 VDD15 VDD16
123 124 123 124
VDD17 VDD18 VDD17 VDD18
1 126 1 126
VREF_DQ VREF_CA VREF_DQ VREF_CA
199 199
VDD(SPD) VDD(SPD)
M_A_DQ0 5 4 M_A_DQ4 M_B_DQ0 5 4 M_B_DQ4
M_A_DQ5 DQ0 DQ4 M_A_DQ7 M_B_DQ1 DQ0 DQ4 M_B_DQ5
7 6 7 6
M_A_DQ3 DQ1 DQ5 M_A_DQ1 M_B_DQ7 DQ1 DQ5 M_B_DQ3
15 16 15 16
M_A_DQ6 DQ2 DQ6 M_A_DQ2 M_B_DQ6 DQ2 DQ6 M_B_DQ2
17 18 17 18
M_A_DM0 DQ3 DQ7 M_A_DQS#0 M_B_DM0 DQ3 DQ7 M_B_DQS#0
11 10 11 10
DM0 DQS#0 M_A_DQS0 DM0 DQS#0 M_B_DQS0
12 12
M_A_DQ10 DQS0 M_B_DQ13 DQS0
21 21
M_A_DQ8 DQ8 M_A_DQ15 M_B_DQ9 DQ8 M_B_DQ12
23 22 23 22
M_A_DQ9 DQ9 DQ12 M_A_DQ13 M_B_DQ11 DQ9 DQ12 M_B_DQ8
33 24 33 24
M_A_DQ12 DQ10 DQ13 M_A_DQ14 M_B_DQ10 DQ10 DQ13 M_B_DQ14
35 34 35 34
M_A_DQS#1 DQ11 DQ14 M_A_DQ11 M_B_DQS#1 DQ11 DQ14 M_B_DQ15
27 36 27 36
M_A_DQS1 DQS#1 DQ15 M_A_DM1 M_B_DQS1 DQS#1 DQ15 M_B_DM1
29 28 29 28
DQS1 DM1 DQS1 DM1
B M_A_DQ23 39 40 M_A_DQ17 M_B_DQ16 39 40 M_B_DQ20 B
M_A_DQ18 DQ16 DQ20 M_A_DQ21 M_B_DQ21 DQ16 DQ20 M_B_DQ17
41 42 41 42
M_A_DQ22 DQ17 DQ21 M_A_DQ20 M_B_DQ22 DQ17 DQ21 M_B_DQ18
51 50 51 50
M_A_DQ16 DQ18 DQ22 M_A_DQ19 M_B_DQ19 DQ18 DQ22 M_B_DQ23
53 52 53 52
M_A_DQS#2 DQ19 DQ23 M_A_DM2 M_B_DQS#2 DQ19 DQ23 M_B_DM2
45 46 45 46
M_A_DQS2 DQS#2 DM2 M_B_DQS2 DQS#2 DM2
47 47
DQS2 M_A_DQ26 DQS2 M_B_DQ28
56 56
M_A_DQ24 DQ28 M_A_DQ29 M_B_DQ24 DQ28 M_B_DQ25
57 58 57 58
M_A_DQ31 DQ24 DQ29 M_A_DQ27 M_B_DQ29 DQ24 DQ29 M_B_DQ30
59 68 59 68
M_A_DQ28 DQ25 DQ30 M_A_DQ30 M_B_DQ26 DQ25 DQ30 M_B_DQ31
67 70 67 70
M_A_DQ25 DQ26 DQ31 M_A_DQS#3 M_B_DQ27 DQ26 DQ31 M_B_DQS#3
69 62 69 62
M_A_DM3 DQ27 DQS#3 M_A_DQS3 M_B_DM3 DQ27 DQS#3 M_B_DQS3
63 64 63 64
DM3 DQS3 DM3 DQS3
M_CKE0 73 74 M_CKE1 M_CKE2 73 74 M_CKE3
[6] M_CKE0 CKE0 CKE1 M_CKE1 [6] [6] M_CKE2 CKE0 CKE1 M_CKE3 [6]
M_A_BS#2 79 108 M_A_BS#1 M_B_BS#2 79 108 M_B_BS#1
[7] M_A_BS#2 BA2 BA1 M_A_BS#1 [7] [7] M_B_BS#2 BA2 BA1 M_B_BS#1 [7]
[7] M_A_BS#0 M_A_BS#0 109 [7] M_B_BS#0 M_B_BS#0 109
BA0 M_A_A14 BA0 M_B_A14
80 80
M_A_A12 A14 M_A_A11 M_B_A12 A14 M_B_A11
83 84 83 84
M_A_A9 A12/BC# A11 M_A_A7 M_B_A9 A12/BC# A11 M_B_A7
85 86 85 86
M_A_A8 A9 A7 M_A_A6 M_B_A8 A9 A7 M_B_A6
89 90 89 90
M_A_A5 A8 A6 M_A_A4 M_B_A5 A8 A6 M_B_A4
91 92 91 92
M_A_A3 A5 A4 M_A_A2 M_B_A3 A5 A4 M_B_A2
95 96 95 96
M_A_A1 A3 A2 M_A_A0 M_B_A1 A3 A2 M_B_A0
97 98 97 98
M_A_A10 A1 A0 M_B_A10 A1 A0
107 107
M_A_A13 A10/AP DDR3_DRAMRST# M_B_A13 A10/AP DDR3_DRAMRST#
119 RESET#
30 119 RESET#
30 DDR3_DRAMRST# [6]
A13 A13
M_CLK_DDR0 101 102 M_CLK_DDR1 M_CLK_DDR2 101 102 M_CLK_DDR3
[6] M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 [6] [6] M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 [6]
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
SO-DIMM (204P)

SO-DIMM (204P)
[6] M_CLK_DDR#0 103 104 M_CLK_DDR#1 [6] [6] M_CLK_DDR#2 103 104 M_CLK_DDR#3 [6]
CK0# CK1# CK0# CK1#
M_CS#1 121 114 M_CS#0 M_CS#3 121 114 M_CS#2
DDR3 SDRAM

DDR3 SDRAM
[6] M_CS#1 CS1# CS#0 M_CS#0 [6] [6] M_CS#3 CS1# CS#0 M_CS#2 [6]
M_A_WE# 113 110 M_A_RAS# M_B_WE# 113 110 M_B_RAS#
[7] M_A_WE# WE# RAS# M_A_RAS# [7] [7] M_B_WE# WE# RAS# M_B_RAS# [7]
M_A_CAS# 115 M_B_CAS# 115
[7] M_A_CAS# CAS# [7] M_B_CAS# CAS#
116 M_ODT0 116 M_ODT2
ODT0 M_ODT0 [6] ODT0 M_ODT2 [6]
M_A_DQ32 129 120 M_ODT1 M_B_DQ32 129 120 M_ODT3
DQ32 ODT1 M_ODT1 [6] DQ32 ODT1 M_ODT3 [6]
M_A_DQ37 131 M_B_DQ37 131
M_A_DQ36 DQ33 M_A_DQ34 M_B_DQ34 DQ33 M_B_DQ36
141 130 141 130
M_A_DQ35 DQ34 DQ36 M_A_DQ39 M_B_DQ35 DQ34 DQ36 M_B_DQ33
143 132 143 132
M_A_DQS#4 DQ35 DQ37 M_A_DQ33 M_B_DQS#4 DQ35 DQ37 M_B_DQ38
135 140 135 140
M_A_DQS4 DQS#4 DQ38 M_A_DQ38 M_B_DQS4 DQS#4 DQ38 M_B_DQ39
137 142 137 142
DQS4 DQ39 M_A_DM4 DQS4 DQ39 M_B_DM4
136 136
C M_A_DQ41 DM4 M_B_DQ41 DM4 C
147 147
M_A_DQ40 DQ40 M_A_DQ47 M_B_DQ40 DQ40 M_B_DQ44
149 146 149 146
M_A_DQ42 DQ41 DQ44 M_A_DQ45 M_B_DQ43 DQ41 DQ44 M_B_DQ45
157 148 157 148
M_A_DQ43 DQ42 DQ45 M_A_DQ44 M_B_DQ47 DQ42 DQ45 M_B_DQ46
159 158 159 158
M_A_DM5 DQ43 DQ46 M_A_DQ46 M_B_DM5 DQ43 DQ46 M_B_DQ42
153 160 153 160
DM5 DQ47 M_A_DQS#5 DM5 DQ47 M_B_DQS#5
152 152
M_A_DQ49 DQS#5 M_A_DQS5 M_B_DQ53 DQS#5 M_B_DQS5
163 154 163 154
M_A_DQ55 DQ48 DQS5 M_B_DQ52 DQ48 DQS5
165 165
M_A_DQ51 DQ49 M_A_DQ50 M_B_DQ51 DQ49 M_B_DQ50
175 164 175 164
M_A_DQ54 DQ50 DQ52 M_A_DQ53 M_B_DQ49 DQ50 DQ52 M_B_DQ48
177 166 177 166
M_A_DQS#6 DQ51 DQ53 M_A_DQ48 M_B_DQS#6 DQ51 DQ53 M_B_DQ54
169 174 169 174
M_A_DQS6 DQS#6 DQ54 M_A_DQ52 M_B_DQS6 DQS#6 DQ54 M_B_DQ55
171 176 171 176
DQS6 DQ55 M_A_DM6 DQS6 DQ55 M_B_DM6
170 170
M_A_DQ63 DM6 M_B_DQ56 DM6
181 181
M_A_DQ56 DQ56 M_A_DQ57 M_B_DQ57 DQ56 M_B_DQ59
183 180 183 180
M_A_DQ59 DQ57 DQ60 M_A_DQ60 M_B_DQ60 DQ57 DQ60 M_B_DQ61
191 182 191 182
M_A_DQ61 DQ58 DQ61 M_A_DQ62 M_B_DQ62 DQ58 DQ61 M_B_DQ58
193 192 193 192
M_A_DM7 DQ59 DQ62 M_A_DQ58 M_B_DM7 DQ59 DQ62 M_B_DQ63
187 194 187 194
DM7 DQ63 M_A_DQS#7 DM7 DQ63 M_B_DQS#7
186 186
PM_EXTTS#0 DQS#7 M_A_DQS7 PM_EXTTS#1 DQS#7 M_B_DQS7
[6] PM_EXTTS#0 198 188 [6] PM_EXTTS#1 198 188
EVENT# DQS7 EVENT# DQS7
R16 10K_4 197 200 CGDAT_SMB R22 10K_4 197 200 CGDAT_SMB
SA0 SDA CGDAT_SMB [2,20] SA0 SDA
R17 10K_4 201 202 CGCLK_SMB +3V R23 10K_4 201 202 CGCLK_SMB
SA1 SCL CGCLK_SMB [2,20] SA1 SCL
+SMDDR_VTERM 77 78 +SMDDR_VTERM +SMDDR_VTERM 77 78 +SMDDR_VTERM SMDDR_VREF_DIMM
NC1 A15 NC1 A15
125 122 125 122
NCTEST NC2 NCTEST NC2 F3B
203 204 203 204
VTT1 VTT2 VTT1 VTT2 R138 *short_6 +SMDDR_VREF
3 2 3 2
VSS2 VSS1 VSS2 VSS1
9 8 9 8
VSS4 VSS3 VSS4 VSS3 R136 *10K_4 R46 *10K_4
13 14 13 14 +1.5VSUS
VSS5 VSS6 VSS5 VSS6
19 20 19 20
VSS7 VSS8 VSS7 VSS8
25
VSS9 VSS10
26 25
VSS9 VSS10
26 0.32uA(20mils)
31 32 31 32
VSS11 VSS12 VSS11 VSS12
37 38 37 38
VSS13 VSS14 VSS13 VSS14
43 44 43 44
VSS15 VSS16 VSS15 VSS16
49 48 49 48
VSS18 VSS17 VSS18 VSS17
55 54 55 54
VSS20 VSS19 VSS20 VSS19
61 60 61 60
VSS22 VSS21 VSS22 VSS21
65 66 65 66
VSS23 VSS24 VSS23 VSS24
71 72 71 72
D VSS25 VSS26 VSS25 VSS26 D
127 128 127 128
VSS27 VSS28 VSS27 VSS28
133 134 133 134
VSS29 VSS30 VSS29 VSS30
139 138 139 138
VSS32 VSS31 VSS32 VSS31
145 144 145 144
VSS34 VSS33 VSS34 VSS33
151 150 151 150
VSS36 VSS35 VSS36 VSS35
155 156 155 156
VSS37 VSS38 VSS37 VSS38
161 162 161 162
VSS39 VSS40 VSS39 VSS40
167 168 167 168
VSS41 VSS42 VSS41 VSS42
173 172 173 172
VSS44 VSS43 VSS44 VSS43
179 178 179 178
VSS46 VSS45 VSS46 VSS45
185 184 185 184
VSS48 VSS47 VSS48 VSS47
189 190 189 190
VSS49 VSS50 VSS49 VSS50
195
VSS51 VSS52
196 195
VSS51 VSS52
196 PROJECT : BU3
DDRRK-20401-TP4B DDRSK-20401-TP4B Quanta Computer Inc.
DDR-REV. DDR-STD.
Size Document Number Rev
DIMM0 DIMM1 Custom
DDR2 SODIMMS: A/B CHANNEL D3B
NB7
Date: Monday, August 10, 2009 Sheet 16 of 34
1 2 3 4 5 6 7 8
 5 4 3 2 1

CN1

LCD Panel Module 0.3A (20mils) VIN 1

2
1 HALL SENSOR&BACK LIGHT SWITCH
LCDVCC 2
LCDVCC 3 3
4 +3V
4
+3V 5 5
CCD_POWER 6
MIC_GND 6
[21] MIC_GND 7 7
INT_MIC_R 8 R14
[21] INT_MIC_R 8
9 9
VIN 10 1K_4
USBP3-_LCD 10
11 11
USBP3+_LCD 12
D 12 DISPON [22] D
+ C332 C3 C2 13
LCD_DDCCLK 13
[6] LCD_DDCCLK 14 14
10u/25V_1210 1000p/50V_4 0.1u/25V_6 LCD_DDCDAT 15 DISPON D2 BAS316
[6] LCD_DDCDAT 15 LID591# [21,22]
16
[6] INT_TXLCLKOUT-
INT_TXLCLKOUT-
INT_TXLCLKOUT+
17
16
17
F3B
D1 RSX101M-30
[6] INT_TXLCLKOUT+ 18 18 INT_LVDS_BLON [6]
19 19
INT_TXLOUT2- 20
[6] INT_TXLOUT2- 20
INT_TXLOUT2+ 21 R11
[6] INT_TXLOUT2+ 21
22 22

3
INT_TXLOUT1- 23 100K_4
[6] INT_TXLOUT1- 23
+3V R259 2.2K_4 LCD_DDCDAT INT_TXLOUT1+ 24 34
[6] INT_TXLOUT1+ 24 34
25 25 2 EC_FPBACK# [22]
R258 2.2K_4 LCD_DDCCLK INT_TXLOUT0- 26 33
[6] INT_TXLOUT0- 26 33
INT_TXLOUT0+ 27 Q12
[6] INT_TXLOUT0+ 27
NB Strap 28 32

1
LVDS_VADJ 28 32 DTC144EUA
29 29
INT_LVDS_EDIDDATA DISPON 30 30 31 31

GS13307-11230-7F

F3B R3 0_4

U25 input S
C 1
*PI5A3157CE
6
output A
S S CRT CON. C
[6] INT_LVDS_PWM B1 S BLPWM_SEL [22]
2 5 +3V INT_LVDS_PWM H
GND VCC
3 4 LVDS_VADJ CN16
[22] CONTRAST B0 A CONTRAST L +5V
(20mil) 1 2 +3V
3 4
R2 *0_4 C7 0.1u/10V_4 5 6 CRT_DDCDAT
CRT_DDCDAT [6]
CRT_VSYNC 7 8 CRT_DDCCLK
[6] CRT_VSYNC CRT_DDCCLK [6]
CRT_HSYNC 9 10
[6] CRT_HSYNC
11 12 RED_L
GREEN_L 13 14
CCD 15 16 BULE_L

0.2A(20mils)
USBP3+_LCD RP1 2 1 0X2 +5V R1 *short_8 CCD_POWER
USBP3+ [13]
USBP3-_LCD 4 3 USBP3- [13]
C6 10u/6.3V_8 88107-16001

+
R260 2.2K_4 CRT_DDCCLK
L1 +3V
1 2*WCM2012-90_C C5 *1000p/50V_4
4 3 R261 2.2K_4 CRT_DDCDAT
C4 *0.1u/10V_4

B E3A B

R390 0_6 RED_L

LCD POWER SWITCH +10V [6] CRT_RED
R393 0_6 GREEN_L
[6] CRT_GREEN
+3V
R394 0_6 BULE_L
[6] CRT_BLUE
R8
3

330K_6 1.5A(65mils)
Q4 C400 C399 C398 C401 C402 C403
+3VPCU LCDONG 2 LCDVCC
AO3404 *4.7p/50V_4 *4.7p/50V_4 *4.7p/50V_4 *4.7p/50V_4 *4.7p/50V_4 *4.7p/50V_4
F3B
R9 C11 LCDVCC1 L2 *short_6
1
3

100K_4 0.01u/25V_4
R5 C9 C10 C8
2 Q6
22_8 0.1u/10V_4 0.01u/25V_4 10u/6.3V_8
ME2N7002E CRT CON. co-lay
3

LCDDISCHG
Q5
1

2
[6] INT_LVDS_DIGON
E3A
LCDON# 2 Q3
1

A A
R10 PDTC143TT
ME2N7002E
100K_4
1

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
LCD/LED Panel/CCD
Date: Monday, August 10, 2009 Sheet 17 of 34
5 4 3 2 1
 5 4 3 2 1

HDMI IC
+3V
B1A

NB Strap R315 R313

SDVO_CTRLDATA 1.5K/F_4 1.5K/F_4

SDVO_CTRLCLK
SDVO_CTRLDATA
D D

B1A
HDMI HPD +3V

R301

20K_4

PORT-B_HPD#
PORT-B_HPD# [6]

C C

HDMI CON. USB SW +3V_S5

U21
TS3USB221DRCR
USB_SW+ 1 1D+ 10 C380 *0.1u/10V_4
VCC
USB_SW- 2 9 USB_BUS_SW0
C2A 1D- S USB_BUS_SW0 [14]
CN11 USBP9+ 3 8 BUSBP9+
F3B 1
[13] USBP9+
USBP9-
2D+ D+
BUSBP9-
[13] USBP9- 4 7
2 2D- D-
3 USB_BUS_SW1
5 6

GND
GND
GND
+3V 4 GND OE USB_BUS_SW1 [14]
15 14
5 GND GND
+5VPCU 6
2A (80mils)

13
12
11
7
8
(30mils) +5V 9
10 +3V_S5 R367 *10K_4 USB_BUS_SW0

BUSBP9- 11 R193 10K_4 USB_BUS_SW1

BUSBP9+ 12
13
14 Default Mount
[13,22] USBOC9# 15
[22] USB_SLEEP_EN# 16
[14] BOARD_ID4 17
PORT-B_HPD#
B SDVO_CTRLDATA 18 B
[6] SDVO_CTRLDATA 19 +5VPCU +5VPCU +5VPCU
SDVO_CTRLCLK
[6] SDVO_CTRLCLK 20
TMDSB_CLK# 21
[6] TMDSB_CLK# 22
TMDSB_CLK
[6] TMDSB_CLK 23
TMDSB_DATA0# 24 R321 R322
[6] TMDSB_DATA0# 25
TMDSB_DATA0 U19 75K/F_4 43K_4
[6] TMDSB_DATA0 26
14 7
TMDSB_DATA2# 27 VCC GND
[6] TMDSB_DATA2# 28
[6] TMDSB_DATA2 TMDSB_DATA2 USB_SW+ 2 3
29 C379 1A 1B
TMDSB_DATA1# 30 USB_SW-
[6] TMDSB_DATA1# 5 6
TMDSB_DATA1 31 2A 2B
[6] TMDSB_DATA1 32 0.1u/10V_4
9 11
88511-3201 3A 4B
12 8 R364 100_4
4A 3B
USB_BUS_SW3 1 10 USB_BUS_SW2
[14] USB_BUS_SW3 1OE 3OE USB_BUS_SW2 [14]
4 13 R324 R325
2OE 4OE
51K_4 51K_4
EMI SN74CBT3125CPWR

S OE# Function
X H Disconnect OE# Function OE# 1OE# 2OE# 3OE# 4OE#
A A
L L D=1D H Disconnect Mode3 High High Low Low
H L D=2D L A port= B port Mode4 Low Low High High

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
HDMI/USB SW/EMI
Date: Monday, August 10, 2009 Sheet 18 of 34
5 4 3 2 1
 5 4 3 2 1

SATA ODD G-sensor

+3V_HDP

U4
6 2 ACCELX
C2A +3V_HDP Vdd Xout
Yout 3 ACCELY
U7 C123 7 4 ACCELZ
CN7 SLEEP# Zout
[9,22,27,28,29,31] MAINON 1 4
SHDN VO C185 *[email protected]/10V_4 AXSTST
1 13
GND +5VPCU Self Test
2
GND *GS@10u/6.3V_8
RXP 2 SATA_TXP1 [12]
3 VIN SET 5
3 SATA_TXN1 [12] 1
RXN C170 R42 *GS@0_4 NC
GS@G913C 10 8
D g-select NC D
GND 4 9 0g-Detect NC 11
[email protected]/10V_4 12
NC
5 SATA_RXN1 [12] 5 14
TXN GND NC
6 *GS@MMA73XXL
TXP SATA_RXP1 [12]

GND 7

8 R118 *1K_4
DP
9 R289 *short_6
+5V 1.6A(100mils)
10 +5V_ODD R285 *short_8 +5V FS (Full Scale) selection
+5V
0 1
C225 C217 C212 C221 C200 + C345 FS +3V_HDP
*88513-1041 2g Full-Scale 6g Full-Scale 0.0015A(20mils) U5
*0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *10u/6.3V_8 *100u/6.3V_3528 +3V_HDP 2 3 ACCELX
Vdd Voutx ACCELY
12 5
Vdd Vouty ACCELZ R69
PD (Power Down) selection Voutz
7
C155 C124 *GS@10K_4
0 1 9 4 AXSTST
GS@10u/6.3V_8 [email protected]/10V_4 Reserve ST FS
PD 10 Reserve FS 8
Normal Mode Power-down mode 11
Reserve
6 14 R60
PD NC GS@0_4
13 GND NC 15
1 GND NC 16

Main SATA HDD HDPPD selection GS@TSH35TR

0 1
HDPPD
Normal Mode Power-down mode

C C

CN18
23
GND23

GND1
1 F3B +3V_HDP
B1A
2 SATA_TXP0_R RP8 2 1 *short_4P2R SATA_TXP0
RXP SATA_TXN0_R SATA_TXN0
3 4 3
RXN
GND2 4 0.013A(20mils) U6
5 SATA_RXN0_R RP7 2 1 *short_4P2R SATA_RXN0 +3V_HDP
TXN SATA_RXP0_R SATA_RXP0 KXP84_SCL
6 4 3 +3V_HDP 16 1
TXP VCC HDPSCL KXP84_SDA
7 7 20
GND3 C167 C166 C129 VCC HDPSDA
(20mils) ACCELY 18
ACCELX RESET
3 G-RESET# R85 [email protected]_4
8 +3.3VSATA1 R275 *0_8 GS@1u/6.3V_4 [email protected]/10V_4 [email protected]/10V_4 ACCELX 17 8 R88 [email protected]_4
3.3V +3V ACCELY MODE
9 ACCELZ 15
3.3V AXSTST ACCELZ XIN_G R86 [email protected]_4
10 2 4
3.3V C340 C341 AXSTST Reserved XOUT_G R87 [email protected]_4
11 6
GND HDPACT Reserved
12 [14] HDPACT 11 12
GND *10u/6.3V_8 *0.1u/10V_4 GND HDPACT Reserved
GND
13 Close to Pin 7 and Pin 16 HD_PINT
10
HDPPD Reserved
13
14 R89 GS@1K_4 9
5V [14] HDPINT HDPINT
15 HDPLOC R54 *GS@0_4 14 19
5V [14] HDPLOC HDPLOC Reserved
16 5
5V VSS
17
GND GS@R5F211B4D34SP#W4(3B25H)
RSVD
18
0.94A(80mils) Close Chipset
19
GND HDPLOC HDPACT
12V
20 ADDRESS: 32H
21 +5V_HDD1 R271 *short_8 +5V
12V
22
12V
24 C338 C339 C337 + C335 R52 R55
GND24
13@C166AN-12205-L 0.1u/10V_4 0.1u/10V_4 10u/6.3V_8 *100u/6.3V_3528 *GS@47K/F_6 GS@47K/F_6

+3V_HDP
B B

U8
Vcc
3
G-RESET#
Close Chipset ACCELX
1
Reset#
2
GND ACCELY
*GS@G691L308T73UF
ACCELZ
Main SATA HDD (For 11.6") C128 C127 C130

[email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4

CN5
1 +3V_HDP
GND
2 SATA_TXP0 SATA_TXP0 [12]
RXP XIN_G C178 *GS@22p/50V_4
3 SATA_TXN0 SATA_TXN0 [12]
RXN

1
Y2
4 R56 R84
GND *GS@8MHZ
5 SATA_RXN0 [email protected]_4 [email protected]_4
SATA_RXN0 [12]

2
TXN
2

XOUT_G C179 *GS@22p/50V_4

6 SATA_RXP0
TXP SATA_RXP0 [12] KXP84_SDA
[22] 3ND_MBDATA 3 1
7
GND Q16 GS@ME2N7002E
8
DP
9 +3V_HDP
+5V 0.94A(80mils)
10 +5V_HDD1
+5V
A A
2

*11@88513-1041
3 1 KXP84_SCL
[22] 3ND_MBCLK
Q17 GS@ME2N7002E

CO-LAYOUT With MAIN SATA HDD

Quanta Computer Inc.
PROJECT : BU3
Size Document Number Rev
D3B
HDD/ODD/G-sensor
Date: Monday, August 10, 2009 Sheet 19 of 34
5 4 3 2 1
 5 4 3 2 1

MINI Card Slot#1 +1.5V WIMAX_P +3V_S5 WIMAX_P

(WLAN)
F3B 0.5A(30mils) 2.75A(120mils)
D3A B1A C322 C318 C292 C319 C325
R335 *0_4 SERIRQ_debug

PLTRST# R379 *100K_4

[14,22] SERIRQ
[12] LDRQ#1
R206 *0_4 LDRQ#1__debug
PLTRST#_debug
C2A 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 10u/6.3V_8

R209 *0_4 PCLK_DEBUG_R

[2] PCLK_DEBUG
CN22
51 NC +3.3V 52
R207 *0_4 CL_RST#1_WLAN 49 50 +1.5V
[14] ICH_CL_RST1# C-Link_RST GND
R219 *0_4 PLTRST#_PCIE 47 48
[14] CL_DATA1
[14] CL_CLK1
R203 *0_4 CL_CLK1_WLAN 45
C-Link_DAT
C-Link_CLK
+1.5V
LED_WPAN#
46 B1A
D 43 44 D
GND LED_WLAN# C323 C317 C316
41 42 WiMAX_LED# [21]
NC NC
39 NC NC 40
37 38 USBP10+ [13] 0.01u/25V_4 0.1u/10V_4 10u/6.3V_8
GND USB_D+
35 GND USB_D- 36 USBP10- [13]
[13] PCIE_TXP6 33 PETp0 GND 34
31 32 WL_SMDATA
[13] PCIE_TXN6 PETn0 SMB_DATA
29 30 WL_SMCLK
GND SMB_CLK
27 28
GND +1.5V
25 26
Intel module use S5 power for +3.3V
[13] PCIE_RXP6
[13] PCIE_RXN6 23
PERp0
PERn0
GND
+3.3Vaux
24 +3V_S5
0.33A(30mils)
Other module keep +3V for +3.3V 21 22 PLTRST#
GND PERST# RF_EN
19 NC W_DISABLE# 20 RF_EN [22]
17 NC GND 18
WIMAX_P
+3V_S5 WIMAX_P +3V_S5 15
GND NC
16 LFRAME#_PCIE R236 F3B *0_4 LFRAME# [12,22]
13 14 LAD3_PCIE R235 *0_4
[2] CLK_PCIE_MINI1 REFCLK+ NC LAD3 [12,22]
11 12 LAD2_PCIE R234 *0_4
[2] CLK_PCIE_MINI1# REFCLK- NC

4
2
9 10 LAD1_PCIE R233 *0_4 LAD2 [12,22]
GND NC LAD0_PCIE R232 *0_4 LAD1 [12,22] RP6
7 8
WCS_CLK R204 *short_4 WCS_CLKR CLKREQ# NC LAD0 [12,22]
1 3 [21] WCS_CLK 5 6
R250 WCS_DAT R205 *short_4 WCS_DATR BT_CHCLK +1.5V 4.7KX2
To BT [21] WCS_DAT 3
BT_DATA GND
4
Q22 AO3413 4.7K_4 WLAN_WAKE# 1 2 Q24

54
53
WAKE# +3.3V

2
ME2N7002E
2

3
1
80052-1021

54
53
3 1 WL_SMDATA
[2,16] CGDAT_SMB
[14,23] PCIE_WAKE# 3 1

Q20 ME2N7002E R247 *0_4

3

B1A

2
Q23 R208 10K_4 WIMAX_P
WIMAX_P
2 WMAX_P [22]
DTC144EUA
Q25
1

2
C C
ME2N7002E

3 1 WL_SMCLK
[2,16] CGCLK_SMB

R248 *0_4

MINI Card Slot#2

B1A +1.5V_3G +3V_3G
+3V_3G
3G
+3V_S5
F3B +3V_3G +3V_S5
C2A C267 C264 C327 C328
2.75A(120mils)
[email protected]/25V_4 [email protected]/10V_4 [email protected]/10V_4 3G@10u/6.3V_8
CN21
51 52
NC +3.3V
1 3 49 50
R253 C-Link_RST GND
47 48
Q27 3G@AO1313 [email protected]_4 C-Link_DAT +1.5V
45 46
C-Link_CLK LED_WPAN#
43 44
2

GND LED_WLAN#
41 42 3G_LED# [21]
+3.3V LED_WWAN#
39 40 CPUSB# [12,14]
+3.3V CPUSB#
37 38
B1A 35
CPEE#
GND
USB_D+
USB_D-
36
USBP6+ [13]
USBP6- [13] D3A
[13] PCIE_TXP3 33 34
PETp0 GND
3

Q26
[13] PCIE_TXN3 31
29
PETn0 SMB_DATA 32
30
B1A +1.5V +1.5V_3G
GND SMB_CLK
2 27 28
3G_P [22]
[13] PCIE_RXP3 25
GND
PERp0
+1.5V
GND 26 0.5A(30mils)
B 3G@DTC144EUA 23 24 B
[13] PCIE_RXN3 RERn0 +3.3Vaux
21 22 PLTRST#
PLTRST# [13,21,22,23]
1

GND RESET# 3G_EN R380 *3G@0_8

19 20 3G_EN [22]
MMC_DAT W_DISABLE#
17 18
MMC_CMD GND
15 16 UIM_VPP +1.5V_3G
GND UIM_VPP UIM_RST
[2] CLK_PCIE_3G 13 14
REFCLK+ UIM_RST UIM_CLK
[2] CLK_PCIE_3G# 11 12
REFCLK- UIM_CLK UIM_DATA
9 GND UIM_DATA 10
7 8 UIM_PWR C383 C384 C385
CLKREQ# UIM_PWR C308
5 6
D3A 3
BT_CHCLK
BT_DATA
+1.5V
GND
4 *[email protected]/25V_4 *[email protected]/10V_4 *3G@10u/6.3V_8
PCIE_WAKE# 3 1 3G_WAKE# 1 2 *3G@100p/50V_4
54
53

WAKE# +3.3V
Q31 *3G@ME2N7002E 3G@80052-1021
54
53
2

R381 *3G@10K_4
+3V_3G BOI

B1A C2A CN8

1 UIM_CLK
2
3 UIM_DATA
4
5 UIM_RST
6 UIM_VPP
7 UIM_PWR C314 [email protected]/10V_4
8
9
A 10 USBP7+ [13] A
1411 USBP7- [13]
1312

SIM CARD CO-LAY 3G@88511-120N

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
MINI CARD/TMA
Date: Monday, August 10, 2009 Sheet 20 of 34
5 4 3 2 1
 5 4 3 2 1

Power board
INT KeyBoard USB&FPC&CARDERAD CONNECTOR
C2A B1A
+3VPCU
CN3 PWR/B_LED#_Q
RP2
MX7 36
10 1 10KX8 CN9
F3B

3
MX0 9 2 MX6 R6
MX1 8 3 MX5 K_LED_P 0_4
1 1 ACZ_SDIN0_AUDIO [12]
MX3 7 4 MX4 MY16 ACZ_SDOUT_AUDIO [12]
2 MY16 [22] 2
MX2 6 5 PWR/B_LED# 2 Q2
3 3 [22] PWR/B_LED#
MY17
4 MY17 [22] 4 ACZ_SYNC_AUDIO [12]
5 5 ACZ_RST#_AUDIO [12]
K_LED_P *ME2N7002E
CP3 MX7 6 MY2 6
7 8 *220pX4 MY2 [22] BIT_CLK_AUDIO [12]

1
MX2 7 MY1 7
D 5
3
6
4 MX3 8 MY0 MY1 [22] 8 Bluetooth D

9 MY0 [22] 9 MIC_GND [17]

1 2 MX4 MY4 INT_MIC_R [17]
10 MY4 [22] 10
MY3 CN12
11 MY3 [22] 11
MY5

12
12 MY5 [22] 12 PCBEEP [14] 1
MY14
CP2 7 8 *220pX4 MX0 13
14
MY6
MY14 [22]
MY6 [22]
13
14
AMP_MUTE# [22]
USBOC#0_1 [13,22]
D3A 2
3
USBP2+ [13]
USBP2- [13]
5 6 MX5 MY7 CN2
3 4 MX6 15
16
MY13
MY7 [22]
MY13 [22]
15
16 USBP0+ [13] +3VPCU
(10mils) 1
4
5
WCS_CLK [20]
1 2 MX1 MY8 USBP0- [13] BT_RESET
17 MY8 [22] 17 [22] NBSWON# 2 6 BT_RESET [22]
MY9 PWR/B_LED#_Q
18
19
MY10
MY9 [22]
MY10 [22]
18
19 USBP1+ [13]
3
4
7
8
WCS_DAT [20]
+3V
0.18A(20mils)
MY11 USBP1- [13] BT_EN
20 MY11 [22] 20 9 BT_EN [22]
CP1 7 8 *220pX4 MY7 MY12 88513-044N

11
MY13 21 MY15 MY12 [22] 21 10
5 6
3 4 MY12 22
23
MX7
MY15 [22]
MX7 [22]
22
23
USB_EN#0_1 [22]
+3V
0.34A (20mils) 88266-10001-06
1 2 MY15 MX2
24 MX2 [22] 24
MX3 VDDIO_CODEC R176 *short_4
25
26
MX4
MX3 [22]
MX4 [22]
25
26
+1.5V 0.61mA (15mils)
MX0
27 MX5
MX0 [22] 27 +5V LED/TP/Hall Sensor Con.
CP4 7 8 *220pX4 MY3 28
29
MX6
MX5 [22]
MX6 [22]
28
29
1.008A(45mils)
5 6 MY5 MX1
3 4 MY14 30
31
K_LED_P
MX1 [22] 30
31
+5VPCU
B1A +5V
1 2 MY6 CAPSLED
32
33
FN_F10
CAPSLED [22]
FN_F10 [22]
32
33
3A (140mils) CN6
NUMLED R99
34 NUMLED [22] 34
35 18 18 +5V
CP5 7 8 *220pX4 MY2 MMC_LED# 17 +3VPCU *10K_4
MY1 36 17
5 6 35 37 PLTRST# [13,20,22,23] 16 16 +3V
3 4 MY0 15
MY4 38 15 ACIN [22,24] SATA_LED#_C HDDLED# Q18
1 2 196130-340201 USBP4+ [13] 14 MMBT3906_NL
39 14 PWRLED# [22]
USBP4- [13] 13 SUSLED_EC [22]
40 13
12 BAT_SAT0 [22]
88511-400N 12
11 BAT_SAT1 [22]
C
C333 *100p/50V_4 MY17 11 SATA_LED#_C
C
10
10 R76 10K_4
9
(10mils) 9
8
8 3G_WIMAX_LED#
RF_LED [22] +3V SATA_LED# [12]

+3V R7 150_4 K_LED_P 7 MMC_LED# TPDATA

C334 *100p/50V_4 MY16 7 TPDATA TPCLK
6 TPDATA [22]
6 TPCLK
5 5 TPCLK [22]
4 LID591# [17,22]
4 C213 C219
3 3
2 2
1 10p/50V_4 10p/50V_4
1

88511-180N

HOLE
CPU FAN F3B E3A
HOLE8 HOLE3 HOLE5 B1A

10

10
C2A HOLE6 HOLE7 7 6 HOLE2 HOLE4 HOLE1
7 6 7 6 8 5 7 6 7 6 7 6 7 6 7 6
8 5 8 5 9 4 8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4 9 4 9 4 3G_WIMAX_LED# D19 3G@BAS316 3G_LED#
3G_LED# [20]
1
2
3
1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3
D20 BAS316 WiMAX_LED#
WiMAX_LED# [20]
h-c197d142p2-8
h-c197d142p2-8 h-c197d142p2-8 *H-C276D98P2-8 *H-C276D98P2-8 *H-TC276BC236D98P2-8 *HG-TC240BO236X433D87P2 *O-BU3-2-PTH

B B

E3A F3B EMI

HOLE11 HOLE10 HOLE9 HOLE12 HOLE13 HOLE14 +1.5VSUS
E3A
1

C397 C396 C395 C394 C393 C392 C391 C390

*H-C154D91P2 *H-C154D91P2 *H-C154D91P2 *H-C154D91P2 *H-C154D91P2 *H-C154D91P2 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4

A A

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
KB/TP/PB/LEB/CON/HOL
Date: Monday, August 10, 2009 Sheet 21 of 34
5 4 3 2 1
 5 4 3 2 1

SM BUS PU
EC D3A
D22 *VPORT 0603 220K-V05
+3VPCU +3VPCU 0.01A(20mils)
+3VPCU
+3V
MBCLK R148 4.7K_4
L11 BLM18AG601SN1D_6 +A3VPCU +3V_VDD_EC R102 *short_6 MBDATA R147 4.7K_4
2ND_MBCLK R146 4.7K_4
C245 C251 C201 C188 2ND_MBDATA R152 4.7K_4
3ND_MBCLK R122 4.7K_4
0.03A(30mils) 0.1u/10V_4 10u/6.3V_8 0.1u/10V_4 10u/6.3V_8 3ND_MBDATA R121 4.7K_4

C348 C207 C234 C233 C252 C253 8769AGND

115

102
D D
R393 must close to C315 and

19
46
76
88

4
10u/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 U9 close to EC Pin100/102.
Routing 20/10/20
C2A I/O Base Address

VCC1
VCC2
VCC3
VCC4
VCC5

AVCC

VDD
H=1.6mm R135 100K/F_4
+3VPCU

[12,20] LFRAME# 3 97 MTEMP [24]

LFRAME AD0/GPI90 ICMNT
[12,20] LAD0 126
LAD0 AD1/GPI91
98 ICMNT [24] I/O Address
127 99 ACSET_EC
[12,20] LAD1
[12,20] LAD2 128
LAD1
LAD2 A/D
AD2/GPI92
AD3/GPI93
100
ACSET_EC [24] F3B BADDR1-0 Index Data
[12,20] LAD3 1 108 H_PROCHOT#_EC [3]
PCLK_591 LAD3 AD4/GPIO05
[2] PCLK_591 2
LCLK AD5/GPIO04
96 USBOC9# [13,18] 00 XOR TREE TEST MODE
95 NBSWON#
AD6/GPIO03 NBSWON# [21]
PCLK_591 8 94 01 CORE DEFINED
[14] CLKRUN# CLKRUN/GPIO11 AD7/GPIO07 SUSB# [14]

[12] GATEA20 121

GA20 10 2Eh 2Fh
101
R108 DA0/GPI94
[12] RCIN# 122
KBRST DA1/GPI95
105 VFAN [3] 11 164Eh 164Fh
D/A DA2/GPI96
106
SHBM=0: Enable shared memory with host BIOS
*22_4 D9 BAS316 SCI#_uR 29 LPC 107
[14] SCI# ECSCI/GPIO54 DA3/GPI97 SUSLED_EC [21]

[17] EC_FPBACK# 6
C197 LDRQ/GPIO24 BAT_SAT0 BADDR0 R124 *10K_4
GPIO41(VBAT)
80 BAT_SAT0 [21] BADDR0
124
*10p/50V_4 LPCPD/GPIO10 BT_EN R129 10K_4
GPIO GPIO42/TCK
17 RF_LED [21] BADDR1
[13,20,21,23] PLTRST# 7 20 AMP_MUTE# [21]
LRESET GPIO43/TMS RF_EN R142 10K_4
wake-up GPIO44/TDI
21 ID [24] SHBM
USB_EN#0_1 123 capability 25
[21] USB_EN#0_1 PWUREQ/GPIO67 GPIO50/TDO D/C# [24]
27 DISPON [17]
CIRTX2/GPIO52/RDY
[14,20] SERIRQ 125
SERIRQ
no wake-up GPO82/TRIS 110
BAT_SAT1 9 capability GPO84/BADDR0 112 BADDR0 Disabled ('1') if using FWH device on LPC.
[21] BAT_SAT1 SMI/GPIO65 Enabled ('0') if using SPI flash for both system BIOS and EC firmware
111 BT_EN
SOUT_CR/GPO83/BADDR1 BT_EN [21]
54 113
[21]
[21]
MX0
MX1 55
KBSIN0
KBSIN1 SER
SIN_CR/CIRRX/GPIO87
GPIO06
93
USB_SLEEP_EN#
LID591# [17,21]
[18] ID
[21] MX2 56
KBSIN2 +3VPCU
C
[21] MX3 57 32 CONTRAST [17]
C
KBSIN3 A_PWM/GPIO15 U10
[21] MX4 58 118
KBSIN4 B_PWM/GPIO21 USBOC#0_1 2ND_MBCLK
59 62 6 1
[21]
[21]
MX5
MX6 60
KBSIN5
KBSIN6
C_PWM/GPIO13
D_PWM/GPIO32
65
USBOC#0_1 [13,21]
2ND_MBDATA 5
SCL
SDA
A0
A1
2 0.003A(20mils)
[21] MX7 61
KBSIN7 PWM E_PWM/GPIO45
22 SUSON [27,31] A2
3
16 MAINON [9,19,27,28,29,31]
F_PWM/GPIO40/CLKIN48 PWR/B_LED#
[21] MY0 53 81 PWR/B_LED# [21] 7 8
KBSOUT0/JENK G_PWM/GPIO66 PWRLED# WP VCC
[21] MY1 52 66 PWRLED# [21] 4
KBSOUT1/TCK H_PWM/GPIO33 GND C261
[21] MY2 51
KBSOUT2/TMS AF24BC08-SI-TE1(DCEF)
[21] MY3 50
KBSOUT3/TDI 0.1u/10V_4
[21] MY4 49
KBSOUT4/JEN0 KB TA1/GPIO56
31 3G_P [20]
[21] MY5 48 63 FANSIG [3]
KBSOUT5/TDO TB1/GPIO14
[21] MY6 47
KBSOUT6/RDY TA2/GPIO20
117 WMAX_P [20] ADDRESS: A0H
[21] MY7 43
KBSOUT7 TIMER TB2/GPIO01
64 ACIN [21,24] Pin 117
[21] MY8 42 26 S5_ON [25]
KBSOUT8 TA3/GPIO51 AMD PWM 1.2V
[21] MY9 41 15 VRON [26]
KBSOUT9 TB3/GPIO36 INTEL WiMAX_P
[21] MY10 40
KBSOUT10
39
[21]
[21]
MY11
MY12 38
KBSOUT11
KBSOUT12/GPIO64 SPI_DI/GPIO77
84 BT_RESET [21]
SPI FLASH
+5V 37 SPI 83 RF_EN RF_EN [20]
[21] MY13 KBSOUT13/GPIO63 SPI_DO/GPO76/SHBM
[21] MY14 36 82
TPCLK KBSOUT14/GPIO62 SPI_SCK/GPIO75 +3VPCU
R150 10K_4
[21] MY15 35 91 DNBSWON#_uR D10 BAS316
DNBSWON# [14]
R149 10K_4 TPDATA KBSOUT15/GPIO61/XOR_OUT GPIO81
34
[21]
[21]
MY16
MY17 33
KBSOUT16/GPIO60
KBSOUT17/GPIO57 IRRX1/GPIO72/SIN2
75 RSMRST#
RSMRST# [14]
U16 0.025A(20mils)
FIR 73 SPI_SDI_uR R294 33_4 SPI_SDI 2 8
IRRX2_IRSL0/GPIO70 SUSC# [14] SO VDD
74 MPWROK
IRTX/GPIO71/SOUT2 MPWROK [6,14]
70 23 SPI_SDO_uR R291 33_4 SPI_SDO 5 7 C351
[24] MBCLK SCL1/GPIO17 CIRRXM/GPIO46/TRST SI HOLD
[24] MBDATA 69 14
SDA1/GPIO22 GPIO34/CIRRXL SPI_SCK_uR R292 33_4 SPI_SCK 0.1u/10V_4
[3] 2ND_MBCLK 67
SCL2/GPIO73 SMB CIR CIRTX1/GPIO16
114 NUMLED [21] 6
SCK WP
3
[3] 2ND_MBDATA 68 109 CAPSLED [21]
SDA2/GPIO74 CIRTX2/GPIO30 SPI_CS0#_uR
[19] 3ND_MBCLK 119 1 4
SCL3/GPIO23 CE VSS
[19] 3ND_MBDATA 120
SDA3/GPIO31 SPI_SDI_uR R295 10K_4 W25X16AVSSIG
[20] 3G_EN 24 86 +3VPCU
HWPG SCL4/GPO47 F_SDI/F_SDIO1 SPI_SDO_uR
28 87
SDA4/GPIO53 F_SDO/SDIO0 SPI_CS0#_uR
FIU F_CS0
90
92 SPI_SCK_uR
TPCLK F_SCK
[21] TPCLK 72
TPDATA PSCLK1/GPIO37
[21] TPDATA 71
B PSDAT1/GPIO35 B
10
11
PSCLK2/GPIO26
PSDAT2/GPIO27 PS/2 CLKOUT/GPIO55
30 LAN_P [23]
C2A
12
[21] FN_F10
13
PSCLK3/GPIO25
85 VCC_POR# R143 4.7K_4 INTERNAL KEYBOARD STRIP SET
F3B [17] BLPWM_SEL
8768_32KX1
PSDAT3/GPIO12 VCC_POR
VREF_uR
+3VPCU
R133 0_4 +A3VPCU +3VPCU
VCORF

77 104
32KX1/32KCLKIN VREF
AGND
GND1
GND2
GND3
GND4
GND5
GND6

R144 20M_6 8768_32KX2 79 MY0 R132 10K_4

32KX2
WPCE775CA0DG
5
18
45
78
89
116

103

44

R153

Y3 33K/F_4 +3V
VCORF_uR

1 4 HWPG
2 3
L12 0_6
C2A C255 32.768KHZ C257 R107
C230
15p/50V_4 15p/50V_4 10K_4
1u/10V_6

8769AGND 8769AGND [25] SYS_HWPG

D8 BAS316 HWPG

D7 BAS316
[28] HWPG_1.05V
D6 BAS316
[29] HWPG_1.8V
D5 BAS316
[6,27] HWPG_1.5V

LED
DNBSWON#_uR C250 *0.47u/10V_4
+3VPCU +3VPCU

NBSWON# SW1 *SHORT_ PAD PWRLED# R145 10K_4 PWR/B_LED# R151 10K_4
A
ACSET_EC
close to u9 A

R137 *10K_4 R154 *10K_4

ICMNT

SMBUS Table
SMBUS Devices Address C254 C256 USBOC#0_1
[13,21] USBOC0#
USBOC#0_1
[13,21] USBOC1#
1 Battery *10u/6.3V_8 *10u/6.3V_8
USB_EN#0_1 BAT_SAT0 R141 10K_4
CPU Thermal Sensor1 98H 8769AGND
[21] USB_EN#0
[21] USB_EN#1
USB_EN#0_1 BAT_SAT1 R106 10K_4 Quanta Computer Inc.
2
EC EEPROM A0H PROJECT : BU3
3 3D Sensor 40H Size Document Number Rev
D3B
EC-WPCE775CA0DG
Date: Monday, August 10, 2009 Sheet 22 of 34
5 4 3 2 1
 5 4 3 2 1

Atheros Lan Decoupling CAP Close to U3

DVDDL

+2.5V_LAN_R AVDDL12_R

C93 C79 C82 C88 C83 C92 C86 C89 C84

0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *1u/6.3V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4

D D

U3 (20mils)
C85 0.1u/10V_4 PCIE_RXN5_C 37 28 DVDDL C96 1u/6.3V_4
[13] PCIE_RXN5 TX_N DVDDL
C87 0.1u/10V_4 PCIE_RXP5_C 38 32 C114 10u/6.3V_8
[13]
[13]
PCIE_RXP5
PCIE_TXN5 44
TX_P
RX_N
DVDDL
DVDD_REG
45 Close to Pin45,46 0.262A(30mils)
43 46 C111 1u/6.3V_4
[13] PCIE_TXP5 RX_P DVDD_REG
40 1 LX/VDD18O C103 0.1u/10V_4
[2] CLK_PCIE_LAN# REFCLKN LX
[2] CLK_PCIE_LAN 41
REFCLKP LAN_VDD33 R43 0_6
2 +3V_S5
TWSI_SDA VDD33
30
TWSI_SCL TWSI_DATA VDD3V/CTRL12
29 5
TWSI_CLK VDD3V C94 1u/6.3V_4
SDATA_LAN 33 15 +2.5V_LAN
SCLK_LAN 31
SMDATA
SMCLK
VDDHO
AVDDH 19
+2.5V_LAN (15mils)
+2.5V_LAN_R R30 0_6

P L T R S T #
AVDDH 25
[13,20,21,22] PLTRST# 3
PERSTn

[14,20] PCIE_WAKE#
PCIE_WAKE# 4
WAKEn
Atheros AVDD_REG
VDD11_REG
11
8
16
AVDDL_LAN

AVDDL12_R R45 0_6 C98 0.1u/10V_4

AVDDL12
C102 C97
R38 2.37K/F_4 RBIAS AVDDL
12 22
RBIAS AVDDL C99 1u/6.3V_4 Close to Pin11 0.1u/10V_4 *1000p/50V_4
C
AVDDL 36 C
34 39 Close to Pin8
TESTMODE AVDDL LAN_AVDDL R36 0_6 LAN_VDD33
35 42
NO CONN
AR8132 AVDDL C91 0.1u/10V_4

C107 33p/50V_4 XTLI 10 SENSITIVE PIN! 6 AVDD_CEN

XTLI VDD17

2
4
PER FAE SUGGESTION,
XTLO RESERVE ONE BEAD FOR EMI. RP3
9 XTLO NC 24
2

Y1 23
SEL_25MHz NC *4.7KX2
7 21
SEL_25MHz NC Q9
20
NC

2
25MHz 18 TX1N *ME2N7002E
1

1
3
R40 TRXN[1] TX1P
49 GND1 TRXP[1] 17
C106 33p/50V_4 14 TX0N 3 1 SDATA_LAN
TRXN[0] [2,14] SDATA
*4.7K_4 13 TX0P
TRXP[0]
R26 0_4
47 R37 4.7K_4
LED_ACTn LAN_VDD33
48
LED_LINK10/100n
26
NC R28 *4.7K_4
27
CLKREQn
Q10

2
*ME2N7002E

3 1 SCLK_LAN
[2,14] SCLK
AR8132-AL1E-R
R20 0_4

B B

C2A
+3V_S5 LAN_VDD33 +3V_S5
E E P R O M

LAN CONNECTOR 1 3
PLACE NEAR LAN IC SIDE Q33 *AO3413
C388 C387 R383
Close to U3

2
+3V_S5 *4.7K_4
*0.01u/25V_4 *0.01u/25V_4
L3 4.7uh_C LX/VDD18O

C105 C109 R384 *3.01K/F_4

R21 (60mils) C2A
TX0N

TX1N
TX0P

TX1P

*0_6 0.1u/10V_4 10u/6.3V_8

(30mils)

3
CN4
Q32
TWSI_SDA AVDD_CEN AVDD_CEN 7
2 LAN_P [22]
1
2
4

2
4

TWSI_SCL TX1P
RN2 RN1 C100 TX1N 2 *DTC144EUA
C81 C80 3

1
49.9X2 49.9X2 0.1u/10V_4 TX0P 4
1
3

1
3

*0.1u/10V_4 *0.1u/10V_4 TX0N 5

6
VDD3V/CTRL12 8
A Pin5 88513-064N A

Close to U3 pin30 C104

When moun EEPROM 0.1u/10V_4
C95 C90
TWSI_SCL PU 4.7K_6
0.1u/10V_4 0.1u/10V_4

+2.5V_LAN R44 0_6

Quanta Computer Inc.
Pin15
PROJECT : BU3
Size Document Number Rev
D3B
Atheros Lan
Date: Monday, August 10, 2009 Sheet 23 of 34
5 4 3 2 1
 5 4 3 2 1

0.01_3720
C2A VA D3A PD4 PR81 PQ21 PQ19
PCN1 PF2
BUS-7A-1206
PL2
HI0805R800R-00_8
PDS1040S-13
1
R1 AP4435GM VIN AP4435GM

1 JACK 1 2 3 1 2 VA2 1 8 1 8 BAT-V

2 2 7 2 7
2 3 6 3 6
5 5

1
PC56 PC1 PC74 PR89 PC25 PC70 PR22
3 PL1 0.1u/50V_6 0.1u/50V_6 PD6 0.1u/50V_6 220K/F_6 0.1u/50V_6 2200p/50V_6

4
HI0805R800R-00_8 P4SMAJ20A 33K_6
4

2
D D
20288-044L 1 6 PR27
PD7 10K_6
PC19 PC9 PC2 1N4148WS PR93 2 5
0.1u/50V_6 0.1u/50V_6 220K/F_6
2200p/50V_6 3 4

3
PQ22
F3B IMD2AT108
CSIN_1 [22] D/C# 2

PR88 +3VPCU PQ3

82.5K/F_6 CSIP_1 2N7002K
B1A

1
VIN

[22] ACSET_EC
PR102 C2A
10K/F_6 PC37
1u/16V_6
PC39 PR35
10K_6 PR73 PR74
10u/6.3V_8 ACIN 10/F_6 10/F_6
[21,22] ACIN
PR78
PC66 4.7_6 PC68
0.1u/50V_6 1u/16V_6

PC63 PC62
CSIP CSIN 0.1u/50V_6 10u/25V_1206
PD5 PC32

33
32
31
30
28

27

26

21
C C

1
PC82 +3VPCU RB500V-40 2200p/50V_6

5
6
7
8
0.1u/50V_6

CSSP

VDDP
NC
GND
GND
GND
GND

CSSN

VCC
PR75 PC64
2.7_6 0.1u/50V_8 4
MBDATA 11 25 PQ2
VDDSMB BOOT AO4468
0.01_3720
MBCLK 9 24 PR71
PU2 SDA UGATE PL9
CM1293A-04SO PCMC063T-6R8MN

3
2
1
ID 1 6 MBDATA 10 23 1 2 BAT-V
CH1 CH4 SCL PHASE

5
6
7
8
2 VN VP 5 +3VPCU
13 20 PR8
TEMP_MBAT MBCLK ACOK LGATE
3 CH2 CH3 4
PC67 4 2.2/F_6 PC60
PR79 0.1u/50V_6 19 0.01u/50V_6
Add ESD diode base on EC FAE suggestion 49.9/F_6 C2A PGND
DCIN 22 PQ1
DCIN PR92 AO4710 PC5
PR77 10/F_6 2200p/50V_6 PC61
82.5K/F_6 18 CSOP CSOP_1 CSOP_1 2200p/50V_6

3
2
1
6251ACSET CSOP PC6 PC57
2 ACIN
+3VPCU BAT-V 10u/25V_1206 10u/25V_1206
PC75
PR84 3 0.1u/50V_6
VREF
B
22K/F_6
CSON 17 CSON BAT-V
B
PR2 PR1
*100K_4 10K_6 4 PR94
ICOMP 10/F_6
NC 16
PC17 PR98 0_4
5
F3B C2A NC
CN14 PF1 15 PR99 100_4 BAT-V
BUS-10A-1206 HI0805R800R-00_8 VBF
11 11 6 VCOMP
PL7 29
9 MBAT+ 100p/50V_6 BAT-V GND
1 2

GND
8

ICM
ID

NC

NC
7 ID [22]
PL6 PU3
6 TEMP_MBAT ISL88731
7

14

12
5 HI0805R800R-00_8
4
1

PC18 PR96
3 PC4 +3VPCU 2.21K/F_6
2 PC3 0.1u/50V_6
2

1
10 10 47p/50V_6 ICMNT [22]
BTJ-09HT0B PR13 47p/50V_6 PR28 PC79
100_4 *100K/F_6 0.01u/50V_6
PD1
PR12
100_4 MBDATA [22]
MTEMP [22]
MBCLK MBCLK [22] PC83
*SW1010CPT PC69 PC73 PC76 10u/25V_1206
1

*1u/16V_6 0.01u/50V_6 *0.01u/50V_6

1

PD2 PD3 PR17

A *100K/F_6 PC20 PR16 A
*ZD3.6V *ZD3.6V .01u/50V_6 0_4
2
2

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
CHARGER (ISL88731)
Date: Monday, August 10, 2009 Sheet 24 of 34
5 4 3 2 1
 5 4 3 2 1

PR125 0_4
[3] SYS_SHDN# 1 2

VIN
C2A C2A
D VIN VIN D
VL

1
VL

2
PD9
ZD5.6V PC100
Peak 8.521A,AVG 6.391A 4.7u/6.3V_6

1
1

1
Total capacitor : 160uF PR57 PC118 PC55 PC117
PR126 0_4 PR121 PR124 0.1u/50V_6 2200p/50V_6 10u/25V_1206
ESR : 25mΩ 39K/F_4 PC101 0_4 *0_4 (Peak 7.733A,AVG 5.801A)
PC113 PC114 PC112 PR118 PC99 1u/16V_6

2
f : 400k Hz 0.1u/50V_6 2200p/50V_6 10u/25V_1206 100K/F_4 0.1u/50V_6 Total capacitor : 150 uF

2
2
PC103

5
6
7
8
1u/6.3V_4 PC102 +3VPCU
OCP: 10A ESR : 25mΩ
0.1u/50V_6 PQ33

1
3V5V_EN REF AO4468 f : 500k Hz
C2A

1
8
7
6
5
3V_DH 4
+5VPCU PR120 *0_6 Modified on 04/08 OCP : 9.5A
PR119
4 200K/F_4

8
7
6
5
4
3
2
1
PQ30
C2A AO4468
C2A PL13

LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF
2R2uH/8A_7X7X3

6 3
7 2
8 1
+3VPCU

5
PR128
C2A +5VPCU
9 32 REFIN2 196K/F_6

1
2
3
PL14 BYP REFIN2 PR145
10 OUT1 ILIM2 31 1 2
C 2R2uH/8A_7X7X3 11 30 4 *4.7_6 C
+5VPCU FB1 PU7 OUT2 SKIP
1 2 12 ILIM1 SKIP# 29
PR134 196K/F_6 DDPWRGD_R 13 ISL6237 28 DDPWRGD_R PQ35
PGOOD1 PGOOD2
2

8
7
6
5 3V5V_EN 14 EN1 EN2 27 3V5V_EN AO4710 PR135 +
PR129 5V_DH 15 26 0_6
*0_4 PR144 5V_LX DH1 DH2 3V_LX PC120 PC106 PC110
16 LX1 LX2 25
*4.7_6 4 5V_DL 37 *680p/50V_6 0.1u/50V_6 150U/6.3_3528

3
2
1
+ PAD
36
1

PAD

PGND
PVCC
PC115 PQ34

BST1

BST2
GND
PAD
PAD
PAD

DL1

DL2
AO4710 PC107 PC105

NC
1 2
2

PC116 PC119 0.1u/50V_6 0.1u/50V_6 PR137 *0_4

150U/6.3_3528 PR130 *680p/50V_6 PR139 1 2

35
34
33

17
18
19
20
21
22
23
24
0_4 PR140 1/F_6 PR132 0_4
1
2
3

1/F_6 1 2
1 2 3V_DL
1

PR131
PC54 0.1u/50V_6 *0_6

2
10u/25V_1206 VL PR58 SKIP PR59 *0_6 REF

2
PC111 0_6 PR60
2 0.1u/50V_6 PR141 0_4 PR133 0_4
*0_4 PC108 1 2
PR142 3 1u/16V_6

1
PD10 PR136 10K/F_6
+10V
B1A

1
1 CHN217
AO4710 Rdson=11.8~14.2mOhm +3VPCU

L(ripple current)
22_8 AO4710 Rdson=11.8~14.2mOhm
PC109 DDPWRGD_R 1 2
=(19-5)*5/(2.2u*400k*19) 0.1u/50V_6 +3VPCU OCP:4.5A 500K SYS_HWPG [22]
~4.187A PR138 0_4
B L(ripple current) B
Let Iocp = 10A =(19-3.3)*3.3/(2.2u*500k*19)
( 10 - 4.187 / 2 ) * 14.2mohm = ( R * 5uA ) / 10 ~2.479A Let Iocp = 9.5A
R(Ilim) = 225Kohm ( 9.5 - 2.479 / 2 ) * 14.2mohm = ( R * 5uA ) / 10
R(Ilim) = 235Kohm

MAIND
MAIND [27,31]
VIN +3V_S5 +5V_S5 +10V +3VPCU +5VPCU

+5VPCU
+3VPCU F3B F3B
Modified on 04/16

Modified on 04/16 PR67 PR68 PR61 PR143 PC150

1M_6 22_8 22_8 1M_6 *2200p/50V_4 PC151

5
6
7
8

3
*2200p/50V_4
F3B F3B PQ32
PC149 AO4468
PC148 *2200p/50V_4 S5D 4 S5D 2
*2200p/50V_4
5
6
7
8

3
PQ29
PQ27 F3B 2N7002K
AO4468 2 PC147
[22] S5_ON

1
MAIND 4 MAIND 2 2 2 2 *2200p/50V_4

3
2
1
PR65 PQ17 PQ12 PQ31
1

PQ28 PR64 PQ16 1M_6 DMN601K-7 DMN601K-7 DMN601K-7 +5V_S5

A AO3404 100K/F_4 DTC144EU +3V_S5 A
1

1
0.002A
2.567A
3
2
1

Modified on 04/08

+5V
+3V
Quanta Computer Inc.
3.21A
3.014A PROJECT : BU3
Size Document Number Rev
D3B
SYSTEM 5V/3V (ISL6237)
Date: Monday, August 10, 2009 Sheet 25 of 34
5 4 3 2 1
 5 4 3 2 1

D3A +1.05V

PR149

*10K/F_4
31
PR87 *Short_4
VR_PWRGD_CK410# [14]
PR148 0_4
H_DPRSTP# [3,6,12]
PR83 499/F_4
D DPRSLPVR [6,14] VID 1.0V D
PR43 10K/F_4
PR33 *0_4 H_VID0
PR41 *Short_4
+3V VRON [22]
PR42 *0_4 H_VID1
H_VID6 [4]
PC38 1u/16V_6
H_VID5 [4]
PR32 *0_4 H_VID2
PR45 *Short_4
[3,6,14] DELAY_VR_PWRGOOD H_VID4 [4]
PR39 1.91K/F_4 PR29 0_8 PR40 *0_4 H_VID3
+3V H_VID3 [4] +3VPCU

D3A H_VID2 [4]

PR34 *0_4 H_VID4

41

40

39

38

37

36

35

34

33

32

31
H_VID1 [4]
PU1
PR37 *0_4 H_VID5
For ISL6261 mount PR113 0_0402

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3
GND_PAD

PGOOD

DPRSLPVR

VR_ON
H_VID0 [4] +3VPCU

PR147 *0_4 PR38 *0_4 H_VID6

+5V_S5 DPRSLPVR PR146 0_4 1 30

FDE VID2
PR86 *0_4
PR80 *6.81K/F_4 2 29
PMON VID1
VIN
PC65 *0.1u/50V_6

1
PR76 147K/F_4 3 28 +5V
RBIAS VID0
C PR72 *10K/F_4 PR30 1_8 PC33 C

2
+3VPCU 2.2u/6.3V_6
[3] H_PROCHOT# 4 VR_TT# Pin 41 is GND Pin VCCP 27

PR31 4.02K/F_4 PR85 470K/NTC_4 5 26 PC13 PC12 PC59

NTC LGATE 10u/25V_1206 10u/25V_1206
PC35 10n/25V_6 ISL6261A QFN 40 6X6 0.1u/50V_6
6 SOFT VSSP 25
PC34 15n/25V_4

6261AVO PR25 8.06K/F_4 7 24 PC27 0.22u/25V_6 Peak 18A,AVG 15A

B1A OCSET PHASE
For 1.5uF 0801 PC30 1000p/50V_4 Total capacitor : 440uF
PC122 220p/50V_4 8 23
PR23 6.81K/F_4 VW UGATE
ESR : 4.5mΩ
C2A

5
PC26 1000p/50V_4 f : 300k Hz
PC121 220p/50V_4 9 22 PR21 2.2/F_6
PC21 82p/50V_4 COMP BOOT PQ18
PR24 332K/F_4 PC23 120p/50V_4 AOL1448
OCP: 20A
4
10 21 PL8
FB NC

1
5 2
3
For 1.5uF 0801 +VCC_CORE
1uH
DROOP

VSUM
VDIFF

VSEN

VDD
RTN

DFB

VSS

1
VIN
VO

PQ20 PR10 PR5

B1A 4 AOL1718 *Short_4 *Short_4 + + +
PR20 1.5K/F_4
11

12

13

14

15

16

17

18

19

20 For 1.5uF 0801

1
2
3

2
PR18 1.62K/F_4 PC24 1200p/50V_4 PR19 10/F_6 +5V PR26
6261ADROOP

*2.2/F_6
6261AVSUM

B PC22 1 2 1u/10V_6 B
6261ADFB

6261AVO

PC28 PC46
For 1.5uF 0801 220u/2V_7343 PC29 *220u/2V_7343
PC31 220u/2V_7343
PR15 10/F_6 *2200p/50V_6
VIN
PC14 PC15 0.1u/50V_6
1000p/50V_4

PC10 PC7 C2A B1A

6261AVSUM PR11 7.68K/F_4
1000p/50V_4 330p/50V_4

PR7 PR70 *3.57K/F_4

PC16 PC8 3.24K/F_4
0.1u/25V_4 0.047u/25V_4 PR69 10K/NTC_6 Rfset(Kohm) = ( period(us) - 0.29) * 2.33
PR14 *Short_4
VCCSENSE [4]
6261AVO PR6 0_4 Period(us) = Rfset(Kohm) / 2.33 +0.29 = 3.213 * 10^ -6 s
PR9 *Short_4
VSSSENSE [4] Frequency = 1 / (3.213 * 10^ -6) = 311K
For 1.5uF 0801
PR3
1K/F_4
L(ripple current)
6261ADFB
=(19-1)*1/(1.0u*311k*19)
PC11 PC58 ~3.05A
330p/50V_4 0.22u/25V_8
PR4 Rocset = ( Ioc * Rdroop) / 10uA
B1A 3.09K/F_4
Rdroop = 4mV/A
A Ioc = Rocset * 10uA / Rdroop = 20.15A A
6261ADROOP

For 1.5uF 0801

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
POWER_CPU CORE (RT8152B)
Date: Monday, August 10, 2009 Sheet 26 of 34
5 4 3 2 1
 5 4 3 2 1

PC84
2A 10u/10V_8
+SMDDR_VTERM
PR100 0_6 C2A
PC77 0.1u/50V_6
VIN
1.8V_H
PC45 PC86
10u/10V_8 10u/10V_8 1.8V_LX Modified on 04/08
D D
1.8V_L

5
PQ5
AOL1448 PC43 PC44 PC81

25

24

23

22

21

20

19
4
2200p/50V_6 10u/25V_1206
10u/25V_1206

LL

DRVL
GND

VTT

VLDOIN

VBST

DRVH

1
2
3
PL10
1.5UH +-20% 13A_10x10x4 C2A
+1.5VSUS

1 VTTGND PGND 18 12.2A

2 17 + +
VTTSNS CS_GND PR82 5.62K/F_6
B1A

5
3 TPS51116REGR 16
GND PU4 CS PR36
DIS_MODE PQ4
+SMDDR_VREF 4 MODE V5IN 15
4 AOL1718 *2.2/F_6
OCP: 14.4A
C 5 14 PC80 C
VTTREF V5FILT +5VPCU
PC78 PC41 10u/10V_8

1
2
3
+5VPCU 6 13 PR44 5.1/F_6 220u/2.5V_3528 220u/2.5V_3528
COMP PGOOD

1
VDDQSNS

VDDQSET
Del PR23 0_6 2009/03/02 PC72 PC71
1u/6.3V_4 1u/6.3V_4 PC36

2
*2200p/50V_6
NC

NC
PC85 Peak 12.2A,AVG 10A
S3

S5
0.033u/50V_6 PR90 +3VPCU
100K/F_6 Total capacitor : 440uF
7

10

11

12
FOR DDR II HWPG_1.5V [6,22]
ESR : 10.5mΩ
PR91 For RT8207 400KHZ f : 400k Hz
VIN
620K/F_4
PR46 S5_1.8V PR95 0_4
PR101 *0_6
SUSON [22,31] OCP: 14.6A
0_4 S3_1.8V PR97 0_4
MAINON [9,19,22,28,29,31]
Edited for DDR3
+5VPCU
B AO4710 Rdson=3.4 ~ 4.3mOhm B

+1.5VSUS
F3B L(ripple current)
Vout = (PR104/PR103) X 0.75 + 0.75
PR47
10K/F_4
PR48 =(19-1.5)*1.5/(1.5u*400k*19)
10.2K/F_4 ~2.303A
PC152
MAIND *2200p/50V_4
MAIND [25,31] Vtrip(mV)=RILIM*10uA

5
6
7
8
(10u*PR82)/Rdson+Delta_I/2=Iocp
MAIND 4
PQ26
Let Iocp = 14.6A
DIS_MODE
PR50 AO4468 (Iocp - Delta_I / 2) * Rdson / 10u
*0_6 S5_1.8V S3_1.8V
PR82 = 5.78Kohm
PR49 0_4
+1.5VSUS
A Added on 04/08 A

3
2
1
PC40 PC42
*0.1u/50V_6 *0.1u/50V_6 Quanta Computer Inc.
PROJECT : BU3
+1.5V
Size Document Number Rev
D3B
DDR 1.8V(TPS51116)
Date: Monday, August 10, 2009 Sheet 27 of 34
5 4 3 2 1
 5 4 3 2 1

C2A
VIN
+5VPCU
PR56

10_6 PD8 E3A

5
D D
RB500V-40
PQ8
PC89 FDMC8884

1
PR110 PC90
1M_6 *0.1u/50V_6 4
4.7u/6.3V_6

2
PR109 PR107 PC49 PC48
*10K/F_6 0_6 0.1u/50V_6 10u/25V_1206

3
2
1
PR111 0_6 PC92
15 13 0.1u/50V_6
[9,19,22,27,29,31] MAINON EN/DEM BOOT C2A OCP: 10A
+3V 16 12 UGATE-1V PL11
PC93 TON UGATE 2R2uH/8A_7X7X3
*0.1u/50V_6 1 11 PHASE-1V
VOUT PHASE PQ9 +1.05V
2 10 PR105 4.7K/F_6 FDMC8296
VDD OC D3A

5
PR104 PU5
10K/F_6 3 UP6111AQDD 9 C2A 1.05V
FB VDDP PR53 + PR106
C C
[22] HWPG_1.05V 4 PGOOD LGATE 8 LGATE-1V B1A
2.2/F_6 PC91
6 7
4
PC88
R1 *33p/50V_6
GND PGND 220u/2.5V_3528 4.02K/F_6
5 17
Rds*OCP=RILIM*20uA

3
2
1
NC TPAD PC47
14 NC
E3A 2200p/50V_6
1

PC50 PC95 PC94 PC87 PR103

10u/10V_8 10K/F_6
R2
2

1u/16V_6 *1000p/50V_6 0.01u/50V_6

1V_FB
VOUT=(1+R1/R2)*0.75

B (Peak 21.199A,AVG 8A) B

FDMC8296 Rdson= 8 mOhm
Total capacitor : 230 uF
TON=3.85p*RTON*Vout/(Vin-0.5) ESR : 21mΩ
TOFF = (Vin / Vout -1)* Ton L(ripple current) f : 253k Hz
TON = 2.185* 10^ -7 =(19-1.05)*1.05/(2.2u*253k*19)
TOFF = 3.736 * 10 ^ -6 ~1.78A OCP :10A
Frequency = 1 / (Ton + Toff) ~ 253K
Let Iocp = 10A
Iocp - Iripple / 2 = RILIM * 20u /Rdson
10 - 1.78 / 2 = RILIM * 20u / 8mohm
RILIM = 3.644Kohm
A A

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
VCCP 1.05V(UP6111AQDD)
Date: Monday, August 10, 2009 Sheet 28 of 34
5 4 3 2 1
 5 4 3 2 1

D D

+3V_S5

1
PR127
100K_4
+5V_S5

2
PC96 PU6
.1u/50V_6 RT9025-25PSP
4 VPP PGOOD 1 HWPG_1.8V [22]
PS1 SHORT 0 0603
C
[9,19,22,27,28,31] MAINON 2 VEN VO 6 +1.8V C

+3V_S5 3 VIN 0.12A

8 GND

ADJ
9 GND NC 5
PR123
PC51 PC98 PC104 43K/F_4 PC97

7
10u/10V_8
10u/10V_8 .1u/50V_6 *.1u/50V_6
0.8V

PR122
34K/F_6

Vout =0.8(1+R1/R2)
B =1.8V B

A A

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
VCCP 1.05V(UP6111AQDD)
Date: Monday, August 10, 2009 Sheet 29 of 34
5 4 3 2 1
 A B C D E

+3VPCU
+3VPCU
E3A
4 4

PR150 PR151 PR152 PR153 PR154

*45@0_6 *45@0_6 *45@0_6 *45@0_6 *45@0_6

GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 GPU_VID0

+3V
PR155 45@0_4
2 1 GFX_VR_EN

1
PR156
[email protected]/F_4 PC123
*[email protected]/50V_6

2
PR157
45@10K_4
GPU_VID4 [6]

GPU_VID3 [6]

GPU_VID2 [6]

GPU_VID1 [6]

GPU_VID0 [6]

33

32

31

30

29

28

27

26

25
VID4

VID3

VID2
PAD

PGOOD

AF_EN

VR_ON

PMON
FDE
PR158
3 45@150K/F_4 E3A VIN
3
1 24
RBIAS VID1

1
PC124 PQ36 Peak 8A,AVG 6A
PR159 2 1 2 23 +5V_S5 45@FDMC8884

2
[email protected]/F_6 SOFT VID0
PC129 Total capacitor : 220uF
[email protected]/16V_4 4
PC130 +1.05VGFX_CORE_INT 3 PU8 22 1 2 ESR : 21mΩ
45@68p/50V_4 OCSET PVCC PC125 PC126 PC127 PC128 f : 293k Hz
PC131 PR160 45@ISL6263A [email protected]/6.3V_6 45@2200p/50V_6 [email protected]/[email protected]/25V_8 [email protected]/50V_6

3
2
1
[email protected]/F_6 4 21 ISL6263A_LGATE OCP: 11A
VW LGATE
PR161 45@374K/F_6 PC132 45@180p/50V_4 45@1000p/50V_4 F3B
5 20
COMP PGND PL15
45@1UH 20%11A PR183 45@0_1206
6 19 ISL6263A_PHASE +1.05VGFX_CORE_INT
FB PHASE
PR162 [email protected]/F_4 E3A PQ37 F3B PR184 45@0_1206

5
7 18 ISL6263A_UGATE 45@FDMC8296
VDIFF UGATE +
PC133

1
8 17 1 2 PR164
VSEN BOOT
DROOP

4 *[email protected]_6

2
VSUM
PR163 45@1/F_6

VDD
RTN

VSS
DFB

[email protected]/25V_6

VIN
VO

2
PR165 PC134

3
2
1
[email protected]/F_4 45@560p/50V_4 PR166
9

10

11

12

13

14

15

16
45@10/F_6 PC137 PC135 PC136
+5V_S5 *45@2200p/50V_6 [email protected]/50V_645@220u/2.5V_3528

PC138
PC139
F3B 45@1u/6.3V_4
45@1000p/50V_4 PR167
PC140 [email protected]/F_4

45@1000p/50V_4 VIN
2 2
PC142
1

PR169 PC141 45@330P/50V_4 PR168

*45@10/F_4 45@1000p/50V_4 45@10/F_6
+1.05VGFX_CORE_INT PC143
2

[email protected]/50V_6
PR171
PR170 ISL6263A_VSUM
PR172 45@0_4 45@1K/F_4
[email protected]/F_4
[8] VCC_AXG_SENSE
PR173
PR174 45@0_4 [email protected]/F_4
[8] VSS_AXG_SENSE
E3B
PR175
Parallel [email protected]/F_4
1

PR176 PC144
*45@10/F_4 [email protected]/50V_6 PR177
45@10K _6 NTC
2

PR178 45@0_8

PC145
*[email protected]/10V_4 PC146
[email protected]/10V_4

Rfset = 1 / (( T - 0.29*10^-6 ) * 47)

Rfset = 6.81K, T = 3.414 * 10^-6 s
VIN
F = 1/ T = 293KHz
+1.05VGFX_CORE_INT

L(ripple current)
PR179 PR180 =(19-1.05)*1.05/(1.0u*293k*19)
45@1M_6 45@22_8
~3.86A
GFX_VR_EN_G Rocset = ( Ioc * Rdroop) / 10uA
1 1
3

Rdroop =7mV/A Rocset = 8.06K

3

Ioc = Rocset * 10uA / Rdroop =11.5A

PR181
GFX_VR_EN 2 45@1M_62
[6] GFX_VR_EN
PQ39
1

PQ38 45@DMN601K-7
1

PR182 45@DTC144EU
1

45@100K_4

Quanta Computer Inc.

2

PROJECT : BU3
Size Document Number Rev
D3B
1.05V_GFX (ISL6263A)
Date: Monday, August 10, 2009 Sheet 30 of 34
A B C D E
 5 4 3 2 1

D D
VIN +1.5VSUS +10V

PR116 PR55 B1A PR66

1M_6 *22_8 *1M_6

SUS_ON_G

3
3
PR117
2 1M_6 2 2
[22,27] SUSON PC53
PQ11 PQ15 *2200p/50V_4
PQ25 *DMN601K-7 *DMN601K-7

1
PR113 DTC144EU

1
100K/F_4

VIN +3V +5V +1.05V +1.5V +SMDDR_VTERM +10V

C PR115 PR108 PR63 PR52 PR54 PR51 PR62 C

1M_6 22_8 22_8 *22_8 *22_8 *22_8 1M_6

MAINON_ON_G MAIND
MAIND [25,27]

3
3
PR114
2 1M_6 2 2 2 2 2 2
[9,19,22,27,28,29] MAINON PC52
PQ23 PQ14 PQ7 PQ10 PQ6 PQ13 *2200p/50V_4
PQ24 DMN601K-7 DMN601K-7 *DMN601K-7 *DMN601K-7 *DMN601K-7 DMN601K-7
1

PR112 DTC144EU

1
100K/F_4

B B

A A

Quanta Computer Inc.

PROJECT : BU3
Size Document Number Rev
D3B
Discharge/1.5/2.5V
Date: Monday, August 10, 2009 Sheet 31 of 34
5 4 3 2 1
 5 4 3 2 1

MODEL BU3
Model REV CHANGE LIST PAGE FROM To

1 1A 1B
PAGE 2: add RP21 value 3G@0X2 ,add net name CLK_PCIE_3G to 3G Card pin13 & CLK_PCIE_3G# to 3G Card pin11 2 1A 1B
B1B PAGE 13: Add net name PCIE_RXN3,PCIE_RXP3,PCIE_TXN3,PCIE_TXP3 to 3G connector 3 1A 1B
BU3 MB PAGE 13: Add C386,C382 both value [email protected]/10V_4 4 1A 1B
PAGE 13: del USB5-,USB5+ net 5 1A 1B
D
PAGE 13: add USB7-,USB7+ net to sim connector 6 1A 1B D
PAGE 18: del HDMI function U17,R298,R299,R303,R305,R307,R309,R320,R323,R308,R306,R304,R310,R319,R317,R302,R297,R296,R312,R157 7 1A 1B
PAGE 18: del HDMI function C365,C369,C356,C354,Q28,RN,4,RN5,RNN6,RN3,L20.L21.L22.L23,Q28 8 1A 1B
PAGE 20: change Q20 PIN 2 net neme +3V_S5 to WIMAX_P 9 1A 1B
PAGE 20: change Q22,Q27 PIN 1 net neme +3V_S5 to +3VPCU 10 1A 1B
PAGE 20: Add R380 value 0_8 between net +1.5V and net +1.5V_3G. 11 1A 1B
PAGE 20: Add C383 value 0.01V/25_4,C384 value 0.1/10V_4,C385 value 10u/3.6V_8 between net +1.5V_3G and GND 12 1A 1B
PAGE 20: change R253,R250 power source +3V_S5 to +3VPCU 13 1A 1B
PAGE 20: Connect CN21 PIN 48,PIN 28,PIN 6 to +1.5V_3G 14 1A 1B
PAGE 20: Add CN23 value 3G@88266-10001-06 for co-lay SIM card 15 1A 1B
PAGE 20: CN21 Connect PIN 33 to PCIE_TXP3,Connect PIN 31 to PCIE_TXN3,Connect PIN 25 to RCIE_RXP3,Connect PIN 23 to PCIE_RXN3 16 1A 1B
PAGE 20: Add Q31 value 3G@ME2N7002E,R296 value 3G@10K_4 for PCIE_WAKE to CN21 PIN 1 17 1A 1B
PAGE 18: Change CN11 pin define to PORT-B_HPD# 18 1A 1B
PAGE 21: Change CN6 footprint and pin define 19 1A 1B
PAGE 2: Change CLOCK GEN SRC6 net CLK_PCIE_3G and CLK_PCIE_3G# for 3G card 20 1A 1B
PAGE 2: Change CLOCK GEN SRC4 net CLK_PCIE_MINI1 and CLK_PCIE_MINI1# for mini card 1 21 1A 1B
PAGE 20: Change D15 to R297 value 0805 ohm 22 1A 1B
PAGE 21: Remove CN13 23 1A 1B
PAGE 7: Change R116 value to 12.1K ohm, Add U17 for DDR3_POWER_OK 24 1A 1B
C PAGE 25: Change PR134 value to 169K ohm, change PR128 value to 174K phm . NC PR141 25 1A 1B C

PAGE 26: Change PR25 value to 8.06k ohm ,change PR20 value to 1.5K ohm ,change PR4 value to 3.09K ohm ,change PR7 value to 3.24k ohm. 26 1A 1B
PAGE 27: Change PR82 value to 5.9k ohm 27 1A 1B
PAGE 27: Change PR105 value 9.31K ohm , NC PC91 28 1A 1B
PAGE 27: NC PR66,PQ15 29 1A 1B
PAGE 20: Change CN22 footprint to minipci-80019-1021-52p-ruv-v ,chabge CN23 footprint to minipci-80052-1021-52p-ldv-v 30 1A 1B
PAGE 21: Change HOLE 4 module
PAGE 6: Change R116 value 12.1K/F_4 , add R378 & U22 for DDR3_POWER_OK
PAGE 6: Change CN6 pin define.
PAGE 27: Change PR82 value to 5.62K ohm
PAGE 2: Swap vertical RP11,RP21
PAGE 15 : Change R227 value to 100/F_6
PAGE 19 : Change U6 value to GS@R5F211B4D31SP#W4(0217H)
PAGE 14 : Add R382 to +3V_S5 for ICHP SCI#
PAGE 17 : Change T79,T80,T82,T84,T83,T86, footprint to TP3050
PAGE 20 : Add D19,D20 for 3G_LED# & WiMAX_LED# between CN6 PIN 8 3G_WIMAX_LED#
PAGE 21 : Change CN9 PIN 33 DEFINE for MMC_LED#,change CN6 footprint 18pin
PAGE 22 : Add R135 for battery state issue.
PAGE 23 : Add Q33 Q32 C388 R383 R384 for LAN_P soft start, change CN4 pin define.
B
C2A PAGE 20 : change CN21 CN22 footprint
B

PAGE 20 : remove CN13 and change CN8 connector module

PAGE 14 : R191 always pull high for HDMI & USB BOI-FUNCTION
PAGE 18 : Change CN11 PIN11 net to BOARD_ID4
PAGE 28 : remove PL5 ,remove JP3, short by trace.
PAGE 27 : remove PL4 ,remove JP2&JP1 , short by trace.
PAGE 25 : remove PL12 &PL15,remove JP5 & JP4, short by trace.
PAGE 24 : remove PL3 ,short by trace.
PAGE 26 : PC8 change to CH3474K1B04 CAP CHIP 0.047U 25V(+-10% X7R 0402)
PAGE 21 : Change CN9 PIN 24 net to 1.5V
PAGE 22 : Add R135 for battery leakage current
PAGE 26 : Add PU1 PIN8 & PIN9 PC121,PC122 CAP CHIP 220P 50V(+-10%,X7R,0402) to GND SINGAL
PAGE 9 : Add C389 value 10u/6.3V_8, and change C187 value to 22u/6.3V_8 for CRT power noise issue,(reserve U23)
PAGE 24 : Change PU3 Part number to AL088731001
PAGE 22 : Change C255 and C257 value to 15p/50V_4
PAGE 14 : Change R156 Part Number to CS23243F930
PAGE 12 : Add R385 ,R386 for USB-ODD CO-LAY.(reserve)
PAGE 24 : Change PD4 Footprint to d-5_375-3_975 for OPEN issue
A D3A PAGE 21 : Change CN2 PIN1 NET from +5VPCU to +3VPCU A

PAGE 20 : Change R379 value to 100K_4 for WIFI INTEL module issue
PAGE 13 : Add R388,R389 for reserve gemalto 3G sim card
PAGE 18 : Reserve D21 and R387 to keep voltage 0.4 V

PROJECT MODEL : BU3 APPROVED BY: Mosy Li DATE: 2009/04/27 Quanta Computer Inc.
DOC NO. 204 PROJECT : BU3
PART NUMBER: 31BU3MB0000 DRAWING BY: Mosy Li REVISON: 1B Size Document Number Rev
D3B
Change list
Date: Monday, August 10, 2009 Sheet 31 of 33
5 4 3 2 1
 5 4 3 2 1

MODEL BU3
Model REV CHANGE LIST PAGE FROM To

1 1A 1B
PAGE 26: Add PR146,PR147,PR148 value 0_4 ,PR149 value 10K/F_4 for power suggest 2 1A 1B
D3A PAGE 22: Add D22 for ESD/EOS suggestion  - Power pin EOS 3 1A 1B
BU3 MB PAGE 22: C386,C382,RP21不 不不不 4 1A 1B
PAGE 02: change C373,C374 value to 33p/50V_4 for XTAL report 5 1A 1B
D
PAGE 20: reserve Q31,R381,R380,C383,C384,C385 6 1A 1B D
PAGE 17: reserve CRT FILTER R390,R393,R394,C398,C399,C400,C401,C402,C403 for EMI requirement. 7 1A 1B
E3A PAGE 21: add C390,C391,C392,C393,C394,C395,C396,C397 for EMI requirement . 8 1A 1B
PAGE 30: add 1.05v_GFX SCHEMATIC for reader stand by function (GS45 only) 9 1A 1B
PAGE 28: change PQ8 and PQ9 value and footprint . 10 1A 1B
PAGE 17: Add R3,R2 BOI-OPTION for GS40. 11 1A 1B
PAGE 17: Add R392 ,R391 for Board ID3 12 1A 1B
PAGE 21: Add HOLE 9,HOLE 11, HOLE 10. 13 1A 1B
PAGE (12) :Change R244 to bead 120ohm, C324 to 22PF for EMI requirement. 14 1A 1B
F3A PAGE (24) : Add PR88, PR35 for Adapter Voltage monitor 15 1A 1B
PAGE (17) : Reserve U25 for LVDS_VADJ option (support XP function key). 16 1A 1B
PAGE (25) : Reserve PC147,PC148,PC149,PC150,PC151,PC152 for power soft start 17 1A 1B
PAGE (21) : Change CN9 connector pin define to 40 pin 18 1A 1B
PAGE (17) : Change D1 footprint 19 1A 1B
PAGE (18) : Change HDMI CN11 connector PIN DEFINE 20 1A 1B
PAGE (22) : R176,RP7,RP8,L2,R138,R161,R377,R199,R251,R351,R213,R225,R211,R373,R357,R240,R212,R217,R175,R342,R155,R48,R59,R112,R111,R130,R131,R288,R284,R62,R91,R41,R134 replace by short pad 21 1A 1B
PAGE (22) : R378,R68,R279,R12,RP17,RP15,RP16,RP14,RP13,RP12,RP11,RP10,RP9,R293,R8 replace by short pad 22 1A 1B
PAGE (22) : Change CN9 pin define. 40PINS 23 1A 1B
PAGE (30) : Change PL15 from 2.2uH to 1uH , PC145 change to unmounted , PR167 change to 1.54K , PC136 should be mounted for 3D hang up issue. 24 1A 1B
C PAGE (09) : reserve C186,C149,C269,C247,C113,C342,C154,C135 for cost down 25 1A 1B C

26 1A 1B
27 1A 1B
28 1A 1B
29 1A 1B
30 1A 1B

B B

A A

PROJECT MODEL : BU3 APPROVED BY: Mosy Li DATE: 2009/04/27 Quanta Computer Inc.
DOC NO. 204 PROJECT : BU3
PART NUMBER: 31BU3MB0000 DRAWING BY: Mosy Li REVISON: 1B Size Document Number Rev
D3B
Change list
Date: Monday, August 10, 2009 Sheet 32 of 33
5 4 3 2 1
 5 4 3 2 1

Power Tree VCC_CORE +-3% +5V_S5 +-5%

Table 2 VRON enable 6 S5_ON enable
ISL6261A 2N7002K
1 P.26 (Peak 18A,AVG 13.5A) OCP 18A P.25 (Peak 0.002A,AVG 0.001A)
D
AC System D

Charger +5V +-5%

ISL88731 7 MAINON enable
DC P.24 +5VPCU +-5% AO4468
AC/DC Insert enable P.25 (Peak 4.019A,AVG 3.014A)

(Peak 8.52A,AVG 6.391A) OCP 8A

3
ISL6237
P.25
+3VPCU +-5% +3V +-5%
C
AC/DC Insert enable 8 MAINON enable C

AO3404
(Peak 7.733A,AVG 5.8A) OCP 7A P.25 (Peak 3.423A,AVG 2.567A)

+3V_S5 +-5% +1.8V +-5%

+1.05V +-5% 9 S5_ON enable 10 MAINON enable
MAINON enable
4 AO4468 RT9025
UPI6111A P.25 (Peak 4.28A,AVG 3.21A) P.29 (Peak 0.12A,AVG 0.09A)

P.28 (Peak 21A,AVG 8A) OCP 10A

4 +1.05VGFX_CORE_INT +-3%
B
ISL6263A GFX_VR_EN enable B

P.30 (Peak 8A,AVG 6A) OCP 11A

+SMDDR_VTERM
MAINON enable

5 +SMDDR_VREF
TPS51116 SUSON enable
P.27 +1.5V
+1.5VSUS +-3% 13 MAINON enable
SUSON enable
AO4468
A (Peak 16.324A,AVG 12.243A) (Peak 2.901A,AVG 2.176A) A
OCP 14.4A P.27
Quanta Computer Inc.
PROJECT : BU3
Size Document Number Rev
D3B
Power Tree Table
Date: Monday, August 10, 2009 Sheet 34 of 34
5 4 3 2 1