INTEGRATED CIRCUITS

DATA SHEET

83C145; 83C845
83C055; 87C055
Microcontrollers for TV and video
(MTV)
Product specification 1996 Mar 22
File under Integrated Circuits, IC20
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

CONTENTS 14 PROGRAMMING CONSIDERATIONS

14.1 EPROM Characteristics
1 FEATURES
14.2 Programming operation
2 DESCRIPTION 14.3 Erasure Characteristics
3 APPLICATIONS 14.4 Reading Signature Bytes
14.5 EPROM Programming and Verification
4 ORDERING INFORMATION
15 PROGRAMMING THE OSD EPROM
5 BLOCK DIAGRAM
15.1 Overview
5.1 Part options
15.2 Character description and programming
6 PINNING INFORMATION 15.3 OSD EPROM bit map
6.1 Pinning 16 REGISTER MAP
6.2 Pin description
17 LIMITING VALUES
7 DESCRIPTION OF STANDARD FUNCTIONS
18 HANDLING
8 INPUT/OUTPUT (I/O)
19 DC CHARACTERISTICS
9 DESCRIPTION OF DERIVATIVE
20 AC CHARACTERISTICS
FUNCTIONS
9.1 General description 21 PACKAGE OUTLINES

10 6-BIT PWM DACS 22 SOLDERING

22.1 Introduction
10.1 PWM DAC operation
22.2 Soldering by dip or wave
10.2 Special Function Register PWMn (n = 0 to 7)
22.3 Repairing soldered joints
11 14-BIT PWM DAC (TDAC)
23 DEFINITIONS
11.1 14-bit counter
11.2 14-bit DAC operation 24 LIFE SUPPORT APPLICATIONS
11.3 Special Function Register TDACL
11.4 Special Function Register TDACH
12 SOFTWARE ANALOG-TO-DIGITAL FACILITY
12.1 Special Function Register SAD
12.2 Software ADC operation
13 ON SCREEN DISPLAY (OSD)
13.1 OSD features
13.2 General description of the OSD module
13.3 OSD logic
13.4 Character Generator ROM
13.5 Display RAM organization
13.6 OSD Special Function Registers
13.7 OSD Control Register OSCON
13.8 OSD Control Register OSMOD
13.9 OSD Control Register OSORG

1996 Mar 22 2
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

1 FEATURES • One 14-bit PWM for high-precision voltage integration

• Masked ROM sizes: • Digital-to-analog converter and comparator with 3 inputs
multiplexer
– 8 kbytes (83C845)
• Nine dedicated I/Os plus 28 port bits (15 port bits with
– 12 kbytes (83C145)
alternative uses)
– 16 kbytes (83C055)
• 4 high current open-drain port outputs
– 16 kbytes OTP (87C055)
• 12 high voltage (+12 V) open-drain outputs
• RAM: 256 bytes
• Programmable video input and output polarities
• On Screen Display (OSD) controller
• 80C51 instruction set
• Three digital video outputs
• No external memory capability
• Multiplexer/mixer and background intensity controls
• Plastic shrink dual in-line package (0.07 inch centre
• Flexible formatting with OSD New Line option pins)
• 128 × 10 bits display RAM • High-speed CMOS technology
• Designed for reduced Radio Frequency Interference • Power supply: 5 V ±10%.
(RFI)
• Character generator ROM: 2 DESCRIPTION
– character format 18 lines × 14 dots
The 83C055, Microcontroller for Television and Video
– 60 visible characters (MTV) applications, is a derivative of Philips’ industry
– 4 special characters standard 80C51 microcontroller.
• Eight text shadowing modes The 83C055 is intended for use as the central control
• Text colour selectable per character mechanism in a television receiver or tuner.
• Background colour selectable per word
• Background colour versus video selectable per 3 APPLICATIONS
character Providing tuner functions and an OSD facility, it represents
• Eight 6-bit Pulse Width Modulators (PWM) for analog a next generation replacement for the currently available
voltage integration parts.

4 ORDERING INFORMATION

PACKAGE TEMP.
FREQ.
TYPE NUMBER RANGE
NAME DESCRIPTION VERSION (MHz)
(°C)
P83C055BBP
P87C055BBP
SDIP42 plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1 0 to +70 3.5 to 12
P83C145BBP
P83C845BBP

1996 Mar 22 3
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

5 BLOCK DIAGRAM

handbook, full pagewidth BF VID1 VCTRL VCLK1 HSYNC

T0 INT1 INT0 VID2 VID0 VCLK2 VSYNC

VDD
OSD BLOCK
XTAL1
(IN) 8-BIT CHARACTER
ROM RAM DISPLAY
TIMER / GENERATOR
CPU (1) 256 bytes RAM
EVENT ROM
128 × 10
XTAL2 COUNTER 60 × 18 × 14
(OUT)

8-bit internal bus

80C51
RST
core
excluding PARALLEL SOFTWARE
14-BIT
ROM / RAM I/O 8 x 6-BIT PWM CONTROL
PWM
PORTS ADC

V SS

8 8 4 8 8 3 MBE766

P3 P2 P1 P0 PWM0 to PWM7 TDAC ADI2 to ADI0

(1) ROM sizes: see Table 1.

Fig.1 Block diagram.

5.1 Part options

Table 1 Differences between the types
TYPES
MEMORY
83C845 83C145 83C055 87C055
ROM 8 kbytes 12 kbytes 16 kbytes −
EPROM (OTP) − − − 16 kbytes

1996 Mar 22 4
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

6 PINNING INFORMATION
6.1 Pinning

handbook, halfpage
VPP/TDAC/P0.0 1 42 VDD
handbook, halfpage
PROG/PWM1/P0.1 2 41 P3.7

ASEL/PWM2/P0.2 3 40 P3.6

PWM3/P0.3 4 39 P3.5

PWM4/P0.4 5 38 P3.4

PWM5/P0.5 6 37 P3.3/INT0

PWM6/P0.6 7 36 P3.2/T0

PWM7/P0.7 8 35 P3.1/INT1

ADI0/P1.0 9 34 P3.0

ADI1/P1.1 10 83C145 33 RST

83C845
ADI2/P1.2 11 83C055 32 XTAL2
87C055
PWM0/P1.3 12 31 XTAL1

P2.7 13 30 BF

P2.6 14 29 VCLK2

P2.5 15 28 VCLK1

P2.4 16 27 VSYNC

P2.3 17 26 HSYNC

P2.2 18 25 VCTRL

P2.1 19 24 VID2

P2.0 20 23 VID1

VSS 21 22 VID0

MBE765

Fig.2 Pin configuration (SOT270-1).

1996 Mar 22 5
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

6.2 Pin description

Table 2 Pin description SDIP42 (SOT270-1)
SYMBOL PIN DESCRIPTION
Port 0 (notes 1, 2 and 4)
P0.0/TDAC/VPP 1 P0.0: open-drain bidirectional port line;
TDAC: output for the 14-bit high-precision PWM;
VPP: 12 V programming supply voltage during EPROM programming.
P0.1/PWM1/PROG 2 P0.1: open-drain bidirectional port line;
PWM1: output for the 6-bit lower-precision PWM;
PROG: input for EPROM programming pulses.
P0.2/PWM2/ASEL 3 P0.2: open-drain bidirectional port line;
PWM2: output for the 6-bit lower-precision PWM;
ASEL: input indicating the EPROM address bits that are applied to Port 2.
P0.3/PWM3 4 to 8 P0.3 to P0.7: 5 open-drain bidirectional port lines;
to PWM3 to PWM7: 5 outputs for the 6-bit lower-precision PWM.
P0.7/PWM7
Port 1 (notes 1, 2 and 5)
P1.0/ADI0 9 to 11 P1.0 to P1.2: 3 open-drain bidirectional port lines;
to ADI0 to ADI2: inputs for the software analog-to-digital facility.
P1.2/ADI2
P1.3/PWM0 12 P1.3: open-drain bidirectional port line; PWM0: output for the 6-bit lower-precision
PWM. PWM0 can be externally pulled up as high as +12 V ±5%
Port 2
P2.7 to P2.0 13 to 20 Port 2: 8-bit open-drain bidirectional port; P2.3 to P2.0 have high current capability
(10 mA at 0.5 V) for driving LEDs. Port 2 pins that have logic 1s written to them float,
and in that state can be used as high-impedance inputs. Any of the Port 2 pins are
driven LOW if the port register bit is written as a logic 0. The state of the pin can
always be read from the port register by the program.
Port 3 (note 1 and 3)
P3.0 34 P3.0: open-drain bidirectional port line.
P3.1/INT1 35 P3.1: open-drain bidirectional port line; INT1: External interrupt 1.
P3.2/T0 36 P3.2: open-drain bidirectional port line; T0: Timer 0 external input.
P3.3/INT0 37 P3.3: open-drain bidirectional port line; INT0: External interrupt 0.
P3.4 to P3.7 38 to 41 P3.4 to P3.7: 4 open-drain bidirectional port lines.
General
VSS 21 Ground: 0 V reference.
VID2 to VID0 22 to 24 Digital Video bus: Three totem-pole outputs comprising digital RGB (or other colour
encoding) from the OSD facility. The polarity of these outputs is controlled by a
programmable register bit (register OSCON; bit Po).
VCTRL 25 Video Control: A totem-pole output indicating whether the OSD facility is currently
presenting active video on the VID2 to VID0 outputs. Signal is used to control an
external multiplexer (mixer) between normal video and the video derived from VID2 to
VID0. The polarity of this output is controlled by a programmable register bit (register
OSCON; bit Pc).

1996 Mar 22 6
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

SYMBOL PIN DESCRIPTION

HSYNC 26 Horizontal Sync: A dedicated input for a TTL-level version of the horizontal sync
pulse. The polarity of this pulse is programmable; its trailing edge is used by the OSD
facility as the reference for horizontal positioning.
VSYNC 27 Vertical Sync: A dedicated input for a TTL-level version of the vertical sync pulse. The
polarity of this pulse is programmable, and either edge can serve as the reference for
vertical timing.
VCLK1 28 VCLK1: Video Clock 1; input for the horizontal timing reference for the OSD facility.
VCLK2 29 VCLK2: Video Clock 2; output from the on-chip video oscillator. VCLK1 and VCLK2
are intended to be used with an external LC circuit to provide an on-chip oscillator. The
period of the video clock is determined such that the width of a pixel in the OSD is
equal to the inter-line separation of the raster.
BF 30 Background/Foreground: A totem-pole output which, when VCTRL is active,
indicates whether the current video data represents a Foreground (LOW) or
Background (HIGH) dot in a character. This signal can be used to reduce the intensity
of the background colour and thus emphasize the text.
XTAL1 31 XTAL1: Input to the inverting (oscillator) amplifier and clock generator circuit that
XTAL2 32 provides the timing reference for all 83C055 logic other than the OSD facility.
XTAL2: Oscillator output terminal for system clock. XTAL1 and XTAL2 can be used
with a quartz crystal or ceramic resonator to provide an on-chip oscillator. Alternatively,
XTAL1 can be connected to an external clock, and XTAL2 left unconnected.
RST 33 Reset: If this pin is HIGH for two machine cycles (24 oscillator periods) while the
oscillator is running, the MTV is reset. This pin is also used as a serial input to enter a
test or EPROM programming mode, as on the 87C751.
VDD 42 Power supply: for normal and Power-down operation.
Notes
1. Port 0, Port 1 , and Port 3 pins that have logic 1s written to them float, and in that state can be used as
high-impedance inputs.
2. The state of the pin can always be read from the port register by the program.
3. P3.0, P3.4, and P3.7 can be externally pulled up as high as +12 V ±5%; while P3.5 and P3.6 have 10 mA drive
capability.
4. For each PWM block, a register bit (register PWMn; bit PWnE; n = 0 to 7) controls whether the corresponding pin is
controlled by the block or by Port 0; Port 0 controls the pin immediately after a reset. Regardless of how each pin is
controlled, it can be externally pulled up as high as +12 V ±5%.
5. Any of the Port 1 pins are driven LOW if the corresponding port register bit is written as a logic 0, or for P1.3 only, if
the TDAC module presents a logic 0.

1996 Mar 22 7
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

7 DESCRIPTION OF STANDARD FUNCTIONS • The IP register is not used, and the IE register (address
A8H) is similar to that on the 80C51;see Table 36.
For a description of the standard functions please refer to
the “Data Handbook IC20; Section 2: 80C51 Technical • The VSYNC input used by the OSD facility can generate
Description” . an interrupt. The active polarity of the pulse is
programmable (see Section 13.7); interrupt occurs at
the leading edge of the pulse.
8 INPUT/OUTPUT (I/O)
• Since there is no serial port, there are no interrupts nor
The I/O structure of the 83C055 is similar to the standard control bits relating to this interrupt. The interrupts and
I/O structure in the 80C51, except for the points described their vector addresses are shown in Table 3.
in Table 5. • External Interrupt 1 is modified so that an interrupt is
generated when the input switches are in either direction
9 DESCRIPTION OF DERIVATIVE FUNCTIONS (on the 80C51, there is a programmable choice between
interrupt on a negative edge or a LOW level on INT1).
9.1 General description This facility allows for software pulse-width
Although the 83C055 is specifically referred to throughout measurement handling of a remote control.
this data sheet, the information applies to all the devices.
The differences to 80C51 features and the derivative Table 3 Program Memory address
functions are described in the following Sections and EVENT PROGRAM MEMORY ADDRESS
Chapters.
Reset 000H
Figure 1 shows the block diagram of the 83C055.
External INT0 003H
9.1.1 NOT IMPLEMENTED FUNCTIONS Timer 0 00BH
External INT1 013H
Standard functions to the 80C51 that are not implemented
in the 83C055: Timer 1 01BH

• As Data and Program Memory are not externally VSync Start 023H
expandable on the 83C055, the ALE, EA, and
PSEN signals are not implemented. 9.1.3 PCON REGISTER DIFFERENCE
• Idle mode. The PCON register format is shown in Table 4. Bits GF1
• Power-down mode. and GF0 are general purpose flag bits.

9.1.2 INTERRUPT FACILITIES DIFFERENCES Table 4 PCON Register format (address 87H)

The interrupt facilities of the 83C055 differ from those of 7 6 5 4 3 2 1 0

the 80C51 as follows: − − − − GF1 GF0 − −

9.1.4 I/O PORTS DIFFERENCES

Table 5 I/O ports differences
I/O STANDARD 80C51 83C055
Port 0 external memory expansion 8-bit open-drain bidirectional port; and includes:
alternative use for PWM outputs
Port 1 8-bit general purpose quasi-bidirectional 4-bit open-drain port, and includes alternative uses
for analog inputs and a PWM output
Port 2 quasi-bidirectional and can be used for external open-drain and general purpose
memory expansion
Port 3 quasi-bidirectional; all eight bits have alternate uses 3 port bits have some of the same alternative uses
as on the 80C51 but not necessarily on the same
pins; 5 pins are open-drain and general purpose

1996 Mar 22 8
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

10 6-BIT PWM DACS When the value matches, the output flip-flop is cleared, so
that the output pin is driven LOW.
Figure 3 shows the 6-bit PWM DAC logic circuit, consisting
of 8 PWMn modules. When the value rolls over to zero, the output flip-flop is set,
so that the output pin is released. Thus the output
The basic MCU clock is divided by 4 to get a waveform that
waveform has a fixed period of 64 PWM clock cycles; its
clocks a 14-bit counter which is common to all the PWMs
duty cycle is determined by contents of PWMn.5 to
(including the 14-bit PWM). This divided clock is hereafter
PWMn.0 (PVn5 to PVn0).
called the PWM clock.
Three of the nine total PWM modules (8 PWMn and the
As illustrated in Fig.3, the lower-precision (6-bit) PWMs
14-bit PWM DAC) operate as previously described; for
use the least significant part of the 14-bit counter.
three others, both the rising and falling edges of the output
Figure 4 shows the circuit diagram of a 6-bit PWM module. are delayed by one PWM clock; for the remaining three,
Each PWM module has a Special Function Register both edges are delayed by two PWM clocks. This feature
PWMn; n = 0 to 7. The register format is shown in Table 6. reduces the radio-frequency emission that would
otherwise occur when the counter rolled over to zero and
10.1 PWM DAC operation all nine open-drain outputs were released.
Value field PVn5 to PVn0 of each PWMn register
(n = 0 to 7) is compared to the 6 LSBs of the common
counter (14-bit counter).

10.2 Special Function Register PWMn (n = 0 to 7)

Table 6 Special Function Register PWMn (n = 0 to 7; addresses D4H to DFH)
7 6 5 4 3 2 1 0
PWnE − PVn5 PVn4 PVn3 PVn2 PVn1 PVn0

Table 7 Description of PWMn bits

BIT SYMBOL DESCRIPTION

7 PWnE PWM module enable bit. If for a particular PWM block (n) the bit:
PWnE = 1, then the block is active and controls its assigned port pin.
PWnE = 0, the corresponding port pin is controlled by the port.
6 − Reserved.
5 to 0 PVn5 to PVn0 Value field for PWMn register.

1996 Mar 22 9
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

handbook, full pagewidth

ZERO
P1.3 8
6
1st PWM MODULE (n = 0) PWM0/P1.3
8

6 P0.1

2nd PWM MODULE (n = 1) PWM1/P0.1

8

6 P0.2 to P0.6
PWM2/P0.2
3rd to 7th PWM MODULE (n = 2 to 6) to
PWM6/P0.6
8

6 P0.7

8th PWM MODULE (n = 7) PWM7/P0.7

8

LS 6-bits PWM clock internal bus

14-BIT PWM
14-BIT COUNTER 4 fxtal
DAC BLOCK
MBE771 - 1

Fig.3 6-bit PWM DAC logic circuit.

handbook, full pagewidth I/O port

PWM module (n)

PWMn
ZERO I/O pin

LS 6-bits
6-bit (1) (2)
COMPARATOR

6-bits (PVn0 to PVn5)

8 PVn0 PVn1 PVn2 PVn3 PVn4 PVn5 PWnE

internal bus

PWM clock
MBE770

(1) This flip-flop occurs in 5 of the 8 PWMn modules.

(2) This flip-flop occurs in 3 of the 8 PWMn modules.

Fig.4 A 6-bit PWM module.

1996 Mar 22 10
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

11 14-BIT PWM DAC (TDAC) 11.2.2 HIGH PRECISION OPERATION

11.1 14-bit counter For the higher-precision aspect of this feature, the 7 MSBs
of the counter are used in a logic block with the 7 LSBs of
The 14-bit counter was already mentioned in Section 10.
the programmed value.
The nature of the counter is such that it can achieve a
stable output value through its MSB, and the value can The 7th LSB (binary value 64) of the programmed value is
propagate through logic like that shown in Fig.5. The logic ANDed with the 7th MSB (128) of the counter, the 6th LSB
output can be stable within: of the value is ANDed with the counter’s 6th and 7th MSBs
• one period of the PWM clock (e.g. 250 ns) if being 10, and so on through the LSB of the programmed
edge-triggered logic is used to capture the logic output, value being ANDed with the counter’s 7 MSBs being
or 100000. Then these 7 ANDed terms are ORed. If the
result is true (logic 1) at the time the 7 LSBs of the counter
• one phase of the PWM clock (e.g. 125 ns) if a phase of match the MSBs of the programmed value, the output is
the PWM clock is used to capture the logic output. forced high for 1 (additional) PWM clock cycle.
The 14-bit (TDAC) counter is a ripple counter (cost and The result is that, if the value-64 bit of the 14-bit value is
die-size reasons). programmed to a logic 1, every other cycle of 128 PWM
The 14-bit PWM DAC is controlled by two special function counter clocks has its duty cycle stretched by one counter
registers TDACL and TDACH. clock; if the value-32 bit is programmed to logic 1, every
4th cycle is stretched, and so on through, if the value-1 bit
11.2 14-bit DAC operation is programmed to logic 1, one cycle out of each 128 is
stretched.
When software wishes to change the 14-bit value
(TD0 to TD13), it should first write to TDACL and then 11.2.3 14-BIT DAC OUTPUT
write to TDACH. Alternatively, if the required precision of
the duty cycle is satisfied by 6 bits or less, software can Assuming the external integrator can handle all this, the
simply write to TDACH (TD8 to TD13). net effect is a PWM DAC that has the period of a 7-bit
design (which makes the integrator easier and more
11.2.1 LOW PRECISION OPERATION feasible to design) with the accuracy of a 14-bit one.

Figure 5 shows that this block includes an ‘extra’ 14-bit An obvious prerequisite for such precision is that the load
latch between TDACL - TDACH and the comparator and on the voltage must be very light, like a single op-amp or
other logic. The programmed value is clocked into the comparator.
operative latch when the 7 low-order bits of the counter roll
over to zero, provided that the software is not in the midst 11.2.3.1 Note
of loading a new 14-bit value, i.e. it is not between writing The TDAC feature differs from the corresponding features
TDACL and writing TDACH. of predecessor parts in several ways:
In a similar fashion to the lower-precision PWMs, this 1. The 14-bit value is functionally composed of major and
facility has an output flip-flop that is set when the lower minor portions of 7 bits each.
7 bits of the counter overflow/wrap. The more significant
2. The 14-bit value is programmed as a contiguous
7 bits of the operative latch’s programmed value are
multi-register value that can be manipulated
compared for equality against the less significant 7 bits of
straight-forwardly via arithmetic instructions.
the counter, and the output FF is cleared when they match.
Thus this output has a fixed period of 128 PWM clock 3. As discussed for the 6-bit DACs, both of the preceding
cycles, and the duty cycle is determined by the parts had a feature whereby the PWM output could be
programmed value. inverted, redundantly with complementing the 14-bit
value. This feature has been eliminated.

1996 Mar 22 11
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

11.3 Special Function Register TDACL

Table 8 Special Function Register TDACL format (address D2H)

7 6 5 4 3 2 1 0
TD7 TD0 TD1 TD2 TD3 TD4 TD5 TD6

Table 9 Description of TDACL bits

BIT SYMBOL DESCRIPTION

7 to 0 TD7, TD0 to TD6 8 LSBs of the 14-bit value.

11.4 Special Function Register TDACH

Table 10 Special Function Register TDACH format (address D3H)
7 6 5 4 3 2 1 0
TDE − TD13 TD12 TD11 TD10 TD9 TD8

Table 11 Description of TDACH bits

BIT SYMBOL DESCRIPTION

7 TDE Enable bit.
6 − Reserved.
5 to 0 TD13 to TD8 6 MSBs of the 14-bit value.

1996 Mar 22 12
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

handbook, full pagewidth

INTERNAL BUS
7 7

TDACH TDACL

88 8
8

14-BIT LATCH

7 MSB 7 7 LSB
7

7-BIT COMPARATOR

TDACH.7

TDAC/
P0.0

P0.0
7
7

7 LSB 7 MSB
PWM clock
14-BIT COUNTER 4 fxtal
MBE774

Fig.5 14-bit PWM logic circuit.

1996 Mar 22 13
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

12 SOFTWARE ANALOG-TO-DIGITAL FACILITY

Figure 6 shows the software analog-to-digital facility block diagram. The block includes Special Function Register SAD.

12.1 Special Function Register SAD

Table 12 Special Function Register SAD format (address D8H)
7 6 5 4 3 2 1 0
VHi CH1 CH0 St SAD3 SAD2 SAD1 SAD0

Table 13 Description of SAD bits

BIT SYMBOL DESCRIPTION

7 VHi The comparator output bit; bit addressable.
6 CH1 The channel field controls which pin, if any, is connected to this facility; see Table 14.
5 CH0
4 St The St bit should be written as a logic 1 in order to initiate a voltage comparison.
3 to 0 SAD3 to SAD0 4 LSBs of the SAD register.

12.2 Software ADC operation Table 14 Pin selection: P1.n/ADIn

Port pins P1.0/ADI0 to P1.2/ADI2 can be alternately CH1 CH0 P1.n/ADIn(1)
selected as inputs of a linear voltage comparator. The
0 0 none
other input of the comparator is connected to a 4-bit DAC.
0 1 P1.0/ADI0
This DAC is controlled by bits SAD3 to SAD0 and
1 0 P1.1/ADI1
produces a reference voltage:
1 1 P1.2/ADI2
nominally 0.15625 to 4.84375 V in increments of
0.3125 V. Note
The output of the comparator (HIGH or LOW) can be read 1. Port 1 has open-drain drivers which will not materially
by the program as the MSB of the SAD register i.e. bit VHi. affect an analog voltage as long as any and all pins
used for software analog-to-digital measurement have
After writing St = 1, the program should include intervening
corresponding logic 1s in the port register; n = 0, 1, 2.
instructions totalling at least 6 machine cycles (72 clock
periods or 6 µs at 12 MHz), before the instruction that
accesses and tests VHi.

1996 Mar 22 14
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

handbook, full pagewidth I/O PORT

P1.0/ADI0 VOLTAGE
COMPARATOR

I/O PORT
ANALOG
P1.1/ADI1
MUX

I/O PORT
4-BIT
P1.2/ADI2
DAC

SAD.6:5 SAD.3:0

internal bus

MBE772

Fig.6 Software analog-to-digital facility.

1996 Mar 22 15
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

13 ON SCREEN DISPLAY (OSD) 13.1.3 DUAL-PORTED DISPLAY RAM

Figure 7 shows the OSD block diagram. It shows the CPU The OSD has a true display RAM instead of a character
writing into the 128 × 10 display RAM, which is dual-ported line buffer. This display RAM is dual-ported to allow
to allow the CPU to write into it at any time, including when updating the display RAM at any time instead of having to
it is being read out by the OSD logic. The 10-bit wide data wait for a vertical retrace.
coming out of the display RAM is used to access the
Vertical Sync (VSYNC) interrupts are supported if
appropriate character in the Character Generator memory
flicker-free updates are required.
(6-bits) and to specify character and display control
functions (4-bits).
13.1.4 PROGRAMMABLE CHARACTER SIZE
Timing for the OSD is controlled by the HSYNC, VSYNC,
• Normal characters are displayed as 18 × 14 bit maps.
and dot clock input VCLK1.
• In an interlaced display:
13.1 OSD features – 2 fields are displayed so that one actually sees a
36 × 14 pixel size character.
The 83C055 features an advanced OSD function with
some unique features as described in Sections 13.1.1 to – The part has a double height and width mode which
13.1.10. displays 36 × 28 pixel size bit maps per field.
• For use in non-interlaced systems, the part has a double
13.1.1 USER-DEFINABLE DISPLAY FORMAT height mode so that the displayed characters have the
The OSD does not restrict the user to a fixed number of same pixel size (36 × 14) as on an interlaced display.
lines with a fixed number of characters per line:
13.1.5 CHARACTER SHADOWING
• Using a fixed number of lines restricts the generation of
displays that can be differentiated from others that use When characters are displayed overlaid on a background
the same chip and places limits on screen content. of base video, a black border around the characters makes
• Using a fixed number of characters per line wastes them highly legible. This feature is called shadowing. The
83C055 has 8 shadowing modes to allow the user to select
display RAM if a line has less than the full number of
various partial shadow modes as well as full surround
displayable characters (it has to be padded with
non-visible characters). shadow; see Fig.8 and Table 28.

The OSD on the 83C055 defines a control character: 13.1.6 PROGRAMMABLE POLARITIES
• New Line, that has the same function as a Carriage Inputs to and outputs from the OSD can be programmed
Return and Line Feed. to be recognized as active LOW or HIGH. In conjunction
When the OSD circuitry fetches this character from display with the 12 V outputs, this allows direct interfacing to most
RAM it stops displaying further characters, waits for the video signal processing circuits.
next horizontal scan line, and starts displaying the next
character in display RAM after the New Line character was 13.1.7 CHARACTER GENERATOR MEMORY IN EPROM
received.
On the 87C055, the Character Generator memory is in
The number of lines is thus up to the user, within the limits EPROM. This feature allows quick and inexpensive font
of the display and memory, as are the number of development and refinement against the alternative of
characters per line. This allows far better control of the creating a masked ROM version to see how the final fonts
appearance of the OSD. will appear.

13.1.2 COLOURS SELECTABLE BY CHARACTER 13.1.8 HSYNC LOCKED DOT CLOCK OSCILLATOR
Characters can be displayed on a background of the base The 83C055 is designed to use an LC oscillator circuit that
video or a programmable background colour. is started at the trailing edge of HSYNC and stopped at its
The background colour is selectable by word and the leading edge. In practice, this gives a highly consistent
choice of background (base video/user programmed delay from HSYNC to oscillator start and is stable from
colour) by character. scan line to scan line so that no left margin effects are
seen.

1996 Mar 22 16
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

13.1.9 SHORT ROWS Figure 7 shows the 3 major elements of the OSD facility:
This mode only displays 4 horizontal lines and is used for • OSD logic
generating underlines. • Display RAM
• Character Generator ROM.
13.1.10 PROGRAMMABLE HORIZONTAL AND VERTICAL
POSITIONS
13.3 OSD logic
Bit pairs HS4 to HS0 and VS2 to VS0 in register OSORG For a standard NTSC TV signal with an HSYNC frequency
(Table 30) define the starting point of the display. of 15.750 kHz and a VSYNC frequency of nominally
60 Hz, there are roughly 50 µs of active horizontal scan
13.2 General description of the OSD module line available.
This block is the largest of the additions that are specific to A typical pixel clock frequency is 8 MHz, and therefore
this product. Its basic function is to superimpose text on roughly 400 pixels of resolution can be obtained. At
the television video image, to indicate various parameters 14 dots per character, this means 28 character per
and settings of the receiver or tuner. External circuitry horizontal scan line. If the 12 dot per character display
handles the mixing (multiplexing) of the text and the TV mode is used, that means 33 character per horizontal scan
video. The OSD block has 4 input pins: line. Allowing for edge effects, 26 characters (14 across) or
• Two for a video clock: VCLK1 and VCLK2 31 characters (12 across) can be displayed.
• Horizontal sync signal: HSYNC Note that VGA rates and higher can be used. The
• Vertical sync signal: VSYNC. minimum character dot size will be a function of the VGA
frequency used. For a 640 × 480 display, running at
The block has 4 outputs:
33 kHz, the equivalent 83C055 pixel resolution is about
• 3 colour video signals 160 across (because of the 8 MHz clock and allowing for
• a control signal. overscan). This means that status and diagnostic
information can be displayed on video monitors.
Since this block is the major feature of the part, its main
inputs and outputs are dedicated pins, without alternate 13.3.1 ON-CHIP VIDEO OSCILLATOR
port bits. The OSD of the 83C055 differs from that in
preceding devices in one major way: The video clock pins (VCLK1 and VCLK2) are used to
• It does not fix the number and size of displayed rows of connect a LC circuit to an on-chip video oscillator that is
text. independent of the normal MCU clock.

Several predecessor parts allowed two displayed rows of The L and C values are chosen so that a video pulse, of a
16 characters each. The 83C055 simply has 128 locations duration equal to the VCLK period, will produce a
of Display RAM, each of which can contain: more-or-less square dot on the screen, that is, a dot having
a width approximately equal to the vertical distance
• a displayed character, or between consecutive scan lines.
• a New Line character that indicates the end of a row.
The video oscillator is stopped (with VCLK2 = LOW) while:
A variant of the New Line character is used to indicate
the end of displayed data. • HSYNC (Horizontal Sync) is maintained, and

A number of changes in the OSD architecture have • is released to operate at the trailing edge of HSYNC.
reduced the number of other Special Function Registers This technique helps provide uniform horizontal
involved in the feature, below the number needed with positioning of characters/dots from one scan line to the
predecessor devices: next.
1. The elimination of certain options such as 4, 6, or
8 × character sizes and alternate use of two of the
video outputs.
2. The moving of certain other options from central
registers to Display RAM, such as foreground colour
codes (Fcolor) and background (B) selection.

1996 Mar 22 17
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

13.4 Character Generator ROM 13.5 Display RAM organization

Character Generator ROM. Containing 60 displayable bit Each Display RAM location includes:
maps, i.e. 64 minus 4, comprising: • 6 data bits, and
• One for each of new line: New Line, and • 4 attribute bits.
• Three space characters:
The 6 data bits from Display RAM, along with a
– Space line-within-row count, act as addresses into the Character
– BSpace Generator ROM. Except in special test modes that are
beyond the scope of this data sheet, Display RAM cannot
– SplitBSpace.
be read by the MCU program.
Each bit map includes 18 scan lines by 14 dots.
The Character Generator ROM is maskable or
programmable along with the Program ROM to allow for
various character sets and languages.

dbook, full pagewidth

HSYNC VCLK2
OSD LOGIC
VSYNC VCLK1

7 4 VCTRL
internal OSD RAM ATTRIBUTE
bus 128 × 10 CONTROL

VID2
RGB
6 DIGITAL
VIDEO OUT
VID1

CHARACTER 6 CHARACTER
GENERATOR GENERATOR
ADDRESS LOGIC 60 × 18 × 14 VID0

MBG323

Fig.7 OSD block diagram.

1996 Mar 22 18
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

13.6 OSD Special Function Registers need not be rewritten for each character, only prior to
writing OSDT for the first character with those particular
The programming interface to Display RAM is provided by
attributes.
three Special Function Registers as shown in Tables 15,
17 and 20. The OSAT attribute bits associated with the BSpace,
SplitBSpace and New Line characters (see Table 19) are
Writing OSAT simply latches the attribute bits into a
interpreted differently from those that accompany other
register, while writing OSDT causes the data bus
data characters. With BSpace and SplitBSpace, B is
information, plus the contents of the OSAT register, to be
interpreted as described above, but the 3 colour bits
written into display RAM.
specify the background colour (Bcolor) for subsequent
Thus, for a given Display RAM location, OSAT should be characters. For BSpace, a change in B and Bcolor
written before OSDT. If successive characters are to be becomes effective at the left edge of the character’s bit
written into Display RAM with the same attributes, OSAT map.

13.6.1 SPECIAL FUNCTION REGISTER OSAD

Table 15 Special Function Register OSAD (On Screen ADdress; address 9AH)

7 6 5 4 3 2 1 0
− OSAD6 OSAD5 OSAD4 OSAD3 OSAD2 OSAD1 OSAD0

Table 16 Description of OSAD bits

BIT SYMBOL DESCRIPTION

7 − Reserved.
6 to 0 OSAD6 to OSAD0 These 7-bits hold the Display RAM address into which data will be
loaded. OSAD is automatically incremented by one each time OSDT and
Display RAM are written to.

13.6.2 SPECIAL FUNCTION REGISTER OSDT

Writing OSDT causes the data bus information, plus the contents of the OSAT register, to be written into display RAM.

Table 17 Special Function Register OSDT (On Screen DaTa; address 99H)

7 6 5 4 3 2 1 0
− − OSDT5 OSDT4 OSDT3 OSDT2 OSDT1 OSDT0

Table 18 Description of OSDT bits

BIT SYMBOL DESCRIPTION

7 to 6 − Reserved.
5 to 0 OSDT5 to OSDT0 Character data; see Table 19. In reality, there is a potential conflict
between the timing of a write to OSDT and an access to display RAM by
the OSD logic for data display. This is resolved by the use of a true
dual-ported RAM for display memory.

1996 Mar 22 19
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

Table 19 Special characters related to OSDT register

SPECIAL CHARACTER OSDT5 OSDT4 OSDT3 OSDT2 OSDT1 OSDT0

New Line 1 1 1 1 0 1
Space (normal) 1 1 1 1 0 0
BSpace 1 1 1 1 1 0
SplitBspace 1 1 1 1 1 1

13.6.3 SPECIAL FUNCTION REGISTER OSAT

Table 20 Special Function Register OSAT ( On Screen ATtributes; address 98H)

WITH OSDT = 7 6 5 4 3 2 1 0
New Line − − − E − SR D Sh
BSpace − − − B − BC2 BC1 BC0
SplitBSpace − − − B − BC2 BC1 BC0
Any other character − − − B − FC2 FC1 FC0

Table 21 Description of OSAT bits

BIT SYMBOL DESCRIPTION

7 to 5, 3 − Reserved.
With OSDT = New Line; note 1
4 E End; If the E bit is 1, no further rows are displayed on the screen.
2 SR Short row; If E = 0 and SR = 1, the next row is a ‘short row’, i.e. it is only 4 or 8 scan lines high
rather than 18 or 36. Short rows can be used for underlined text.
1 D Double height; If E = 0 and D = 1, all of the characters in the following row are displayed with
‘double height and width’.
0 Sh Shadowing; If E = 0 and Sh = 1, all of the characters in the following row are displayed with
‘shadowing’; see Section 13.8.
With OSDT = BSpace or SplitBspace; note 2
4 B Background; B indicates whether ‘background pixels’ should show the current background
colour (B = 1), or television video (B = 0).
2 to 0 BC2 to BC0 Bcolor: Background colour (notes 3 and 4; see Table 22).
With OSDT = Any other character
4 B Background; B indicates whether ‘background pixels’ should show the current background
colour (B = 1), or television video (B = 0).
2 to 0 FC2 to FC0 Fcolor: Foreground colour. Fcolor indicates the colour of ‘foreground pixels’ in the ROM bit
map for this character (see Table 22).

1996 Mar 22 20
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

Notes to the description of OSAT bits

1. The latches in which the E,SR, D, and Sh bits are captured are cleared to zero at the start of each vertical scan. This
means that if the first text line on the screen is a short row, or if it contains either double size or shadowing, the text
must be preceded by a New Line character. Like all such characters, this initial New Line advances the vertical
screen position; the VStart value (see register OSORG; Section 13.9) should take this fact into account.
2. For SplitBSpace, a change in B and Bcolor occurs halfway through the character horizontally.
3. The normal Space character has no effect on the Bcolor value.
4. The Bcolor value is not cleared between vertical scans, so that if a single background colour is all that is needed in
an application, it can be set via a single BSpace character during program initialization, and never changed
thereafter. In order for such a BSpace to actually affect the 83C055 internal Bcolor register the Mode field of the
OSMOD register must be set to ‘01B’ (or higher) so that the OSD hardware is operating (see register OSMOD;
Section 13.8).

Table 22 OSD outputs related to character bit map value, Fcolor, Bcolor and B bits
OSD OUTPUTS (notes 1 and 2)
CHARACTER BIT MAP VALUE
VID2 VID1 VID0 VCTRL
logic 1 FC2 FC1 FC0 driven active
logic 0 BC2 BC1 BC0 B

Notes
1. Bcolor (BC2,BC1,BC0) values ‘000’ and ‘111’ minimize the occurrence of transient states among the VID2 to VID0
outputs.
2. The background colour defined by the most recently encountered BSpace or SplitBSpace character is maintained
on the VID2 to VID0 pins except at the following times:
a) During the active time of HSYNC.
b) During the active time of VSYNC.
c) During those pixels of an active character that correspond to a logic 1 in the character’s bit map.
d) During a ‘shadow’ bit.

1996 Mar 22 21
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

13.7 OSD Control Register OSCON

Table 23 OSD Control Register OSCON (address C0H)
7 6 5 4 3 2 1 0
IV Pv Lv Ph Pc Po DH BFe

Table 24 Description of OSCON bits (see note 1)

BIT SYMBOL DESCRIPTION
7 IV Interrupt flag for the OSD feature. Bit IV is set by the leading edge of the VSYNC pulse,
and is cleared by the hardware when the VSYNC interrupt routine is vectored to. It can
also be set or cleared by software writing a logic 1 or logic 0 to this bit.
6 Pv Pv defines the active VSYNC input polarity. If Pv = 0, then VSYNC input is active HIGH;
if Pv = 1, then VSYNC input is active LOW.
One effect of bit Pv is that the VID2 to VID0 and VCTRL outputs are blocked (held at
black/inactive) during the active time of VSYNC. The IV bit is set on the leading edge of
the VSYNC pulse; thus Pv controls whether the OSD interrupt occurs in response to a
HIGH-to-LOW or LOW-to-HIGH transition on VSYNC.
5 Lv Lv defines the active edge of VSYNC. The active edge (leading or trailing) of VSYNC
(as defined by Pv), clears the state counter which determines the vertical start of on
screen data. Time reference for the video field is the leading edge of VSYNC, if Lv = 0,
or the trailing edge of VSYNC, if Lv = 1.
4 Ph Ph defines the active HSYNC input polarity. If Ph = 0, then HSYNC input is active HIGH;
if Ph = 1, then HSYNC input is active LOW.
3 Pc Pc defines the active VCTRL output polarity; VCTRL output active means: show the
colour on VID2 to VID0. If Pc = 0, then VCTRL output is active HIGH; If Pc = 1, then
VCTRL output is active LOW.
2 Po Po defines the VID2 to VID0 outputs polarity; bit is needed only because the Shadowing
feature needs to generate black pixels without reference to a register value. Internally,
the 3-bit code ‘000B’ always designates black.
If Po = 0, a logic 0 internal to the 83C055 corresponds to a LOW on one of the
VID2 to VID0 pins.
If Po = 1, a logic 1 internal to the 83C055 corresponds to a LOW on one of the
VID2 to VID0 pins.
1 DH If DH = 1, character sizes are doubled vertically but not horizontally. This feature allows
the 83C055 to be used in ‘improved definition’ systems that are not interlaced.
The vertical doubling imposed by DH does not affect the VStart logic as described in
Table 30; it operates in HSync units regardless of DH or D.
0 BFe Background/Foreground enable; output BF. If BFe = 1, then the BF output tracks
whether each bit in displayed characters is a Foreground bit (LOW), or a Background bit
(HIGH). If BFe = 0, then the BF pin remains HIGH.

Note
1. It is theoretically possible that a VSYNC interrupt could be missed, or an extra one generated, if OSCON is read,
then modified internally (e.g. in ACC), and the result written back to OSCON. However, none of the other bits in
OSCON are reasonable candidates for dynamic change. Special provisions are included in the 83C055 logic so that
IV will not be changed by a single ‘read-modify-write’ instruction such as SETB or CLR, unless the instruction
specifically changes IV.

1996 Mar 22 22
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

13.8 OSD Control Register OSMOD

Under some conditions writing to OSMOD while the display is active can cause a temporary flicker during that display
field. This can be avoided by only writing to OSMOD during the vertical sync interval.

Table 25 OSD Control Register OSMOD (address C1H)

7 6 5 4 3 2 1 0
Wc − Mode1 Mode0 − SHM2 SHM1 SHM0

Table 26 Description of OSMOD bits (see note )

BIT SYMBOL DESCRIPTION
7 Wc If Wc = 1, then each displayed character is horizontally terminated after
12 bits have been output, as opposed to after 14 bits if Wc = 0. This
allows text to be ‘packed’ more tightly so that more characters can be
displayed per line. In effect, the 2 bits out of the display ROM, which
would otherwise be the rightmost 2 of the 14, are ignored when Wc is 1.
Clearly, if this feature is to be used, it must be accounted for in the design
of the bit maps in the display ROM.
6 − Reserved.
5 Mode1 Display mode select bits; see Table 27.
4 Mode0
3 − Reserved.
2 to 0 SHM2 to SHM0 Shadowing mode (ShMode); determines how characters are shadowed
in rows for which the row attribute Sh = 1 (register OSAT; see Table 21);
for the shadowing modes see Fig.8 and Table 28.

Table 27 Selection of Display Modes

Mode1 Mode0 DISPLAY MODE

0 0 Mode 0 The OSD feature is disabled. VCLK oscillator is disabled, VID2 to VID0 are set to black, and
VCTRL is held inactive.This is the mode to which the 83C055 OSD logic is reset; note 1.
0 1 Mode 1 The VCLK oscillator is enabled and the OSD logic operates normally internally, but
VID2 to VID0 are set to black and VCTRL is held inactive; note 2.
1 0 Mode 2 Normal OSD operation. Active characters can be shown against TV video (for characters
with B = 0) or (for characters with B = 1) against a background of the colour defined as an
attribute of BSpace and SplitBSpace characters.
1 1 Mode 3 Characters can be displayed but all of the receiver’s normal video is inhibited by holding
VCTRL asserted throughout the active portion of each scan line; see note 3.

Notes
1. A direct transition from this mode to ‘active display’ (Mode1, Mode0 = 1X) would result in undefined operation and
visual effects for the duration of the current video field (until the next VSYNC).
2. The OSD feature can be toggled between this state and ‘active display’ as desired to achieve real-time special effects
such as ‘vertical wiping’.
3. Since VID2 to VID0 are driven with the current background colour during this time, except during the foreground
portion of displayed characters, this produces text against a solid background. This mode is useful for extensive
displays that require user concentration.

1996 Mar 22 23
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

Table 28 Shadowing modes determined by bits SHM2 to SHM0 (register OSMOD) and Sh (register OSAT)

SHM2 SHM1 SHM0 Sh SHADOWING MODE(1)

0 0 0 1 South-west
0 0 1 1 West
0 1 0 1 North-west
0 1 1 1 North
1 0 0 1 North-east
1 0 1 1 East
1 1 0 1 South-east
1 1 1 1 Full surround
X X X 0 No Shadowing

Note
1. The mode names are based on the position of an apparent light source, ranging from the lower left (South-west)
clockwise to the lower right (South-east); see Fig.8.

13.9 OSD Control Register OSORG

Table 29 OSD Control Register OSORG (address C2H)

7 6 5 4 3 2 1 0
HS4 HS3 HS2 HS1 HS0 VS2 VS1 VS0

Table 30 Description of OSORG bits (note 1)

BIT SYMBOL DESCRIPTION

7 to 3 HS4 to HS0 HStart field; defines the horizontal start position of all the on-screen character rows, as
approximately a multiple of 4 VCLK clock cycles. Active display begins after the trailing
edge of HSYNC at the position:
HP = [ 4 × ( HStart ) + 1 ] × VCLK clock cycle + ( one single-sized character width )
Where (HStart) is the decimal value of bits (HS4 to HS0); note 2.
2 to 0 VS2 to VS0 VStart field; defines the vertical start position of the first on-screen character row, as
approximately a multiple of 4 HSYNC pulses. Active display begins after the field’s time
reference point (a range of 3 to 31)at the position:
VP = [ 4 × ( VStart ) – 1 ] × HSYNC pulses
Where (VStart) is the decimal value of bits (VS2 to VS0); note 3.

Notes
1. Neither the Hstart nor Vstart parameter is affected by the D line attribute that is used to display double-sized
characters.
2. Counting variations in Wc, there may be 17 to 143 VCLK clock cycles from the end of HSYNC to the start of the first
character of each row.
3. Subsequent character rows occur directly below the first, such that the last scan line of one row is directly followed
by the first scan line of the next row. Successive New Line characters (with or without the Short Row designation)
can be used to vertically separate text rows on the screen.

1996 Mar 22 24
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

handbook, full pagewidth foreground

colour pixel

black pixel

background
colour pixel

apparent light
source
ShMode = 010 ShMode = 011 ShMode = 100

ShMode = 001 No Shadowing ShMode = 101

ShMode = 000 ShMode = 111 ShMode = 110 MBE773

ShMode = (SHM2, SHM1, SHM0)

Fig.8 Effect of shadowing on the letter ‘E’.

1996 Mar 22 25
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

14 PROGRAMMING CONSIDERATIONS
14.1 EPROM Characteristics
The 87C055 is programmed by using a modified Quick-Pulse Programming algorithm similar to that used for devices
such as the 87C751. It differs from these devices in that a serial data stream is used to place the 87C055 in the
programming mode.
Figure 9 shows a block diagram of the programming configuration for the 87C055.

Table 31 Pin usage for Programming

PIN USAGE
XTAL1 Oscillator input and receives the master system clock. This clock should be between
1.2 and 6 MHz.
RESET Used to accept the serial data stream that places the 87C055 into various programming modes.
This pattern consists of a 10-bit code with the LSB sent first. Each bit is synchronized to the
clock input, XTAL1.
Port 0
VPP/TDAC/P0.0 Used as the programming voltage supply input (VPP signal).
PROG/PWM1/P0.1 Used as the program PROG signal. This pin is used for the 25 programming pulses.
Port 2
P2.7 to P2.0 Address input for the byte to be programmed and accepts both the high- and low-order
components of the 11-bit address; note 1.
Port 3
P3.7 to P3.0 Used as a bidirectional data bus during programming and verify operations. During programming
mode, it accepts the byte to be programmed. During verify mode, it provides the contents of the
EPROM location specified by the address which has been supplied to Port 2.

Note
1. Multiplexing of these address components is performed using the ASEL input:
a) ASEL input is driven HIGH and then drive Port 2 with the high-order bits of the address. ASEL should remain
HIGH for at least 13 clock cycles.
b) ASEL may then be driven LOW which latches the high-order bits of the address internally. The high-order address
should remain on Port 2 for at least 2 clock cycles after ASEL is driven LOW.
c) Port 2 may then be driven with the low byte of the address. The low-order address will be internally stable 13 clock
cycles later. The address will remain stable provided that the low byte placed on Port 2 is held stable and ASEL
is kept LOW.
d) ASEL needs to be pulsed HIGH only to change the high byte of the address.

1996 Mar 22 26
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

14.2 Programming operation 14.3 Erasure Characteristics

Figures 10 and 11 show the timing diagrams for the Erasure of the EPROM begins to occur when the chip is
Program/Verify cycle. Programming operation: exposed to light with wavelengths shorter than
1. RST should initially be held HIGH for at least approximately 4000 Angstroms. Since sunlight and
2 machine cycles. P0.1 (PROG) and P0.0 (VPP) will be fluorescent lighting have wavelengths in this range,
at VOH as a result of the RST operation. At this point, exposure to these light sources over an extended time
these pins function as normal quasi-bidirectional I/O (about 1 week in sunlight, or 3 years in room level
ports and the programming equipment may pull these fluorescent lighting) could cause inadvertent erasure.
lines LOW. However, prior to sending the 10-bit code For this and secondary effects, it is recommended that an
on the RST pin, the programming equipment should opaque label be placed over the window. For elevated
drive these pins HIGH (VIH). temperature or environments where solvents are being
2. The RST pin may now be used as the serial data input used, apply Kapton tape Fluorless (part number 2345-5) or
for the data stream which places the 87C055 in the equivalent.
Programming Mode. Data bits are sampled during the
The recommended erasure procedure is exposure to
clock HIGH time and thus should only change during
ultraviolet light (at 2537 Angstroms) to an integrated dose
the time that the clock is LOW. Following transmission of at least 15 Ws/cm2.
of the last data bit, the RST pin should be held LOW.
Exposing the EPROM to an ultraviolet lamp of
3. Next the address information for the location to be
12000 µW/cm2 rating for 20 to 39 minutes, at a distance of
programmed is placed on Port 2 and ASEL is used to
about 1 inch, should be sufficient. Erasure leaves the array
perform the address multiplexing, as previously
in an all logic 1s state.
described (see Table 31; note 1).
a) At this time, Port 1 functions as an output. 14.4 Reading Signature Bytes
b) A high voltage VPP level is then applied to the VPP
The Signature Bytes are read by the same procedure as a
input (P0.0). This sets Port 1 as an input port.
normal verify of locations 30H and 31H (the values are
c) The data to be programmed into the EPROM array shown in Table 32), except that the serial code indicated in
is then placed on Port 3. This is followed by a Table 33 for reading signature bytes should be used.
series of programming pulses applied to the PROG
pin (P0.1). These pulses are created by driving Table 32 Programming and Verification codes
P0.1 LOW and then HIGH. This pulse is repeated
until a total of 25 programming pulses have ADDRESS CONTENT INDICATION
occurred. At the conclusion of the last pulse, the 30H 15H manufactured by Philips
PROG signal should remain HIGH.
31H 4BH 87C055
4. The VPP signal may now be driven to the VOH level,
placing the 87C055 in the Verify Mode; Port 3 is now Table 33 Implementing Program/Verify Modes
used as an output port. After four machine cycles
(48 clock periods), the contents of the addressed SERIAL P0.1 P0.0
OPERATION
location in the EPROM array will appear on Port 3. CODE (PROG) (VPP)
5. The next programming cycle may now be initiated by: Program user EPROM 286H −(1) VPP
a) Placing the address information at the inputs of the Verify user EPROM 286H VIH VIH
multiplexed buffers. Read Signature Bytes 280H VIH VIH
b) Driving the VPP pin to the VPP voltage level.
Note
c) Providing the byte to be programmed to Port 3 and
issuing the 26 programming pulses on the PROG 1. Pulsed from VIH to VIL and returned to VIH.
pin.
d) Bringing VPP back down to the VOH level and
verifying the byte (see Table 33).

1996 Mar 22 27
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

handbook, full pagewidth 8

A0-A15 P2.0-2.7 VDD 5V

ADDRESS STROBE P0.2/ASEL VSS

PROGRAMMING
P0.1
PULSES
87C055
VPP/VIH VOLTAGE
P0.0 8
SOURCE
P3.0-P3.7 DATA BUS
CLK SOURCE XTAL1

RESET
CONTROL RESET
LOGIC MBE767

Fig.9 Programming Configuration.

handbook, full pagewidth

XTAL1

min 2 machine
cycles
10-bit serial code

RESET BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9

P0.0 undefined

P0.1 undefined
MBE768

Fig.10 Entry into Program/Verify Modes.

1996 Mar 22 28
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

14.5 EPROM Programming and Verification

VDD = 5 V ±10%; VSS = 0 V; Tamb = 21 to 27 °C.

SYMBOL PARAMETER MIN. MAX. UNIT

1/tCLCL Oscillator/clock frequency 1.2 6 MHz
tAVGL(1) Address setup to P0.1 (PROG) LOW 10 + 24tCLCL − µs
tGHAX Address hold after P0.1 (PROG) HIGH 48tCLCL − µs
tDVGL Data setup to P0.1 (PROG) LOW 38tCLCL − µs
tGHDX Data hold after P0.1 (PROG) HIGH 36tCLCL − µs
tSHGL VPP setup to P0.1 (PROG) LOW 10 − µs
tGHSL VPP hold after P0.1 (PROG) HIGH 10 − µs
tGLGH P0.1 (PROG) width 90 110 µs
tAVQV(1) VPP (VDD) LOW to data valid − 48tCLCL µs
tGHGL P0.1 (PROG) HIGH to P0.1 (PROG) LOW 10 − µs
tSYNL P0.0 (sync pulse) LOW 4tCLCL − µs
tSYNH P0.0 (sync pulse) HIGH 8tCLCL − µs
tMASEL ASEL HIGH time 13tCLCL − µs
tHAHLD Address hold time 2tCLCL − µs
tHASET Address setup to ASEL 13tCLCL − µs
tADSTA Low address to address stable 13tCLCL − µs

Note
1. Address should be valid at least 24tCLCL before the rising edge of P0.0 (VPP).

handbook, full pagewidth 12.75 V

5V 5V
P0.0 [V (p-p)]
tSHGL tGHSL

25 PULSES

P0.1 (PROG)

tGLGH tGHGL
tMASEL
98µs MIN 10µs MIN

P0.2 (ASEL)

tHASET
tHAHLD

PORT 2 HIGH ADDRESS LOW ADDRESS

tDVGL tGHDX
tADSTA tAVQV

DATA TO BE
PORT 3 INVALID DATA VALID DATA PROGRAMMED INVALID DATA VALID DATA

verify mode program mode verify mode

MBE769

Fig.11 Program/Verify cycle.

1996 Mar 22 29
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

15 PROGRAMMING THE OSD EPROM Each character is 14 bits wide by 18 lines high.A character
is split about a vertical axis into two sections UPPER and
15.1 Overview
LOWER as illustrated in Table 34:
The OSD EPROM space starts at location C000H and • Each section contains 7 bits of the character, such that:
ends at location CFFFH. However, due to the addressing
– the LOWER section contains bits 7 to 1, and
scheme of the OSD, not all locations within this space are
used.The start location of the next character can be – the UPPER section contains bits 14 to 8.
calculated by adding 40H to the start location of the • The LOWER section of the character is programmed
previous character. For example, character 1 starts at when the LSB of the program address equals a logic 0,
C000H; then characters 2, 3, and 4 start at C040H, and the UPPER section when the LSB equals a logic 1.
C080H, and C0C0H, respectively.
During Programming and Verification, each section is
programmed using bytes of program data. The MSB of the
15.2 Character description and programming
program data is not used; however, the MSB location
An example of an OSD character bit map, and the program physically exists, and so will Program and Verify.
data to obtain that character is shown in Table 34.

15.3 OSD EPROM bit map

The mapping for the full OSD EPROM is shown in Table 35. To program the example character into the first character
location of the OSD EPROM would require the data at the address as shown in Table 34.

Table 34 Example of an OSD Character Bit Map (note 1)

CHARACTER BIT MAP PROGRAM DATA ADDRESS (HEX)
LINE UPPER LOWER
UPPER LOWER UPPER LOWER
(BIT 14 TO 8) (BIT 7 TO 1)
Line 1 0000000 0000000 X0000000 X0000000 C001 C000
Line 2 0000000 0000000 X0000000 X0000000 C003 C002
Line 3 0011110 0001100 X0011110 X0001100 C005 C004
Line 4 0011110 0001100 X0011110 X0001100 C007 C006
Line 5 0011110 0001100 X0011110 X0001100 C009 C008
Line 6 0011110 0001100 X0011110 X0001100 C00B C00A
Line 7 0011110 0001100 X0011110 X0001100 C00D C00C
Line 8 0011110 0001100 X0011110 X0001100 C00F C00E
Line 9 0011111 1111100 X0011111 X1111100 C011 C010
Line 10 0011111 1111100 X0011111 X1111100 C013 C012
Line 11 0011111 1111100 X0011111 X1111100 C015 C014
Line 12 0011110 0001100 X0011110 X0001100 C017 C016
Line 13 0011110 0001100 X0011110 X0001100 C019 C018
Line 14 0011110 0001100 X0011110 X0001100 C01B C01A
Line 15 0011110 0001100 X0011110 X0001100 C01D C01C
Line 16 0011110 0001100 X0011110 X0001100 C01F C01E
Line 17 0000000 0000000 X0000000 X0000000 C021 C020
Line 18 0000000 0000000 X0000000 X0000000 C023 C022

Note
1. X can be a logic 0 or logic 1, and will Program and Verify correctly.

1996 Mar 22 30
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

Table 35 OSD EPROM Bit Map

ADDRESS (HEX)
CHARACTER NO. CHARACTER LINE NO.
LOWER BYTE UPPER BYTE
0 C000 C001 1
C002 C003 2
C004 C005 3
C006 C007 4
C008 C009 5
C00A C00B 6
C00C C00D 7
C00E C00F 8
C010 C011 9
C012 C013 10
C014 C015 11
C016 C017 12
C018 C019 13
C01A C01B 14
C01C C01D 15
C01E C01F 16
C020 C021 17
C022 C023 18
C024 to C03F not used
1(1) C040 to C063 1 to 18
C064 to C07F not used
2(1) C080 to C0A3 1 to 18
C0A4 to C0BF not used
3 to 59(1) − −
60(2) CF00 to CF23 1 to 18
CF24 to CF3F not used
61(2) CF40 to CF63 1 to 18
CF64 to CF7F not used
62(2) CF80 to CFA3 1 to 18
CFA4 to CFBF not used
63(2) CFC0 to CFE3 1 to 18
CFE4 to CFFF not used

Notes
1. Characters 1 to 59 are setup in the similar way as character 0; due to space and simplicity this is not fully displayed.
2. Locations 60, 61, 62 and 63 should be programmed to logic 0s. The character names are: character no. 60 = Normal
Space; character no. 61 = New Line; character no. 62 = BSpace; character no. 63 = SplitBSpace.

1996 Mar 22 31
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

16 REGISTER MAP
Table 36 Register map
Values within parenthesis show the bit state after a reset operation; ‘X’ denotes an undefined state.
ADDR.
REGISTER 7 6 5 4 3 2 1 0
(HEX)
E0 ACC(1) ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0
(0) (0) (0) (0) (0) (0) (0) (0)
F0 B(1) B7 B6 B5 B4 B3 B2 B1 B0
(0) (0) (0) (0) (0) (0) (0) (0)
83 DPH DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0
(0) (0) (0) (0) (0) (0) (0) (0)
82 DPL DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0
(0) (0) (0) (0) (0) (0) (0) (0)
A8 IE(1) EA − − EVS ET1 EX1 ET0 EX0
(0) (X) (0) (0) (0) (0) (0) (0)
9A OSAD − OSAD6 OSAD5 OSAD4 OSAD3 OSAD2 OSAD1 OSAD0
(X) (X) (X) (X) (X) (X) (X) (X)
9F to 98 OSAT(1)(2) − − − E − SR D Sh
(X) (X) (X) (X) (X) (X) (X) (X)
OSAT(1)(3) − − − B − BC2 BC1 BC0
(X) (X) (X) (X) (X) (X) (X) (X)
OSAT(1)(4) − − − B − FC2 FC1 FC0
(X) (X) (X) (X) (X) (X) (X) (X)
99 OSDT − − OSDT5 OSDT4 OSDT3 OSDT2 OSDT1 OSDT0
(X) (X) (X) (X) (X) (X) (X) (X)
C0 OSCON(1) IV Pv Lv Ph Pc Po DH BFe
(X) (X) (X) (X) (X) (X) (X) (X)
C1 OSMOD Wc − Mode1 Mode0 − SHM2 SHM1 SHM0
(X) (X) (X) (X) (X) (X) (X) (X)
C2 OSORG HS4 HS3 HS2 HS1 HS0 VS2 VS1 VS0
(X) (X) (X) (X) (X) (X) (X) (X)
80 P0(1) P07 P06 P05 P04 P03 P02 P01 P00
(1) (1) (1) (1) (1) (1) (1) (1)
90 P1(1) P17 P16 P15 P14 P13 P12 P11 P10
(1) (1) (1) (1) (1) (1) (1) (1)
A0 P2(1) P27 P26 P25 P24 P23 P22 P21 P20
(1) (1) (1) (1) (1) (1) (1) (1)
B0 P3(1) P37 P36 P35 P34 P33 P32 P31 P30
(1) (1) (1) (1) (1) (1) (1) (1)
87 PCON − − − − GF1 GF0 − −
(0) (X) (X) (X) (X) (X) (X) (X)
D0 PSW(1) CY AC F0 RS1 RS0 OV − P
(0) (0) (0) (0) (0) (0) (0) (0)
D4 PWM0 PW0E − PV05 PV04 PV03 PV02 PV01 PV00
(0) (0) (0) (0) (0) (0) (0) (0)

1996 Mar 22 32
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

ADDR.
REGISTER 7 6 5 4 3 2 1 0
(HEX)
D5 PWM1 PW1E − PV15 PV14 PV13 PV12 PV11 PV10
(0) (0) (0) (0) (0) (0) (0) (0)
D6 PWM2 PW2E − PV25 PV24 PV23 PV22 PV21 PV20
(0) (0) (0) (0) (0) (0) (0) (0)
D7 PWM3 PW3E − PV35 PV34 PV33 PV32 PV31 PV30
(0) (0) (0) (0) (0) (0) (0) (0)
DC PWM4 PW4E − PV45 PV44 PV43 PV42 PV41 PV40
(0) (0) (0) (0) (0) (0) (0) (0)
DD PWM5 PW5E − PV55 PV54 PV53 PV52 PV51 PV50
(0) (0) (0) (0) (0) (0) (0) (0)
DE PWM6 PW6E − PV65 PV64 PV63 PV62 PV61 PV60
(0) (0) (0) (0) (0) (0) (0) (0)
DF PWM7 PW7E − PV75 PV74 PV73 PV72 PV71 PV70
(0) (0) (0) (0) (0) (0) (0) (0)
D8 SAD(1) VHi CH1 CH0 St SAD3 SAD2 SAD1 SAD0
(0) (0) (0) (0) (0) (0) (0) (0)
81 SP SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
(0) (0) (0) (0) (0) (0) (0) (0)
D3 TDACH TDE − TD13 TD12 TD11 TD10 TD9 TD8
(0) (0) (0) (0) (0) (0) (0) (0)
D2 TDACL TD7 TD0 TD1 TD2 TD3 TD4 TD5 TD6
(0) (0) (0) (0) (0) (0) (0) (0)
8F TCON(1) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
(0) (0) (0) (0) (0) (0) (0) (0)
8C TH0 TH07 TH06 TH05 TH04 TH03 TH02 TH01 TH00
(0) (0) (0) (0) (0) (0) (0) (0)
8D TH1 TH17 TH16 TH15 TH14 TH13 TH12 TH11 TH10
(0) (0) (0) (0) (0) (0) (0) (0)
8A TL0 TL07 TL06 TL05 TL04 TL03 TL02 TL01 TL00
(0) (0) (0) (0) (0) (0) (0) (0)
8B TL1 TL17 TL16 TL15 TL14 TL13 TL12 TL11 TL10
(0) (0) (0) (0) (0) (0) (0) (0)
89 TMOD GATE C/T M1 M0 GATE C/T M1 M0
(0) (0) (0) (0) (0) (0) (0) (0)
C3 RAMCHR for test purposes only
C4 RAMATT for test purposes only
Notes
1. Bit addressable.
2. With OSDT = New Line.
3. With OSDT = BSpace or SplitBSpace.
4. With OSDT = Any other character.

1996 Mar 22 33
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

17 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 34); see notes 1 and 2.
SYMBOL PARAMETER MIN. MAX. UNIT
VDD supply voltage 4.5 5.5 V
VI input voltage on any pin with respect to ground (VSS) −0.5 6.5 V
IOH maximum source current for all port lines − −1.5 mA
IOL maximum sink current for all port lines − 15 mA
Ptot total power dissipation − 1.5 W
Tamb operating ambient temperature 0 70 °C
Tstg storage temperature −65 150 °C

Notes
1. Stresses above those listed under Limiting Values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.

18 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ).

1996 Mar 22 34
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

19 DC CHARACTERISTICS
VDD = 5 V ±10% Tamb = 0 to +70 °C; all voltages with respect to VSS; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply
VDD operating supply voltage 4.5 5.0 5.5 V
IDD operating supply current VDD = 5.5 V; note 1 − − 30 mA
VIL LOW level input voltage −0.5 − 0.2VDD − 0.1 V
VIL1 LOW level input voltage; −0.5 − 0.15VDD V
VSYNC and HSYNC
VIH HIGH level input voltage; 0.7VDD − VDD + 0.5 V
XTAL, VCLK1 and RST
VIH1 HIGH level input voltage; P1.2 to P1.0, 0.2VDD + 0.9 − VDD + 0.5 V
P3.6 to P3.5 and P3.3 to P3.1
VIH2 HIGH level input voltage; 0.2VDD + 0.9 − 12.6 V
P1.3, P3.7,P3.4 and P3.0
VIH3 HIGH level input voltage; VSYNC and 0.67VDD − VDD + 0.5 V
HSYNC
VIH − VDD HIGH level input voltage with respect note 2 0.7VDD − VDD + 0.5 V
to VDD; Port 0, P1.3, P3.7, P3.4 and
P3.0
VOL1 LOW level output voltage; P2.7 to P2.0 IOL = 10 mA; note 3 − − 0.5 V
and P3.6 to P3.5
VOL2 LOW level output voltage; IOL = 700 µA; note 4 − − 0.5 V
TDAC and PWM0 to PWM7
VOL3 LOW level output voltage; all other IOL = 1.6 mA − − 0.45 V
outputs
VOH HIGH level output voltage; IOH = −60 µA 2.4 − − V
Port 1, VID2 to VID0, VCTRL and BF
RRST Reset (RST) pull-down resistor 50 − 300 kΩ
CIO Pin capacitance; except P0.0 and P0.7 test freq. = 1 MHz; − − 10 pF
Tamb = 25 °C; note 5
HYS Hysteresis; VSYNC and HSYNC 0.8 − − V

Notes
1. IDD measured with OSD block initialized and RST remaining LOW.
2. This maximum applies at all times, including during power switching, and must be accounted for in power supply
design. During a Power-on process, the +12 V source used for external pull-up resistors should not precede the VDD
of the 83C055 up their respective voltage ramps by more than this margin, nor, during a Power-down process, should
VDD precede +12 V down their respective voltage ramps by more than this margin.
3. No more than 6 (any 6) of these 10 high current outputs may be used at the VOL1 (IOL = 10 mA) specification.
The other 4 should comply with the VOL3 specification (IOL = 1.6 mA).
4. The specified current rating applies when any of these pins is used as a Pulse Width Modulated (PWM) output.
For use as a port output, the rating is as given subsequently.
5. The capacitance of pins P0.0 and P0.7 for the 87C055 exceeds 10 pF; for P0.0 this is maximum 40 pF, while for P0.7
it is maximum 20 pF.

1996 Mar 22 35
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

20 AC CHARACTERISTICS
VDD = 5 V ±10%; Tamb = 0 to +70 °C; all voltages with respect to VSS; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1/tCLCL XTAL frequency note 1 6 − 12 MHz
tCHCX XTAL1 clock HIGH time note 2 20 − − ns
tCLCX XTAL1 clock LOW time 20 − − ns
tCLCH XTAL1 clock rise time − − 20 ns
tCHCL XTAL1 clock fall time 5 − 20 ns
1/tVCLCL VCLK frequency 5 − 8 MHz
tVCOH − tVCOL Rise versus fall time skew on any one of note 3 − − 40 ns
VID2 to VID0, VCTRL and BF
tVCOH1 − tVCOH2 Rise time skew between any two of − − 30 ns
VID2 to VID0, VCTRL and BF
tVCOL1 − tVCOL2 Fall time skew between any two of − − 30 ns
VID2 to VID0, VCTRL and BF

Notes
1. The 83C055 is tested at its maximum XTAL frequency, but not at any other (lower) rate.
2. These parameters apply only when an external clock signal is used.
3. These parameters assume equal loading at CL = 100 pF, for all the referenced outputs. These parameters are
specified but not tested.

1996 Mar 22 36
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

21 PACKAGE OUTLINES

SDIP42: plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1
seating plane

D ME

A2 A

L
A1
c
Z e w M (e 1)
b1
MH

b
42 22

pin 1 index
E

1 21

0 5 10 mm
scale

DIMENSIONS (mm are the original dimensions)

UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.3 0.53 0.32 38.9 14.0 3.2 15.80 17.15
mm 5.08 0.51 4.0 1.778 15.24 0.18 1.73
0.8 0.40 0.23 38.4 13.7 2.9 15.24 15.90

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

90-02-13
SOT270-1
95-02-04

1996 Mar 22 37
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

22 SOLDERING The device may be mounted to the seating plane, but the
temperature of the plastic body must not exceed the
22.1 Introduction
specified storage maximum. If the printed-circuit board has
There is no soldering method that is ideal for all IC been pre-heated, forced cooling may be necessary
packages. Wave soldering is often preferred when immediately after soldering to keep the temperature within
through-hole and surface mounted components are mixed the permissible limit.
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for 22.3 Repairing soldered joints
printed-circuits with high population densities. In these
Apply a low voltage soldering iron (less than 24 V) to the
cases reflow soldering is often used.
lead(s) of the package, below the seating plane or not
This text gives a very brief insight to a complex technology. more than 2 mm above it. If the temperature of the
A more in-depth account of soldering ICs can be found in soldering iron bit is less than 300 °C it may remain in
our “IC Package Databook” (order code 9398 652 90011). contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
22.2 Soldering by dip or wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

23 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

24 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Mar 22 38
Philips Semiconductors Product specification

83C145; 83C845
Microcontrollers for TV and video (MTV)
83C055; 87C055

NOTES

1996 Mar 22 39
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Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, 457041/1100/01/pp40 Date of release: 1996 Mar 22
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