MJD340(NPN),

MJD350(PNP)
High Voltage Power
Transistors
DPAK for Surface Mount Applications
Designed for line operated audio output amplifier, switchmode www.onsemi.com
power supply drivers and other switching applications.
Features SILICON
• Lead Formed for Surface Mount Applications in Plastic Sleeves POWER TRANSISTORS
(No Suffix) 0.5 AMPERE
• Electrically Similar to Popular MJE340 and MJE350 300 VOLTS, 15 WATTS
• Epoxy Meets UL 94 V−0 @ 0.125 in
• NJV Prefix for Automotive and Other Applications Requiring COLLECTOR COLLECTOR
Unique Site and Control Change Requirements; AEC−Q101 2, 4 2, 4
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant 1 1
BASE BASE
MAXIMUM RATINGS
3 3
Rating Symbol Max Unit EMITTER EMITTER
Collector−Emitter Voltage VCEO 300 Vdc
Collector−Base Voltage VCB 300 Vdc 4
Emitter−Base Voltage VEB 3 Vdc
1 2
Collector Current − Continuous IC 0.5 Adc 3
Collector Current − Peak ICM 0.75 Adc DPAK
Total Power Dissipation PD CASE 369C
@ TC = 25°C 15 W STYLE 1
Derate above 25°C 0.12 W/°C
Total Power Dissipation (Note 1) PD MARKING DIAGRAM
@ TA = 25°C 1.56 W
Derate above 25°C 0.012 W/°C
Operating and Storage Junction TJ, Tstg −65 to +150 °C AYWW
Temperature Range J3x0G
ESD − Human Body Model HBM V
MJD340 (NPN) 3B
MJD350 (PNP) 2
A = Assembly Location
ESD − Machine Model MM V
Y = Year
MJD340 (NPN) M4
MJD350 (PNP) M4 WW = Work Week
J3x0 = Device Code
Stresses exceeding those listed in the Maximum Ratings table may damage the x= 4 or 5
device. If any of these limits are exceeded, device functionality should not be
G = Pb−Free Package
assumed, damage may occur and reliability may be affected.
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended. ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

June, 2016 − Rev. 12 MJD340/D
 MJD340 (NPN), MJD350 (PNP)

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction−to−Case RqJC 8.33 °C/W
Thermal Resistance, Junction−to−Ambient (Note 2) RqJA 80 °C/W
Leading Temperature for Soldering Purpose TL 260 °C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
2. These ratings are applicable when surface mounted on the minimum pad sizes recommended.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
OFF CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Collector−Emitter Sustaining Voltage (Note 3) VCEO(sus) V
(IC = 1 mA, IB = 0) 300 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Collector Cutoff Current ICEO mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VCB = 300 V, IE = 0) − 0.1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Emitter Cutoff Current IEBO mA
(VBE = 3 V, IC = 0) − 0.1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ON CHARACTERISTICS (Note 3)
DC Current Gain hFE −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(IC = 50 mA, VCE = 10 V) 30 240

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Collector−Emitter Saturation Voltage VCE(sat) V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(IC = 100 mA, IB = 10 mA) − 1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Base−Emitter On Voltage VBE(on) V
(IC = 1 A, VCE = 10 V) − 1.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DYNAMIC CHARACTERISTICS
Current Gain − Bandwidth Product fT MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(IC = 50 mA, VCE = 10 V, f = 10 MHz) 10 −
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

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2
 MJD340 (NPN), MJD350 (PNP)

TYPICAL CHARACTERISTICS

MJD340
300

200 VCE = 2 V
VCE = 10 V
hFE , DC CURRENT GAIN

TJ = 150°C
100
70
+100°C
50
+25°C
30

20 -55°C

10
1 2 3 5 7 10 20 30 50 70 100 200 300 500
IC, COLLECTOR CURRENT (mAdc)

Figure 1. DC Current Gain

MJD340
1
TJ = 25°C
0.8 VBE(sat) @ IC/IB = 10
V, VOLTAGE (VOLTS)

0.6 VBE @ VCE = 10 V

0.4

VCE(sat) @ IC/IB = 10
0.2
IC/IB = 5
0
10 20 30 50 100 200 300 500
IC, COLLECTOR CURRENT (mA)
Figure 2. “On” Voltages

MJD350 MJD350
200 1 1
TJ = 150°C
TJ = 25°C

25°C 0.8
100 VBE(sat) @ IC/IB = 10
hFE , DC CURRENT GAIN

V, VOLTAGE (VOLTS)

70
-55°C 0.6 VBE @ VCE = 10 V
50

0.4 IC/IB = 10
30

20 VCE = 2 V 0.2
VCC = 10 V
VCE(sat)
IC/IB = 5
10 0
5 7 10 20 30 50 70 100 200 300 500 5 7 10 20 30 50 70 100 200 300 500
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 3. DC Current Gain Figure 4. “On” Voltages

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3
 MJD340 (NPN), MJD350 (PNP)

1
0.7 D = 0.5
0.5
RESISTANCE (NORMALIZED)
r(t), TRANSIENT THERMAL

0.3 0.2
0.2 0.1 P(pk)
RqJC(t) = r(t) RqJC
0.05 RqJC = 8.33°C/W MAX
0.1
D CURVES APPLY FOR POWER
0.07 0.01
PULSE TRAIN SHOWN t1
0.05 READ TIME AT t1 t2
TJ(pk) - TC = P(pk) qJC(t) DUTY CYCLE, D = t1/t2
0.03 SINGLE PULSE
0.02

0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1k
t, TIME (ms)

Figure 5. Thermal Response

1000 There are two limitations on the power handling ability of

100 ms
500 a transistor: average junction temperature and second
300 500 ms breakdown. Safe operating area curves indicate IC − VCE
IC, COLLECTOR CURRENT (mA)

200
1 ms limits of the transistor that must be observed for reliable
100 operation; i.e., the transistor must not be subjected to greater
50 dissipation than the curves indicate.
30 dc The data of Figure 6 is based on TJ(pk) = 150_C; TC is
20
variable depending on conditions. Second breakdown pulse
10 limits are valid for duty cycles to 10% provided TJ(pk)
5 ≤ 150_C. TJ(pk) may be calculated from the data in
3 Figure 5. At high case temperatures, thermal limitations will
2
reduce the power that can be handled to values less than the
1 limitations imposed by second breakdown.
10 20 30 50 70 100 200 300 500 700 1000
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)

Figure 6. Active Region Safe Operating Area

TA TC
2.5 25
PD, POWER DISSIPATION (WATTS)

2 20

1.5 15
TA
1 10 TC

0.5 5

0 0
25 50 75 100 125 150
T, TEMPERATURE (°C)

Figure 7. Power Derating

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4
 MJD340 (NPN), MJD350 (PNP)

ORDERING INFORMATION
Device Package Shipping†
MJD340G DPAK 75 Units / Rail
(Pb−Free)

MJD340RLG DPAK 1,800 / Tape & Reel

(Pb−Free)

MJD340T4G DPAK 2,500 / Tape & Reel

(Pb−Free)

NJVMJD340T4G DPAK 2,500 / Tape & Reel

(Pb−Free)

MJD350G DPAK 75 Units / Rail

(Pb−Free)

MJD350T4G DPAK 2,500 / Tape & Reel

(Pb−Free)

NJVMJD350T4G DPAK 2,500 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

4 DPAK (SINGLE GAUGE)

CASE 369C
ISSUE F
1 2 DATE 21 JUL 2015
3
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
A Y14.5M, 1994.
E C 2. CONTROLLING DIMENSION: INCHES.
A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3 MENSIONS b3, L3 and Z.
B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4 NOT EXCEED 0.006 INCHES PER SIDE.
L3 Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE
D OUTERMOST EXTREMES OF THE PLASTIC BODY.
DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUM
1 2 3 PLANE H.
7. OPTIONAL MOLD FEATURE.

L4 INCHES MILLIMETERS
NOTE 7
DIM MIN MAX MIN MAX
b2 c BOTTOM VIEW A 0.086 0.094 2.18 2.38
e SIDE VIEW A1 0.000 0.005 0.00 0.13
b b 0.025 0.035 0.63 0.89
0.005 (0.13) M C b2 0.028 0.045 0.72 1.14
TOP VIEW b3 0.180 0.215 4.57 5.46
c 0.018 0.024 0.46 0.61
c2 0.018 0.024 0.46 0.61
H Z Z D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
GAUGE SEATING
L2 PLANE C PLANE
H 0.370 0.410 9.40 10.41
L 0.055 0.070 1.40 1.78
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
L BOTTOM VIEW L3 0.035 0.050 0.89 1.27
A1 L4 −−− 0.040 −−− 1.01
L1 ALTERNATE
Z 0.155 −−− 3.93 −−−
CONSTRUCTIONS
DETAIL A
ROTATED 905 CW GENERIC
MARKING DIAGRAM*
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:
PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE
2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 2. ANODE
3. EMITTER 3. SOURCE 3. ANODE 3. GATE 3. CATHODE
4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 4. ANODE XXXXXXG AYWW
ALYWW XXX
STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: XXXXXG
PIN 1. MT1 PIN 1. GATE PIN 1. N/C PIN 1. ANODE PIN 1. CATHODE
2. MT2 2. COLLECTOR 2. CATHODE 2. CATHODE 2. ANODE
3. GATE 3. EMITTER 3. ANODE 3. RESISTOR ADJUST 3. CATHODE
4. MT2 4. COLLECTOR 4. CATHODE 4. CATHODE 4. ANODE
IC Discrete

SOLDERING FOOTPRINT* XXXXXX = Device Code

A = Assembly Location
6.20 3.00 L = Wafer Lot
0.244 0.118 Y = Year
2.58
0.102 WW = Work Week
G = Pb−Free Package

5.80 *This information is generic. Please refer

1.60 6.17 to device data sheet for actual part
0.228 0.063 0.243 marking.

SCALE 3:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

DOCUMENT NUMBER: 98AON10527D Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed
STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD: REF TO JEDEC TO−252
© Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number:
October, DESCRIPTION:
2002 − Rev. 0 DPAK SINGLE GAUGE SURFACE 1 MOUNT PAGE 1 OFXXX2
 DOCUMENT NUMBER:
98AON10527D

PAGE 2 OF 2

ISSUE REVISION DATE

O RELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001
A ADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008
B ADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009
C ADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009
D RELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A. 29 JUN 2010
CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE.
E ADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS 06 FEB 2014
b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAM-
BALIZA.
F ADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K. 21 JUL 2015
MUSTAFA.

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© Semiconductor Components Industries, LLC, 2015 Case Outline Number:

July, 2015 − Rev. F 369C
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