MX28F1000P

1M-BIT [128K x 8] CMOS FLASH MEMORY

FEATURES
• 131,072 bytes by 8-bit organization – Seven 16-KB blocks
• Fast access time: 70ns(Vcc:5V±5%; CL:35pF) • Auto Erase (chip & block) and Auto Program
90/120ns(Vcc:5V±10%; CL:100pF) – DATA polling
• Low power consumption – Toggle bit
– 50mA maximum active current • 10,000 minimum erase/program cycles
– 100uA maximum standby current • Latch-up protected to 100mA from -1 to VCC+1V
• Programming and erasing voltage 12V ± 5% • Advanced CMOS Flash memory technology
• Command register architecture • Compatible with JEDEC-standard byte-wide 32-pin
– Byte Programming (15us typical) EPROM pinouts
– Auto chip erase 5 seconds typical • Package type:
(including preprogramming time) – 32-pin plastic DIP
– Block Erase – 32-pin PLCC
• Optimized high density blocked architecture – 32-pin TSOP (Type 1)
– Four 4-KB blocks

GENERAL DESCRIPTION

The MX28F1000P is a 1-mega bit Flash memory or- MX28F1000P uses a 12.0V ± 5% VPP supply to
ganized as 128K bytes of 8 bits each. MXIC's Flash perform the Auto Program/Erase algorithms.
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The The highest degree of latch-up protection is
MX28F1000P is packaged in 32-pin PDIP, PLCC achieved with MXIC's proprietary non-epi process.
and TSOP. It is designed to be reprogrammed and Latch-up protection is proved for stresses up to 100
erased in-system or in-standard EPROM program- milliamps on address and data pin from -1V to VCC
mers. + 1V.

The standard MX28F1000P offers access times as

fast as 70 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate
bus contention, the MX28F1000P has separate chip
enable (CE) and output enable (OE ) controls.

MXIC's Flash memories augment EPROM function-

ality with in-circuit electrical erasure and
programming. The MX28F1000P uses a command
register to manage this functionality, while
maintaining a standard 32-pin pinout. The
command register allows for 100% TTL level control
inputs and fixed power supply levels during erase
and programming, while maintaining maximum
EPROM compatibility.

MXIC Flash technology reliably stores memory con-

tents even after 10,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The

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This datasheet has been downloaded from http://www.digchip.com at this page

 MX28F1000P

MX28F1000P Block Address and Block Structure

A16 A15 A14 A13 A12 A[16:0]

1FFFF
1 1 1 1 1 4k 1F000
1EFFF
1 1 1 1 0 4k 1E000
1DFFF
1 1 1 0 1 4k 1D000
1CFFF
1 1 1 0 0 4k 1C000
1BFFF

1 1 0 X X 16k
18000
17FFF

1 0 1 X X 16k
14000
13FFF

1 0 0 X X 16k
10000
0FFFF

0 1 1 X X 16k
0C000
0BFFF

0 1 0 X X 16k
08000
07FFF

0 0 1 X X 16k
04000
03FFF

0 0 0 X X
16k
00000

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 MX28F1000P

PIN CONFIGURATIONS

32 PDIP TSOP (TYPE 1)

VPP 1 32 VCC A11 1 32 OE
A16 2 31 WE A9 2 31 A10
A15 3 30 NC A8 3 30 CE
A12 4 29 A14 A13 4 29 Q7
A7 5 28 A13 A14 5 28 Q6
MX28F1000P

A6 6 27 A8 NC 6 27 Q5
A5 7 26 A9 WE 7 26 Q4
A4 8 25 A11 VCC 8 MX28F1000P 25 Q3
OE VPP 9 24 GND
A3 9 24
A16 10 23 Q2
A2 10 23 A10
A15 11 22 Q1
A1 11 22 CE
A12 12 21 Q0
A0 12 21 Q7
A7 13 20 A0
Q0 13 20 Q6
A6 14 19 A1
Q1 14 19 Q5
A5 15 18 A2
Q2 15 18 Q4 A4 16 17 A3
GND 16 17 Q3

(NORMAL TYPE)

32 PLCC
OE 32 1 A11
VCC
VPP
A12

A15

A16

WE

NC

A10 31 2 A9
CE 30 3 A8
4 1 32 30 Q7 29 4 A13
A7 5 29 A14 Q6 28 5 A14
A6 A13 Q5 27 6 NC
Q4 26 7 WE
A5 A8
Q3 25 MX28F1000P 8 VCC
A4 A9 GND 24 9 VPP
9 MX28F1000P 25 Q2 23 10 A16
A3 A11
Q1 22 11 A15
A2 OE Q0 21 12 A12
A1 A10 A0 20 13 A7
A1 19 14 A6
A0 CE
A2 18 15 A5
Q0 13 21 Q7 A3 17 16 A4
14 17 20

(REVERSE TYPE)
Q1

Q2

VSS

Q3

Q4

Q5

Q6

PIN DESCRIPTION:

SYMBOL PIN NAME

A0~A16 Address Input
Q0~Q7 Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write enable Pin
VPP Program Supply Voltage
VCC Power Supply Pin (+5V)
GND Ground Pin

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 MX28F1000P

BLOCK DIAGRAM

CE CONTROL PROGRAM/ERASE MODE

OE INPUT HIGH VOLTAGE LOGIC
WE LOGIC

STATE

X-DECODER
MX28F1000P REGISTER
ADDRESS FLASH
LATCH ARRAY ARRAY
A0-A16 SOURCE
AND HV COMMAND
Y-DECODER

DATA
BUFFER Y-PASS GATE
DECODER

PGM
SENSE DATA
AMPLIFIER
COMMAND
HV
DATA LATCH

PROGRAM
DATA LATCH

Q0-Q7 I/O BUFFER

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 MX28F1000P

AUTOMATIC PROGRAMMING AUTOMATIC ERASE ALGORITHM

The MX28F1000P is byte programmable using the MXIC's Automatic Erase algorithm requires the user to
Automatic Programming algorithm. The Automatic only write an erase set-up command and erase com-
Programming algorithm does not require the system to mand. The device will automatically pre-program and
time out or verify the data programmed. The typical verify the entire array. Then the device automatically
room temperature chip programming time of the times the erase pulse width, provides the erase verify,
MX28F1000P is less than 5 seconds. and counts the number of sequences. A status bit
similar to DATA polling and a status bit toggling
between consecutive read cycles, provide feedback to
the user as to the status of the erase operation.
AUTOMATIC CHIP ERASE

The device may be erased using the Automatic Erase Commands are written to the command register using
algorithm. The Automatic Erase algorithm automati- standard microprocessor write timings. Register con-
cally programs the entire array prior to electrical erase. tents serve as inputs to an internal state-machine
The timing and verification of electrical erase are which controls the erase and programming circuitry.
controlled internal to the device. During write cycles, the command register internally
latches address and data needed for the programming
and erase operations. For system design simplifica-
tion, the MX28F1000P is designed to support either
AUTOMATIC BLOCK ERASE WE or CE controlled writes. During a system write
cycle, addresses are latched on the falling edge of WE
The MX28F1000P is block(s) erasable using MXIC's or CE whichever occurs last. Data is latched on the
Auto Block Erase algorithm. Block erase modes allow rising edge of WE or CE whichever occur first. To
blocks of the array to be erased in one erase cycle. simplify the following discussion, the WE pin is used as
The Automatic Block Erase algorithm automatically the write cycle control pin throughout the rest of this
programs the specified block(s) prior to electrical text. All setup and hold times are with respect to the
erase. The timing and verification of electrical erase WE signal.
are controlled internal to the device.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX28F1000P electri-
AUTOMATIC PROGRAMMING ALGORITHM cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed one byte at
MXIC's Automatic Programming algorithm requires a time using the EPROM programming mechanism of hot
the user to only write a program set-up command and electron injection.
a program command (program data and address). The
device automatically times the programming pulse
width, provides the program verify, and counts the
number of sequences. A status bit similar to DATA
polling and a status bit toggling between consecutive
read cycles, provide feedback to the user as to the
status of the programming operation.

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 MX28F1000P

TABLE 1. COMMAND DEFINITIONS

COMMAND BUS FIRST BUS CYCLE SECOND BUS CYCLE

CYCLES OPERATION ADDRESS DATA OPERATION ADDRESS DATA

Read Memory 1 Write X 00H

Read Identified codes 2 Write X 90H Read IA ID

Setup auto erase/ 2 Write X 30H Write X 30H

auto erase (chip)

Setup auto erase/ 2 Write X 20H Write EA D0H

auto erase (block)

Setup auto program/ 2 Write X 40H Write PA PD

program

Setup Erase/ 2 Write X 20H Write X 20H

Erase (chip)

Setup Erase/ 2 Write X 60H Write EA 60H

Erase (block)

Erase verify 2 Write EVA A0H Read X EVD

Reset 2 Write X FFH Write X FFH

Note:
IA = Identifier address
EA = Block of memory location to be erased
PA = Address of memory location to be pro-
grammed
ID = Data read from location IA during device iden-
tification
PD = Data to be programmed at location PA
EVA = Address of memory location to be read during
erase verify.
EVD = Data read from location EVA during erase
verify.
Auto modes have the build-in enchanced features.
Please use the auto erase mode whenever it is.

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 MX28F1000P

COMMAND DEFINITIONS

When low voltage is applied to the VPP pin, the con-

tents of the command register default to 00H, enabling
read-only operation.

Placing high voltage on the VPP pin enables read/write

operations. Device operations are selected by writing
specific data patterns into the command register. Ta-
ble 1 defines these MX28F1000P register commands.
Table 2 defines the bus operations of MX28F1000P.

TABLE 2. MX28F1000P BUS OPERATIONS

OPERATION VPP(1) A0 A9 CE OE WE DQ0-DQ7

READ-ONLY Read VPPL A0 A9 VIL VIL VIH Data Out
Output Disable VPPL X X VIL VIH VIH Tri-State
Standby VPPL X X VIH X X Tri-State
Read Silicon ID (Mfr)(2) VPPL VIL VID(3) VIL VIL VIH Data = C2H
Read Silicon ID (Device)(2) VPPL VIH VID(3) VIL VIL VIH Data = 1AH
READ/WRITE Read VPPH A0 A9 VIL VIL VIH Data Out(4)
Standby(5) VPPH X X VIH X X Tri-State
Write VPPH A0 A9 VIL VIH VIL Data In(6)

NOTES:
1. VPPL may be grounded, a no-connect with a resistor tied 3. VID is the Silicon-ID-Read high voltage.(11.5V to 13v)
to ground, or < VCC + 2.0V. VPPH is the programming 4. Read operations with VPP = VPPH may access array
voltage specified for the device. When VPP = VPPL, data or Silicon ID codes.
memory contents can be read but not written or erased. 5. With VPP at high voltage, the standby current equals ICC
2. Manufacturer and device codes may also be accessed + IPP (standby).
via a command register write sequence. Refer to Table 6. Refer to Table 1 for valid Data-In during a write operation.
1. All other addresses are don't care. 7. X can be VIL or VIH.

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 MX28F1000P

READ COMMAND device returns to the Read mode. The system is not
required to provide any control or timing during these
While VPP is high, for erase and programming, mem- operations.
ory contents can also be accessed via the read com-
mand. The read operation is initiated by writing 00H When using the Automatic Chip Erase algorithm, note
into the command register. Microprocessor read that the erase automatically terminates when
cycles retrieve array data. The device remains en- adequate erase margin has been achieved for the
abled for reads until the command register contents memory array(no erase verify command is required).
are altered. The margin voltages are internally generated in the
same manner as when the standard erase verify
The default contents of the register upon VPP power- command is used.
up is 00H. This default value ensures that no spurious
alteration of memory contents occurs during the VPP The Automatic set-up erase command is a command-
power transition. Where the VPP supply is hard-wired only operation that stages the device for automatic
to the MX28F1000P, the device powers up and electrical erasure of all bytes in the array. Automatic
remains enabled for reads until the command register set-up erase is performed by writing 30H to the
contents are changed. command register.

To command automatic chip erase, the command 30H

SILICON-ID-READ COMMAND must be written again to the command register. The
automatic chip erase begins on the rising edge of the
Flash-memories are intended for use in applications WE and terminates when the data on DQ7 is "1" and
where the local CPU alters memory contents. As such, the data on DQ6 stops toggling for two consecutive
manufacturer- and device-codes must be accessible read cycles, at which time the device returns to the
while the device resides in the target system. PROM Read mode.
programmers typically access signature codes by rais-
ing A9 to a high voltage. However, multiplexing high
voltage onto address lines is not a desired system- SET-UP AUTOMATIC BLOCK ERASE/ERASE
design practice. COMMANDS

The MX28F1000P contains a Silicon-ID-Read The automatic block erase does not require the device
operation to supplement traditional PROM- to be entirely pre-programmed prior to executing the
programming methodology. The operation is initiated Automatic set-up block erase command and
by writing 90H into the command register. Following Automatic block erase command. Upon executing the
the command write, a read cycle from address 0000H Automatic block erase command, the device automati-
retrieves the manufacturer code of C2H. A read cycle cally will program and verify the block(s) memory for an
from address 0001H returns the device code of 1AH. all-zero data pattern. The system is not required to
provide any controls or timing during these operations.

SET-UP AUTOMATIC CHIP ERASE/ERASE When the block(s) is automatically verified to contain
COMMANDS an all-zero pattern, a self-timed block erase and verify
begin. The erase and verify operations are complete
The automatic chip erase does not require the device when the data on DQ7 is "1" and the data on DQ6 stops
to be entirely pre-programmed prior to excuting the toggling for two consecutive read cycles, at which time
Automatic set-up erase command and Automatic chip the device returns to the Read mode. The system is
erase command. Upon executing the Automatic chip not required to provide any control or timing during
erase command, the device automatically will program these operations.
and verify the entire memory for an all-zero data
pattern. When the device is automatically verified to When using the Automatic Block Erase algorithm, note
contain an all-zero pattern, a self-timed chip erase and that the erase automatically terminates when adequate
verify begin. The erase and verify operations are erase margin has been achieved for the memory array
complete when the data on DQ7 is "1" at which time the (no erase verify command is required). The margin

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 MX28F1000P

voltages are internally generated in the same manner SET-UP CHIP ERASE/ERASE COMMANDS
as when the standard erase verify command is used.
Set-up Chip Erase is a command-only operation that
The Automatic set-up block erase command is a com- stages the device for electrical erasure of all bytes in
mand only operation that stages the device for auto- the array. The set-up erase operation is performed by
matic electrical erasure of selected blocks in the array. writing 20H to the command register.
Automatic set-up block erase is performed by writing
20H to the command register. To commence chip erasure, the erase command (20H)
must again be written to the register. The erase
To enter automatic block erase, the user must write operation begins with the rising edge of the WE pulse.
the command D0H to the command register. Block
addresses are loaded into internal register on the 2nd This two-step sequence of set-up followed by execu-
falling edge of WE. Each successive block load cycles, tion ensures that memory contents are not accidentally
started by the falling edge of WE, must begin within erased. Also, chip-erasure can only occur when high
30ms from the rising edge of the preceding WE. voltage is applied to the VPP pin. In the absence of this
Otherwise, the loading period ends and internal auto high voltage, memory contents are protected against
block erase cycle starts. When the data on DQ7 is "1" erasure.
and the data on DQ6 stops toggling for two
consecutive read cycles, at which time auto erase
ends and the device returns to the Read mode.

Refer to page 2 for detailed block address. SET-UP BLOCK ERASE/ERASE COMMANDS

Set-up Block Erase is a command-only operation that

stages the device for electrical erasure of all selected
block(s) in the array. The set-up erase operation is
performed by writing 60H to the command register.
SET-UP AUTOMATIC PROGRAM/PROGRAM
COMMANDS To enter block-erasure, the block erase command 60H
must be written again to the command register. The
The Automatic Set-up Program is a command-only block erase mode allows 1 to 8 blocks of the array to be
operation that stages the device for automatic pro- erased in one internal erase cycle. Internally, there are
gramming. Automatic Set-up Program is performed by 8 registers (flags) addressed by A14 to A16. First block
writing 40H to the command register. address is loaded into internal registers on the 2-nd
falling of WE. Each successive block load cycles,
Once the Automatic Set-up Program operation is per- started by the falling edge of WE, must begin within
formed, the next WE pulse causes a transition to an 30ms from the rising edge of the preceding WE. Other-
active programming operation. Addresses are wise, the loading period ends and internal block erase
internally latched on the falling edge of the WE pulse. cycle starts. When the data on DQ7 is "1" at which time
Data is internally latched on the rising edge of the WE auto erase ends and the device returns to the Read
pulse. The rising edge of WE also begins the mode.
programming operation. The system is not required to
provide further controls or timings. The device will
automatically provide an adequate internally
generated program pulse and verify margin. The
ERASE-VERIFY COMMAND
automatic programming operation is completed when
the data read on DQ6 stops toggling for two
After each erase operation, all bytes must be verified.
consecutive read cycles and the data on DQ7 and
The erase verify operation is initiated by writing A0H
DQ6 are equivalent to data written to these two bits, at
into the command register. The address for the byte to
which time the device returns to the Read mode (no
be verified must be supplied as it is latched on the
program verify command is required).
falling edge of the WE pulse.

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 MX28F1000P

The MX28F1000P applies an internally generated DATA POLLING-DQ7

margin voltage to the addressed byte. Reading FFH
from the addressed byte indicates that all bits in the The MX28F1000P also features Data Polling as a
byte are erased. method to indicate to the host system that the
Automatic Program or Erase algorithms are either in
The erase-verify command must be written to the progress or completed.
command register prior to each byte verification to
latch its address. The process continues for each byte While the Automatic Programming algorithm is in op-
in the array until a byte does not return FFH data, or the eration, an attempt to read the device will produce the
last address is accessed. complement data of the data last written to DQ7. Upon
completion of the Automatic Program algorithm an
In the case where the data read is not FFH, another attempt to read the device will produce the true data
erase operation is performed. (Refer to Set-up Erase/ last written to DQ7. The Data Polling feature is valid
Erase). Verification then resumes from the address of after the rising edge of the second WE pulse of the two
the last-verified byte. Once all bytes in the array have write pulse sequences.
been verified, the erase step is complete. The device
can be programmed. At this point, the verify operation While the Automatic Erase algorithm is in operation,
is terminated by writing a valid command (e.g. DQ7 will read "0" until the erase operation is com-
Program Set-up) to the command register. The High pleted. Upon completion of the erase operation, the
Reliability Erase algorithm, illustrates how commands data on DQ7 will read "1". The Data Polling feature is
and bus operations are combined to perform electrical valid after the rising edge of the second WE pulse of
erasure of the MX28F1000P. two write pulse sequences.

The Data Polling feature is active during Automatic

RESET COMMAND Program/Erase algorithms.

A reset command is provided as a means to safely

abort the erase- or program-command sequences. POWER-UP SEQUENCE
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort the The MX28F1000P powers up in the Read only mode. In
operation. Memory contents will not be altered. addition, the memory contents may only be altered after
Should program-fail or erase-fail happen, two successful completion of a two-step command sequence.
consecutive writes of FFH will reset the device to abort Power up sequence is not required.
the operation. A valid command must then be written
to place the device in the desired state.
SYSTEM CONSIDERATIONS
WRITE OPERATON STATUS
During the switch between active and standby condi-
TOGGLE BIT-DQ6 tions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
The MX28F1000P features a "Toggle Bit" as a method of these transient current peaks is dependent on the
to indicate to the host sytem that the Auto Program/ output capacitance loading of the device. At a
Erase algorithms are either in progress or completed. minimum, a 0.1uF ceramic capacitor (high frequency,
low inherent inductance) should be used on each
While the Automatic Program or Erase algorithm is in device between VCC and GND, and between VPP and
progress, successive attempts to read data from the GND to minimize transient effects. In addition, to
device will result in DQ6 toggling between one and overcome the voltage drop caused by the inductive
zero. Once the Automatic Program or Erase algorithm effects of the printed circuit board traces on FLASH
is completed, DQ6 will stop toggling and valid data will memory arrays, a 4.7uF bulk electrolytic capacitor
be read. The toggle bit is valid after the rising edge of should be used between VCC and GND for each eight
the second WE pulse of the two write pulse devices. The location of the capacitor should be close
sequences. to where the power supply is connected to the array.

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 MX28F1000P

NOTICE:
ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under ABSOLUTE MAXI-
RATING VALUE MUM RATINGS may cause permanent damage to the de-
vice. This is stress rating only and functional operational
Ambient Operating Temperature -40oC to 85oC sections of this specification is not implied. Exposure to ab-
Storage Temperature -65oC to 125oC solute maximum rating conditions for extended period may
affect reliability.
Applied Input Voltage -0.5V to 7.0V NOTICE:
Applied Output Voltage -0.5V to 7.0V Specifications contained within the following tables are sub-
ject to change.
VCC to Ground Potential -0.5V to 7.0V
A9 & VPP -0.5V to 13.5V

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
CIN Input Capacitance 14 pF VIN = 0V
COUT Output Capacitance 16 pF VOUT = 0V

READ OPERATION
DC CHARACTERISTICS
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
ILI Input Leakage Current 10 uA VIN = GND to VCC

ILO Output Leakage Current 10 uA VOUT = GND to VCC

IPP1 VPP Current 1 100 uA VPP = 5.5V

ISB1 Standby VCC current 1 mA CE = VIH

ISB2 1 100 uA CE = VCC + 0.3V

ICC1 Operating VCC current 30(NOTE4) mA IOUT = 0mA, f=1MHz

ICC2 50 mA IOUT = 0mA, f=11MHz

VIL Input Low Voltage -0.3(NOTE 1) 0.8 V

VIH Input High Voltage 2.4 VCC + 0.3 V

VOL Output Low Voltage 0.45 V IOL = 2.1mA

VOH Output High Voltage 2.4 V IOH = -400uA

NOTES:
1. VIL min. = -1.0V for pulse width < 50 ns. 3. Test condition:
VIL min. = -2.0V for pulse width < 20 ns. TA =-40°C to 85°C, Vcc = 5V±10%, Vpp = GND to Vcc, CL
2. VIH max. = VCC + 1.5V for pulse width < 20 ns = 100pF(for MX28F1000P-90/12)
If VIH is over the specified maximum value, read operation TA = -40°C to 85°C, Vcc = 5V±10%, Vpp = GND to Vcc, CL
cannot be guaranteed. = 35pF(for MX28F1000P-70)
4.ICC1=35mA for TA=-40°C to 85°C

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 MX28F1000P

AC CHARACTERISTICS
28F1000P-70 28F1000P-90 28F1000P-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 70 90 120 ns CE=OE=VIL

tCE CE to Output Delay 70 90 120 ns OE=VIL

tOE OE to Output Delay 30 35 50 ns CE=VIL

tDF OE High to Output Float (Note1) 0 15 0 20 0 30 ns CE=VIL

tOH Address to Output hold 0 0 0 0 ns CE=OE=VIL

TEST CONDITIONS: NOTE:

• Input pulse levels: 0.45V/2.4V 1. tDF is defined as the time at which the output achieves the
• Input rise and fall times: < 10ns open circuit condition and data is no longer driven.
• Reference levels for measuring timing: 0.8V, 2.0V
• 28F1000P-70:Vcc = 5V ± 5%, CL: 1TTL gate +
35pF(including scope and jig)
• 28F1000P-70:Vcc = 5V ± 5%, CL: 1TTL gate +
35pF(including scope and jig)
• Vpp = GND to Vcc

READ TIMING WAVEFORMS

ADDRESS

WE

CE
STANDBY MODE ACTIVE MODE STANDBY MODE
tCE

OE
tOE tDF

tACC tOH

DATA OUT DATA OUT VALID

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 MX28F1000P

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current 10 uA VIN=GND to VCC

ILO Output Leakage Current 10 uA VOUT=GND to VCC

ISB1 Standby VCC current 1 mA CE=VIH

ISB2 1 100 uA CE=VCC ± 0.3V

ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=1MHz

ICC2 50 mA IOUT=0mA, F=11MHz

ICC3 (Program) 50 mA In Programming

ICC4 (Erase) 50 mA In Erase

ICC5 (Program Verify) 50 mA In Program Verify

ICC6 (Erase Verify) 50 mA In Erase Verify

IPP1 (Read) VPP Current 100 uA VPP=12.6V

IPP2 (Program) 50 mA In Programming

IPP3 (Erase) 50 mA In Erase

IPP4 (Program Verify) 50 mA In Program Verify

IPP5 (Erase Verify) 50 mA In Erase Verify

VIL Input Voltage -0.3 (Note 5) 0.8 V

VIH 2.4 VCC+0.3V V

(Note 6)

VOL Output Voltage 0.45 V IOL=2.1mA

VOH 2.4 V IOH=-400uA

NOTES:
1. VCC must be applied before VPP and removed after VPP. 5. VIL min. = -0.6V for pulse width < 20ns.
2. VPP must not exceed 14V including overshoot. 6. If VIH is over the specified maximum value, programming
3. An influence may be had upon device reliability if the device operation cannot be guranteed.
is installed or removed while VPP=12V. 7. All currents are in RMS unless otherwise noted.(Sampled, not
4. Do not alter VPP either VIL to 12V or 12V to VIL when 100% tested.)
CE=VIL. 8. For 28F1000P-70, Vcc = 5V ±5%, CL = 35pF; for 28F1000P-
90/12, Vcc = 5V ± 10%, CL = 100pF.

P/N: PM0340 REV. 1.6, JAN. 19, 1999

13
 MX28F1000P

AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ± 10%, VPP =12V ± 5%

28F1000-70 28F1000P-90 28F1000P-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONTIONS

tVPS VPP setup time 100 100 100 ns

tOES OE setup time 100 100 100 ns

tCWC Command programming cycle 70 90 120 ns

tCEP WE programming pulse width 40 45 50 ns

tCEPH1 WE programming pluse width High 20 20 20 ns

tCEPH2 WE programming pluse width High 100 100 100 ns

tAS Address setup time 0 0 0 ns

tAH Address hold time 40 45 50 ns

tAH1 Address hold time for DATA POLLING 0 0 0 ns

tDS Data setup time 40 45 50 ns

tDH Data hold time 10 10 10 ns

tCESP CE setup time before DATA polling/toggle bit 100 100 100 ns

tCES CE setup time 0 0 0 ns

tCESC CE setup time before command write 100 100 100 ns

tCESV CE setup time before verify 6 6 6 us

tVPH VPP hold time 100 100 100 ns

tDF Output disable time (Note 3) 15 20 30 ns

tDPA DATA polling/toggle bit access time 70 90 120 ns

tAETC Total erase time in auto chip erase 5(TYP.) 5(TYP.) 5(TYP.) s

tAETB Total erase time in auto block erase 5TYP.) 5(TYP.) 5(TYP.) s

tAVT Total programming time in auto verify 15 300 15 300 15 300 us

tBALC Block address load cycle 0.3 30 0.3 30 0.3 30 us

tBAL Block address load time 200 200 200 us

tCH CE Hold Time 0 0 0 ns

tCS CE setup to WE going low 0 0 0 ns

NOTES:
1. CE and OE must be fixed high during VPP transition from 5V
to 12V or from 12V to 5V.
2. Refer to read operation when VPP=VCC about read opera-
tion while VPP 12V.
3. tDF defined as the time at which the output achieves the open
circuit condition and data is no longer driven.

P/N: PM0340 REV. 1.6, JAN. 19, 1999

14
 MX28F1000P

SWITCHING TEST CIRCUITS

DEVICE 1.8K ohm

+5V
UNDER
TEST

DIODES = IN3064
CL
6.2K ohm OR EQUIVALENT

CL = 100 pF including jig capacitance(35pF for 70 ns parts)

SWITCHING TEST WAVEFORMS

2.4 V
2.0V 2.0V
TEST POINTS
0.8V 0.8V
0.45 V
INPUT OUTPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are <20ns.

P/N: PM0340 REV. 1.6, JAN. 19, 1999

15
 MX28F1000P

AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verify in fast algorithm checking after automatic verify starts. Device outputs
and additional programming by external control are not DATA during programming and DATA after programming
required because these operations are excuted auto- on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle bit, DATA
matically by internal control circuit. Programming polling, timing waveform) are in high impedance.
completion can be verified by DATA polling and toggle bit

Setup auto program/

program command Auto program & DATA polling

Vcc 5V

12V
Vpp tVPH
0V tVPS

A0 ~ A16 Address
valid
tAS
WE tAH1

tCWC tAVT
CE
tCEPH1 tCEP tCESC
tOES tCEP tCESP tCES

OE
tDS tDH tDS tDH tDPA tDF

Q7 Command in Data in DATA DATA

DATA polling
Q0~Q5 Command in Data in DATA

Command #40H

P/N: PM0340 REV. 1.6, JAN. 19, 1999

16
 MX28F1000P

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Apply VppH

Write Set up auto program Command (40H)

Write Auto program Command(A/D)

NO
Toggle Bit Checking
DQ6 not Toggled

YES

NO
Verify Byte Ok

YES

NO Reset
Last Byte

YES

Auto Program Completed Auto Program Failed

P/N: PM0340 REV. 1.6, JAN. 19, 1999

17
 MX28F1000P

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External erase verify is not erase starts. Device outputs 0 during erasure and 1 after
required because data is erased automatically by internal erasure on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle
control circuit. Erasure completion can be verified by bit, DATA polling, timing waveform) are in high imped-
DATA polling and toggle bit checking after automatic ance.

Setup auto chip erase/

erase command Auto chip erase & DATA polling

Vcc 5V

12V
Vpp tVPH
0V tVPS

A0 ~ A16

WE

tCWC tAETC

CE
tOES tCEP tCEPH1 tCEP tCESP tCES tCESC

OE
tDS tDH tDS tDH tDPA tDF

Q7 Command in Command in

DATA polling
Q0~Q5 Command in Command in

Command #30H Command #30H

P/N: PM0340 REV. 1.6, JAN. 19, 1999

18
 MX28F1000P

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Apply VppH

Write Set up auto chip Erase Command (30H)

Write Auto chip Erase Command(30H)

Toggle Bit Checking No

DQ6 not Toggled

YES

DATA Polling No
DQ7 = 1

YES Reset

Auto Chip Erase Completed

Auto Chip Erase Failed

P/N: PM0340 REV. 1.6, JAN. 19, 1999

19
 MX28F1000P

AUTOMATIC BLOCK ERASE TIMING WAVEFORM

Block data indicated by A12 to A16 are erased. External checking after automatic erase starts. Device outputs 0
erase verify is not required because data are erased during erasure and 1 after erasure on Q7. Q0 to Q5 (Q6
automatically by internal control circuit. Erasure comple- is for toggle bit; see toggle bit, DATA polling, timing
tion can be verified by DATA polling and toggle bit waveform) are in high impedance.

Setup auto block erase/erase command Auto block erase & DATA polling

Vcc 5V

12V
Vpp
0V tVPH
tVPS

A0 ~ A11

Block Block Block

A12 ~ A16 address 0 address 1 address #
tAH1
tCH
CE
tCS
tAS tAH tCESC
tCWC tBALC tBAL tAETB

WE tCEPH1
tOES tCEP tCEP tCEPH2

OE
tDS tDH tDS tDH tDF
tDPA

Q7 Command in Command in

DATA polling
Q0~Q5 Command in Command in

Command #20H Command #D0H

*Refer to page 2 for detailed block address.

P/N: PM0340 REV. 1.6, JAN. 19, 1999

20
 MX28F1000P

AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART

START

Apply VppH

Write Set up auto block Erase Command (20H)

Write Auto block Erase Command(D0H)

to Load Block Address

Load Block Address

Last Block NO
to Erase

YES

Wait 200us

Toggle Bit Checking NO

DQ6 not Toggled
YES

DATA Polling NO
DQ7 = 1

YES Reset

Auto Block Erase Completed

Auto Block Erase Failed

P/N: PM0340 REV. 1.6, JAN. 19, 1999

21
 MX28F1000P

COMPATIBLE CHIP ERASE TIMING WAVEFORM

All data in chip are erased. Control verification and

additional erasure externally according tocompatible chip
erase flowchart.

Setup chip erase/

erase command Chip erase Erase Verify

Vcc 5V

12V
Vpp
tVPH
0V
tVPS

Verify
A0 ~ A16 Address

tAS tAH
WE

tET tCESV
tCWC

CE
tCEP tCES tCESC
tOES tCEP tCEPH1 tCEP

OE
tDS tDH tDS tDH tVA
tDS tDH tDF

Q7 Command in Command in Command in Data valid

Q0~Q6 Command in Command in Command in Data valid

Command #20H Command #20H Command #A0H

P/N: PM0340 REV. 1.6, JAN. 19, 1999

22
 MX28F1000P

COMPATIBLE BLOCK ERASE

This device can be applied to the compatible block erase x 8 block) without any voltage stress to the device nor
algorithm shown in the following flowchart. This algorithm deterioration in reliability of data.
allows to obtain faster erase time by the block (16K byte
COMPATIBLE BLOCK ERASE FLOWCHART

START

For selected block(s),

All bits PGM"0"

N=0

BLOCK ERASE FLOW

N = N+1

FAIL
NO
ERSVFY FLOW N = 1024?

ALL BITS VERIFIED YES

BLOCK ERASE FAIL

APPLY
VPP = VCC

END

BLOCK ERASE
COMPLETE

BLOCK ERASE FLOW

START

Apply
VPP = VPPH

WRITE SETUP BLOCK ERASE COMMAND

( 60H )

WRITE BLOCK ERASE COMMAND

( LOAD FIRST SECTOR ADDRESS , 60H )

LOAD OTHER SECTORS' ADDRESS

IF NECESSARY
( LOAD OTHER SECTOR ADDRESS )

WAIT
10 ms

END

P/N: PM0340 REV. 1.6, JAN. 19, 1999

23
 MX28F1000P

ERASE VERIFY FLOW

START

APPLY
VPP = VPPH

ADDRESS =
FIRST ADDRESS OF ERASED BLOCKS
OR LAST VERIFY FAILED ADDRESS

WRITE ERASE VERIFY COMMAND

( A0H )

WAIT 6 us

ERSVFY NO
INCREMENT ADDRESS FFH ?

YES

NO
LAST ADDRESS ?

YES

ERASE VERIFY GO TO ERASE FLOW

COMPLETE AGAIN OR ABORT

P/N: PM0340 REV. 1.6, JAN. 19, 1999

24
 MX28F1000P

COMPATIBLE BLOCK ERASE TIMING WAVEFORM

Indicated block data (16 Kbyte) are erased. Control

verification and additional erasure externally according to
compatible block erase flowchart.

Setup block erase/erase command Block erase Erase Verify

Vcc 5V

12V
Vpp
0V tVPS tVPH

Verify
A0 ~ A13 address

Block Block Block Verify

A14 ~ A16 address 0 address 1 address # address

tAS tAH
tAS tAH
WE

tCWC tBALC tBAL tET tCESV

CE
tCEPH1
tOES tCEP tCEP tCEPH2 tCEP tCESC
tCES

OE

tDS tDH tDS tDH tDS tDH tVA tDF

Q7 Command in Command in Command in Data valid

Q0~Q6 Command in Command in Command in Data valid

Command #60H Command #60H Command #A0H

P/N: PM0340 REV. 1.6, JAN. 19, 1999

25
 MX28F1000P

VPP HIGH READ TIMING WAVEFORM

Vcc 5V

12V
Vpp tVPS
0V tVPH

A0 - A16 Address valid

tCWC
WE
tACC
tCESC
CE
tOES
tOES
tCEP tCEPH1
tCE

OE
tDF

tDS tDH tOE tOH

Q0-Q7 Command in Data out valid

00H

VPP LOW ID CODE READ TIMING WAVEFORM

VID
VIH
A9
VIL

A0

A1 - A8
A10-A16

tACC tACC
VIH
WE
CE

tCE
OE
tDF

tOE tOH tOH

Q0 - Q7 Manufacturer code Device code

C2H 1AH

P/N: PM0340 REV. 1.6, JAN. 19, 1999

26
 MX28F1000P

VPP HIGH ID CODE READ TIMING WAVEFORM

Vcc 5V
12V
Vpp
tVPS
0V tVPH

A0 Address Valid 0 or 1

A1 - A16

tCWC
WE
tACC
tCESC

CE

tOES tOES
tCEP tCEPH2
tCE

OE
tDF

tDS tDH tOE tOH

Q0-Q7 Command in Data out valid

90H C2H or 1AH

RESET TIMING WAVEFORM

Vcc 5V

12V
Vpp tVPS
0V

A0 - A16

tCWC
WE

CE
tOES
tCEP tCEPH1 tCEP

OE
tDS tDH tDS tDH

Q0-Q7 Command in Command in

FFH FFH

P/N: PM0340 REV. 1.6, JAN. 19, 1999

27
 MX28F1000P

TOGGLE BIT, DATA POLLING TIMING WAVEFORM

Toggle bit appears in Q6, when program/erase is

opperating. DATA polling appears in Q7 during pro-
gramming or erase.

HIGH
WE
Vpp 12V
CE

OE

TOGGLE BIT
Q6 HIGH-Z
DATA
DURING P/E

DATA POLLING
Q7 HIGH-Z
DATA DATA DATA DATA
DURING P
HIGH-Z PROGRAM/ERASE COMPLETE
Q7
DURING E
DATA POLLING
HIGH-Z
Q0~Q5 DATA

ERASE AND PROGRAMMING PERFORMANCE

LIMITS
PARAMETER MIN. TYP. MAX. UNITS
Chip/Sector Erase Time 1.5 20 sec
Chip Programming Time 2 13.8 sec
Erase/Program Cycles 10,000 cycles
Byte Program Time 15 642 us

P/N: PM0340 REV. 1.6, JAN. 19, 1999

28
 MX28F1000P

ORDERING INFORMATION PLASTIC PACKAGE

PART NO. ACCESS TIME OPERATING STANDBY PACKAGE ERASE/PROGRAM
CURRENT CURRENT CYCLE
(ns) MAX.(mA) MAX.(uA) MIN.(time)
MX28F1000PPC-70C4 70 50 100 32 Pin DIP 10,000
MX28F1000PPC-90C4 90 50 100 32 Pin DIP 10,000
MX28F1000PPC-12C4 120 50 100 32 Pin DIP 10,000
MX28F1000PQC-70C4 70 50 100 32 Pin PLCC 10,000
MX28F1000PQC-90C4 90 50 100 32 Pin PLCC 10,000
MX28F1000PQC-12C4 120 50 100 32 Pin PLCC 10,000
MX28F1000PTC-70C4 70 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PTC-90C4 90 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PTC-12C4 120 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PRC-70C4 70 50 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PRC-90C4 90 50 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PRC-12C4 120 50 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PPI-70 70 50 100 32 Pin DIP 10,000
MX28F1000PPI-90 90 50 100 32 Pin DIP 10,000
MX28F1000PPI-12 120 50 100 32 Pin DIP 10,000
MX28F1000PQI-70 70 50 100 32 Pin PLCC 10,000
MX28F1000PQI-90 90 50 100 32 Pin PLCC 10,000
MX28F1000PQI-12 120 50 100 32 Pin PLCC 10,000
MX28F1000PTI-70 70 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PTI-90 90 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PTI-12 120 50 100 32 Pin TSOP 10,000
(Normal Type)
MX28F1000PRI-70 70 50 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PRI-90 90 50 100 32 Pin TSOP 10,000
(Reverse Type)
MX28F1000PRI-12 120 50 100 32 Pin TSOP 10,000
(Reverse Type)

P/N: PM0340 REV. 1.6, JAN. 19, 1999

29
 MX28F1000P

PACKAGE INFORMATION
32-PIN PLASTIC DIP

ITEM MILLIMETERS INCHES

A 42.13 max. 1.660 max. 32 17

B 1.90 [REF] .075 [REF]

C 2.54 [TP] .100 [TP]
D .46 [Typ.] .050 [Typ.]
E 38.07 1.500
F 1.27 [Typ.] .050 [Typ.]
1 16
G 3.30 ± .25 .130 ± .010
H .51 [REF] .020 [REF] A K
L
I 3.94 ± .25 1.55 ± .010
J 5.33 max. .210 max.
I J
K 15.22 ± .25 .600 ± .101
L 13.97 ± .25 .550 ± .010 H G

M .25 [Typ.] .010 [Typ.]

F
C
NOTE: Each lead certerline is located within D B M 0~15¡
.25mm[.01 inch] of its true position [TP] at a
E
maximum at maximum material condition.

32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)

A
ITEM MILLIMETERS INCHES
B
A 12.44 ± .13 .490 ± .005 1
4 32 30
B 11.50 ± .13 .453 ± .005
C 14.04 ± .13 .553 ± .005 5 29

D 14.98 ± .13 .590 ± .005

E 1.93 .076
F 3.30 ± .25 .130 ± .010
G 2.03 ± .13 .080 ± .005 9 25 C D

H .51 ± .13 .020 ± .005

I 1.27 [Typ.] .050 [Typ.]
J .71 [REF] .028 [REF]
13 21
K .46 [REF] .018 [REF]
L 10.40/12.94 .410/.510
14 20
17
(W) (L) (W) (L)
M .89R .035R E
N .25[Typ.] .010[Typ.]
F N
G
NOTE: Each lead certerline is located within H
.25mm[.01 inch] of its true position [TP] at a M
I
maximum at maximum material condition. K J

P/N: PM0340 REV. 1.6, JAN. 19, 1999

30
 MX28F1000P

32-PIN PLASTIC TSOP

ITEM MILLIMETERS INCHES

A 20.0 ± .20 .078 ± .006 A
B 18.40 ± .10 .724 ± .004 B
C 8.20 max. .323 max.
D 0.15 [Typ.] .006 [Typ.]
E .80 [Typ.] .031 [Typ.]
F .20 ± .10 .008 ± .004 C

G .30 ± .10 .012 ± .004

H .50 [Typ.] .020 [Typ.] O
N
I .45 max. .018 max. M

J 0 ~ .20 0 ~ .008
K 1.00 ± .10 .039 ± .004
L 1.27 max. .050 max.
M .50 .020 K L
D
N 0 ~5° .500
E J
F G H I
NOTE: Each lead certerline is located within
.25mm[.01 inch] of its true position [TP] at a
maximum at maximum material condition.

P/N: PM0340 REV. 1.6, JAN. 19, 1999

31
 MX28F1000P

Note. Revision History

Revision # Description Page Date
1.4 Fast access time 150ns and 1,000 times erase cycles removed.
Tsop pin configuration diagram rotated 180°.
The flow chart of block erase corrected.
1.5 Fast access time 70ns added. Dec/26/1996
1.6 1)Absolute max. ratings:TA=-40°C to 85°C P11 JAN/19/1999
2)DC Characteristics:ICC1=35mA for TA=-40°C to 85°C
3)AC Characteristics:TA=-40°C to 85°C P14
4)Order Informance:Add Industrial Grade P29
5)Erase & Programming Performance:New in Creased table

P/N: PM0340 REV. 1.6, JAN. 19, 1999

32
 MX28F1000P

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:
TEL:+886-3-578-8888
FAX:+886-3-578-8887

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TEL:+32-2-456-8020
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MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
33