POSTAL Study Course 2018 Computer Science & IT Objective Practice Sets Basics of Computer Design 2 CPUDesign 3 instruction Pipelining 9 Memory Hierarchy Design 2 Input-Output and Secondary Memory 4 Data Representation 2 | MADE EASY dale Boot mettate for IES GATE 6 PSUs For ‘MADE EASY Students Onlyerecta 1 Basics of Computer Design Cr 4. The computer performs all mathematical and logical operations inside its {@) memory unit (0) central processing unit (©) output unit (8) visual display unit 2. Which of the followings not involved in a memory write operation? {a) MAR (b) PC (© MOR (@) data bus 3, __InFlynn’s classification of computers, the vector and array classes of machines belong to (8) Single instruction/single data category (©) Single instruction/muttiple data category (©) Multipte instructionysingle data category (@) Multiple instruction/multiple data category 4, Thefollowing are four statements regarding what a CPU with only a set of 32 bit regist perform. 1. Hold and operate on 32 bit integers 2. Hold and operate on 16 bitintegers 3. Hold and operate on 64 bit floating point arithmetic 4, Hold and operate on 16 bit UNICODE characters, Which of the following is true about such a CPU? @) allaretrue —_(b) 1, 2andSonly (©) 1,2and4.only (¢) 1, 3and4 only 5. _Thefollowing are four statements about Reduced Instruction Set Computer (RISC) architectures. 1, The typical RISC machine instruction set is, small, and is usually a subset of a CISC instruction set 2. Noarithmetic or logical instruction can refer tothe memory directly. 3. A comparatively large number of user registers are available ‘4, Instructions can be easily decoded through hard-wired control units. Which of the above statements is true? (@) 1andSonly —(b) 1.3 and 4only (c) 1,2 and 3 only (4) all of these Which of the following statements is false about CisCarchitectures? (@) CISC machine instructions may include complex addressing modes, which require many clock cycles to carry out (©) CISC control units are typically micro- programmed, allowing the instruction set to be more flexible. (©) Inthe CISCinstruction set, all arthmetie/logic instructions must be register based. (d) CISC architectures may perform better in network centric applications than RISC. Consider the following registertransfer language Ryo Ry + MR, +R) where A, A are the CPU registers and Mis a memory location in primary memory. Which addressing mode is suitable for above register- transfer language? (@) immediate (b) indexed (©) direct (@) displacement Consider a high-level language statement while ['-I then which addressing mode is suitable for it? (@) autoincrement (0) indexed (©) displacement (d) autodecrement Match List-I with List-ll and select the corr answer using the codes given below t!10. " 12, ggmaAne Ensy List Regs[R,] — Regs{A,] + Regs{A] Regs[fi.] - Regs[A] +3 Regs|A,] — Regs[R,] + MemiRegs[R,] List 1. Immediate 2. Register 3. Displacement Codes: A 8B @ 3 2 ) 2 1 (ee (8) Noneotthe above Consider an (n + k) bit instruction with a Abit opcode and single mbit address. Then this instruction allow _______ operations and adoressable memory cells. (@) 2% ame (o) 24, ane (0) 22° (9) amt, ant c 1 3 ‘Tne following diagram shows, which addressing mode? [opoode | Lower Orcode | adaress | adaross (a) immediate addressing mode (©) indirect addressing mode (@) extended addressing mode (d) none of the above A CPU has an arithmetic unit that adds bytes and then sets its V, Cand Zag bits as follows. The V-bit is set if arithmetic overtlow occurs (in 2's complement arithmetic). The C-bit is set fa carry-outs generated from the most significant bit during an operation. The Z-bit is set if the result is zero. What are the values of the V, C and Z flag bit after B-bit byte 1100 1100 and 1000 1111 are added? www.madeeasy.in et kee ie) 2018] 13. 14. (emnoe Easy Computer Organization voc Zz @o o 0 1 1 0 (Ole @o 1 0 Consider the following sequence of instructions. intended for execution on a stack machine. Each arithmetic operation pops the second operand, then pops the first operand, operates on them, and then pushes the result back onto the stack Push b Push ox add Bp Push oc Push oy add Push ¢ suo ope) Which of the following statements is/are true? 1. If push and pop instructions each require 5 bytes of storage, and arithmetic operations each require 1 byte of storage then the instruction sequence as a whole requires a total of 40 bytes of storage. Atthe end of execution, zcontains the same value as y. 3. At the end of execution, the stack is empty. (@) tony (©) 2only (©) 2and3only —(d) 1 and 3only Match List-I with List-Il and select the correct answer using the codes given below thelist: List-1 List-Il A. MOVX, At 1, Three-address instruction B, STOREX 2, Zero-address nstuction ©. POPX — 3, One-addressiinstruction 4, ‘Two-address instruction Codes: Ae eC) @4 3 2 (O) Ge 27 @ 2 3 4 (d) None ofthese Objective Practice Sets [Ey| Computer Science & IT 15. Match List-I with List-il and select the correct answer using the codes given below the lists: List-I G-address instruction 1-address instruction 2-address instruction S-address instruction Lstetl vpogp> 1 2, 3. Y2A-B 4, ACC =ACC-x cD 3 4 1 2 Senne 16. Acertain processor executes the following set ‘of machine instructions sequentially MOV R,, #0 MOV R,, 100(F,) ‘ADD R,,200(R,) MOV 100(R,), R, Assuming that memory location 100 contains the value 35 (Hex), and the memory location 200 Contains the value 4 (Hex), what could be said about the final result? {@) Memory location 100 contains value Ad (0) Memory location 100 contains value DA (6) Memory location 100 contains value 03 (@) Memory location 200 contains value 35 17. Astack-based processor executes the following set of machine instructions sequentially. PUSH 100, PUSH 200, ADD POP 300 ‘Assuming that 1. memory location 100 contains the value 63 (Hex) and memory location 200 contains the value 4C(Hex), 2. the stack is byte organized and the stack pointer is at OOFF, and that (Ey objective Practice sets Eee 2013) GIMACE & 18, 19, 20, 21. f3mapeE G3 Made EAs 3. all PUSH and POP instructions have @ memory operand, Which of the following could the final result be? (2) Memory location 300 contains the value 9F (b) Memory location 0FD contains the value 9F (6) Memory location OOFF contains a value 100 (@) Memory location OOFE contains a value 200, Inacertain processor, a2 byte Jump instruction is encountered at memory address 2010H, the Jump instruction is in PC relative mode. The instruction is JMP -7 where ~7 is signed byte. Determine the Branch Target Address (@) 3008 H (b) 3009 (©) 3003H (@) 3007 H Processor XYZsupports only the immediate and the direct addressing modes. Which of the following programrring language data structures cannot be implemented on this processors? 1. Pointers 2, Arrays 3. Records (@) 1,2and3 (o) tand2 (b) 2and3 ( Only Word 20 contains 40 Word 30 contains 50 Word 40 contains 60 Word §0 contains 70 Which of the following instructions loads 60 into the accumulator? {@) loadimmediate 20 (b) load direct 30 (©) load indirect 20 (¢)_ load indirect 30 Match List-l with List-Il and select the correct, answer using the codes given below the lists: List-1 List-ll A. All]= BIJ; 1. Indirect addressing B. while[*Ar+]; 2. Indexed addressing C. inttemp = "x; 3, Autoincrement Codes: ABC feel a 1 3 2 2 3 1 () ae @ Ens wuwmadeeasy.in28. ACPUhas 24-bit ins GamAape EAsy 22, Consider the following program segment. Here At, Rand AB are the general purpose registers. wucton |_Opmenon —_areaton Ses MOV Rt, 3000] Ri < M3000) 2 2 oven) | Ree : op wa.et| Raho Re : Mov Ra | rol : Nem | Roe et : suztoce | eancronnetzee) 2 ‘Assume that the content of memory location 3000 is 10 and the content of the register 3 is 2000. The content of each of the memory locations from. 2000 to 2010 is 100. The program is loaded from the memory location 100. Allthe numbers are in decimal ‘Assume that the memory is word addressable. ‘Te number of memory references for accessing the data in executing the program completely is @ 10 14 © 2 (2 tuctions. A program starts lat address 300 (in decimal). Which one of the following is a legal program counter (all values indecimaly? (@) 400 (© eo (b) 500 (@ 700 24, Thememory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following programis executed MOVI Rs, 1 Move immediate LOAD Rd, 1000(Rs); Load frommemary ADDIRd, 1000; Addimmediate STOREIO(Rd), 20; Storeimmediate Which of the statements below is TRUE after the. programs executed? (@) memory location 1000 has value 20 (b) memory location 1020 has value 20 (©) memory location 1021 has value 20 (@) memory location 1004 has value 20 wurwamadeeasy.in Postal Study Course BXE| 26. 26. 27. fgmace Easy Computer Organization | 5 Consider the following assembly language program for a hypothetical processor. A, B and C are 8 bit integers. The meaning of various instructions are shown as comments. MovB.#0; 8-0 MOVC,#8; C8 Z: CMP C, #0; compare Cwith o rad jump to Xit zero flag is set SUBC, #1; CHC-1 LRCA, #1; Left rotate A through carry by one bit, Thus ifthe intial value of A and the carry flag are [email protected] and cO respectively, their values after the execution will be a6a5...a0c0 and a7 respectively, JC Y, Jump to Yif carry flag is set UMP 2; Jump to Z Y:ADD #1; BE B41 UMP Z; Jump to Z x ifthe inal value of register Ais A,, the value of register B after the program execution willbe fa) The number of 0 bits in A (0) The number of 1 bits in A OA @e Inthe program below, the number of times the FIRST and SECOND JNZ instructions cause the control to be transferred to LOOP respectively MVvI—H,02H Mvl 05H Loop DOR L FIRST JNZ LOOP oR oH SECOND: JNZ LOOP (@) Sand2 (b) 4and1 (©) 259and1 (a) 260and 1 Consider the following program segment for a hypothetical CPU having three user registers 1, Rand RB, Objective Practi SetsComputer Science & IT racion Size] Instruction Operation ee ao) MOV, 5000, |RI— Memory (S000]] 2 Mov Re, (Rt); | R2. HALTS Be OR tah: Re REI, fy ADD tah 3 ROR, +R, Inthe processor data transfer operations are 64 bit instruction, ALU operations are 32 bit instructions and branch instructions are 16 bit instructions. Objective Practice Sets [EyComputer Science & IT Program has been loaded in the memory with a starting address of 2000 decimal onwards. Ifan interruptis occurred during the execution of the haltinstruction what could be the return address pushed onto the stack stal Study Course PLE] GamaAoe easy (@) 117.45 Mwords/sec (b) 113.63 Mwords/sec (©) 217.45 Mwords/sec (@) 316.45 Mwords/sec 41. The format of double operand instruction of a 39, APCxelalive mode branch insirvationis 8 byte CPU consistof tts opcode and bis or source long. The address of instructon in decimal is and destination. 26 double operand instructions 2016. I signed displacement inthe inttuction and 184 single operand instructions musi be 15-11 then whats the branch target across of implemented, Wh wil be the total number of instruction? zero operand instructions canbe implemented? (a) 2014 (b) 2024 (a) 819200 (c) 2013 (d) 2023 () 409600 co 40. Consider 1GHz clock frequency processor, uses. {e) tx (d) None ofthese diferent operand access modes shown below Gpernd Accs Wode | Feaioney 60 42. Consider the hypothetical processor which has = 256 words memory, A 19 bits insuction is 7 placedin 1 memory cel. supports 2-address, bien o ‘adress and O-acdress instructions, it uses ease zi expanding opcode technique here exis ve 2-address instructions and 760 t-address Assume that @ eyele consumed for memory instructions, then number of O-address telerence, 4 eycles consumed for arithmetic Pecieees computation ang 0 cycles consumed when the operand is in register instruction itself. What is 7 the average operanditetch ate (in milion word sec) ofthe processor? [RENE 22sics of computer Design eee ee ee me eee CeCe CeMECCMiCCCC aes 10, VW. (c) 12 fo) 13. () 14. @ 15 (d) 16 (©) 17, @ 18 f@ 19. 20. (c) 21. (c) 22. (d) 23. (c) 24. (d) 25. (bo) 26. (©) 27. (b) 28. (c) 30. (d) 31. (b) 32. (b) 33. (c) 34 (©) 35. (d) 39. (c) 40. (b) a. @ (EFI objective Practice sets Gg MADE Easy wavwimadeeasy.inGa MADE EAS! Postal Study Course FUE) Basics of Computer Design Computer Organization | “ 7. (b) 14. (a) ‘The Register Transfer Language (RTL) is: 1. Two address instruction Aye A, + MR, + A} 2. One adress instruction in the given statement Fs the base ofan arcay 3. Zero address instruction and A represents an index so indexed addressing mode is suitabie fr given ATL. 15. (a) 3 address instruction 8. (d) Two operand locations anda result location are |n given while loop i is a pointer variable 60 explicitly contained in the instruction word. autodecrement addressing mode is suitable. oe es 41. () 2 adress instruction The diagram shows, extended addressing mode, ‘One of the addresses is used to specify both an In this, he etfective memory address directly ‘operand and the result location specified anditis used by some of the processor og. vex and address specitied is 16 bit adaress 1 address instruction cio Twoaddresses are implied the instuction and initally accumulator based operations voz 4100 1100 eg. ACC = ACC+X 000 ‘cool ait Oadaress instructions Atter Aditon They are applicable to a special memory 170 0104 1014 organization called a stack Itinteract wth a stack V.bitis sett 1 due to arthmetio overfiow. using push and pop operations All addresses C-bit is set to 1 because most significant digits are implied as in register based operations generates acerry, Top(¢-1) Zbitis set 100 because the resut of addition is watz 7.) PUSH 100 43. (6) PUSH 200 ‘There are 7 pushes and pops for a cost of 35. ADD bytes plus 3 arithmetic instructions fora total of POP 200 38 bytes storage. PUSH 100 will push the value at location 100 After Instruction Stack Contains (53,,) onto stak New Variables PUSH 200 wil push the value at location 200 Push b (AC, onto stack Push x Dx ADD will add the value and push the result onto ade be stack pope ° push c bex ober 53 push y benY c=bex abe aca bexty cebt+x ae push c bexty, Dexe=b+x She sub y c=b+x POP 300 wil pop the top value which is (9 F) pop z cabenzay from stack and store the value at location 300. wu. madeeasy.in fg Mabe Ensy Objective Practice Sets18, 20. 22, 23, is} | computer Science & IT (a) Tho Jump instruction is at address 3010 H anc instruction is 2 bytes. Theretore, PC points to 3012 Hon execution a this instruction Now Branch Target PC = PC + (-7) = 2012-7 H= 300BH (co) The given information can be understood as al «0 0, Seo 4o| 60 sol 7 | Now load indirect 20 will load 60 into as follows sal « JE po aorose 40 ence acy Foret sed so[ 70 Hence (0) is correct option () MOV 1 3000 M9000) 1 mamery reference Leep: MOV Re, RI R26 AAR} 1 oy rearence 200 RE, RO RHR MOV), 2 AARB}«- 2 memary france Ine ma macros Decet Rett 8X2 bop Har Total memory reference: loop runs +1 = 2x1041=21 2x Number of times (c) As the instruction are 24 bitor 3 bytes, the value of program counter at any time should be multiple 0f 3 starting from 300 like 300, 303, 306... from ‘options, '600" is multiple of 3 oF is included in above series, Objective Practice Sets Postal Study Course EXEE| 24, 25. 28, GgMRdDE ERs G3MAoE ERsy (a) [1000] = 18 Mp1001) =1 M1020) = 16 MOVER, 1 LOAD Ry, 1000(R) Ro MEYOOOER Roe Mi00061] = M1001) Root ‘ADDR, 1000 Rye Ree 1000 = 191000 STOREIO(R,).20 MORI 009 (b) A, 8, Care 8 bit integers, MOV 8, #0 Bao MOV C, #8 ces ZCMPC,#0 Compare Cwitho 2x SUBC, #1 ceac-1 c LRA, #1 cy IMPZ YADDB#1 Be B41 JMPZ x After execution of LRCA, #1, JCY is executed {and control goes tothe instruction Y: ADD B, #1. Control will come to this condition that number of times as number of 1’ bits in A. Initial value of Bis 0 and when the statement B — B+1 is executed, 1 is added to & So finaly will contain the value which represents the number of 1” bits in A. (c) ADD A[R,].@ 8 A[Ro] :Ituses 2 memory cycles, one to get the value in A, and 2% to get contents of Af]. @B : Itvalue uses 2 memory cycles for indirect addressing mode. Finally, after addition the result is stored back in A(Py]and itwilltake 1 memory cycle as the values are already known (instruction is fetched and decoded). wunwmadeeasy.inGAMBDE EASS GES 2075) Computer Organization 29. (369) 34. (c) 4 byte instruction storage 512 | 513) —— = Fete sta { 515] J (Ua nstruton register 516] Po=st6 Effective address = PC + Relative value Relative value = EA~PC = 885 -516 = (369), 30. (d) —_ 2———— [owe [om [om 2" two address instruction Here 400 two addresses are needed. So (2"*~ 400) op-codes are free. We can store (2 — 400) x 2? one address instructions. 35. (d) 31. (b) vmnctun Jom f_tnasions [tae (e8e 100] oo} ese | 17 — i (Geom [etoen Paes Teed | 15| 20 | 00 | aso fiz00 a sess | ho aeasub | 10} 20 | 40 |200 |400 muon | 18) 20 | 20 | 00 |ao0| N= 28=16 | jumernch | 5 | as | 40 | 75 |200) # Free opcodes = 16-2 14 over Ls} 1s | 2 | 75 |100 41 Address Instruction = 14 x 64 Free opcodes = 896 ~ 60 = 836 Oyclo time = 1 =1nsec # Zero Address Instruction = 836 x 64 = 53, 504 iGHz Total # cycies of CSE = 1100 32. (b) = Time taken to execute CSE | CPU clock cycles = ECPI xe = 1100" 1 nsec = 1.1 psec This yields Total ¥ cycles of IT = 2200 CPU clock cycles, = 2x 1+ 1x2+2x3=10 = Time taken to execute CSE CPU clock cycles, = 4x 141x241 x38. = 2200" 1 nsec = 22sec So sequence 2s fasterit takes less clock cycles. (92) 93. (c) 1, Goycles, PC-relatve -» PC + 500 = 202 + 500 = 702 f, Gcycles : Base-reigister~» 100 + 500 = 600 Label /, 6 oycles 1, deycles I,4cyeles Stimes J 2eycles winwmadeeasy.in GgMAbE EASY Objective Practice Setsa7. 38. 39. GF | Computer Science & IT Example: Time = 12 cycles + 80 cycles: 40. Cycletime = 1 wre °° Program execution tim = 92sec, (-128) 8 Gms | toot |B? 28 49iinstructions => 6 bts nesded for Op-code 32 registers = 5 bits needed for register operands Immediate operand bits = 8 Minimum value = -2? = -128 Since bitis gone for sign representation. (2032) 2000-2007: 1 2008-2011: f 2012-2018: f 2016-2019: J 2020-2027: I 2028-2031: /, 20a2-2083: 1, Return address pushed on to the stack is 2032 ©) 8byte instruction storage: zoe[ aor; | zoel A zoel A 7] instruction aoa] PF Reger 02th 202 | 2023 hy 2008 Etfective address = PC + Relative value = 2024+ (-11) = 2013 Objective Practice Sets Postal Study Course FTE) 41. 42. [mabe ensy GaMAdE EAsy (b) Average of time ((0.2 x0) +(0.2x0)+(0.4x 16) + (0.2 x 12}} (6.44 2.4) = 8.8 cycles So, average of time = 8.8 nsec J operand 8.8nsec Number of number of operands in 1 sec Jloperand imber of operands = 19perand Number of operands = CERES 0.113636 x 10° operand /sec Operand fetch rate = 113.636 million wordsisec (a) ‘otal number of opcode possible with 5 bit = 32 16 opcode for double operand remaining 32-26 =6 Remaining = 2° x6 = 384 Out of 384, 184 single operand instruction, so remaining are 384 - 184 = 200 ‘Total number of free instruction (zero operand) 200 x 2° = 2° 200 = 12800 (2048) Instruction format — 196 ——____+ Opeode | Address 2 | Address 1 3Br oor Since number of words = 256 ‘So number of bits used for addres: = 8 bits Number of opcodes = 2°=8 Number of free opcode = 8~. Number of 1-address instructions x 29 = 266 x3 = 768 Number of free opcode ater allotting 1-address Instruction = [768 - 760] Number of 0-address instructions logp(256) 3 wwmmadeeasy.inCorr yi The bus system of a machine has the following propagation delay times: 40 ns for the signals to propagate through the multiplexers, 90 ns to perform the ADD operation in the ALU, 30 ns delay in the destination decoder, and 20 ns to store the data into the destination register. What Is the minimum cycle time that can be used for the clock? (2) 120n8 (b) 150ns (@) 160ns (a) 180ns The given circuit represents states conto] 129 |_| ets ee | ot @ nstates (©) (0-1) states (© 2rstates (0) 2 states Ifthe last operation performed on a computer with an 8-bit word was an addition in which the two operands were 00000010 and 00000011, what would be the value of the Overflow ,Sign and Hall-Carry flags respectively? @ 0,0,0 ©) 0,1,0 © 1.0.1 @ 0,1,1 Which set of instruction transfers the memory word specified by the effective address to AC cor Load to AC? (@) DRE MARL ACE AC + DR, ER Cyy, SCHO (b) DRE MAR) AC & OR, SCO (©) MAR) — AC, sCe0 (@) OR< MAR] AC AC’ DR, SCO CPU Design \What is the control units function in the CPU? {@) todecode program instructions (©) totranster data to primary storage (©) to perform logical operations (@) tostore program instructions Which of following registers processor used for felch and execute operations? 1. Program counter 2. Instruction register 3. Address register (@) tand3 (b) tand2 (©) 2and3 (@ 1,2and3 The processor used program counter and nstruction register for fetch and execute operations. Microinstuction lengths determined by _. The maximum number of simultaneous miro operations that must be specified. 2, The way in which the control information is represented or encoded, 3, The way in which the next microinstruction address is specified. (@) tand2 (0) 2and3. (©) 1and3 (@) allot these Following are some statements associated with microprocessors. Identify the false statement. (a) The control unit is the component of the CPU that implements the microprocessors instruction set (&) The instruction received by the CPU is decoded by the arithmetic logic unit. (©) ACPUregisteris used toholda binary value temporarily for storage, for manipulation, and/or for simple calculations. (6) The control units are programmed and not hardwired.| Computer Science & IT The register which holds the address of the location oor from which data are tobe transferred is known as (@) index register (©) instruction register (©) memory address register {d) memory data register 10. Consider a CPU has 8 general-purpose registers Foy Ryo Ry and supports the following operations. ADD A, Ry A, Add A, to A, and store the result to R, MUL R.A, Re Multiply R, to R, and store the result to R,, ‘An operation normally takes one clock cycles, ‘an operation takes two clock cycles ifit produces @ result required by the immediately following operations, Consider the expression XY + XYZ+ YZ, where variables X, ¥ and Z are initially located in the registers A, R, and R,. I'contents these registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of XY + XYZ + YZ? 4 ) 5 6 7 11. Consider an accumulator-based CPU supports only single address instruction. The CPU supports the following instructions. LOAD A Load A from memory into accumulator AC. STORE A Store contents of accumulator ‘AC in memory location M, ADD B_—_Load B into data register (DR) and add to accumulator. MOVE A, B Move content of Bto A SUB ‘Assume CPU uses the memory referencing and each instruction LOAD, STORE and ADD takes one clock cycle, To compute Z = X + Y CPU takes how many minimum number of clock A, B Subtract B from A. cycles? @ 2 ©) 3 4 (5 (EFI objective Practice sets 12, 13. 14, (3 mace ensy Gamaoe easy ors] GAMADE SASS The following are the some of the sequences of operations in instruction cycle, which one is correct sequence? @ PC + Address register Data from memory > Data register Data register > IR. PO+1PC © ‘Address register > PC Data register > Data from memory Dataregister > IR PC+19PC © Data trom memory -» Data register PC ~ Address register Data register + IR PC +1 PC (d) None of these Horizontal microinstruction have which of the following attributes? 1. short format 2, limited ability to express parallel micro operations 3. considerable encoding of the contro! information (@) tand2 (b) 2and3 (©) 1,2and3 —(@) Noneofthese Consider the following figure Contat }— inputs PA LT Register = contrat signals The above circuit represents 1. Hardewired control unit 2. Micro programmed control unit (@) Only (b) Only 2 (©) Both 1 and2 (a) Either 1 or2 wwwmadeeasy.inMADE EASS 15, 16. 17. 18, The sequence of events that happen during a typical fetch operation is {@) PC Mar —> Memory MOR -» IR (0) PC > Memory -» MOR > IR (6) PO Memary IR (6) PC > Mar > Memory IR Determine the width of Micro-instruction having following Control signal field, in @ Vertical Micro- programmed Control Unit 1. Next Address field of 7 Bits 2. ALUFunction field selecting 1 outot 13 ALU Function 3. Register-in field selecting 1 out of 13 ALU Function 4, Register-out field selecting 1 out of & Registers 5. Shifter field selecting no shift, right shitt or loft shirt 6. Auxillary control field of 4 bits (@) 2 © 2 (© 24 Os Hardwired control units are faster than Micro- programmed control unit because (@) They do not consist of slower memory elements (b) They do not have slower element such as Gates and Flip-flops (©) They are made using faster VLSI design technology (d) They contain high speed digital components The rmicroinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a rmicro-operation field of 13 bts, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. LS = oad = Address Resistor ‘nerement oneal) Memor at re status Beso Nico-operatons teed 2078] 19, 20. 21. (]mMAde Ensy How many bits are there in the X and Y fields, ‘and what is the size of the control memory in number of words? (@) 10,3, 1024 (©) 5,8, 2048 (0) 8,5, 256 (@) 10,3512 ‘An instruction set of a processor has 125 signals which can be divided into § groups of mutually ‘exclusive signals as follows: Group 1 20 signals, Group 2: 70 signals, Group 3:2 signals, Groups 4 : 10 signals, Group 5:23, signals. How many bits ofthe control words can be saved by using vertical microprogramming over horizontal microprogramrming? (a) 0 (©) 103 2 (9) 55 Ahardwired CPU uses 10 control signals St to ‘S10 in various time steps T1 10 TS implement 4 instructions /1 to /4 as shown below. 7] Bp 7 [SSS SS) SSL] HT | SO |5aSB TTS 58 95 | 58 59,510 [5,56 SF] 98 _| S10 73 | Si $3 $5 | SF, 8,510 [52,56 99] S10 | S183 [ra [St83 55, $256.97} $2510 [55581 S10 Which of the following pairs of expressions represen the crcutfor generating conto signals $5 and S10 respectively [Ij + 1k] Th indicates that the control signal should be generated in time step Thif the instruction being executed is Toor 1k? (@) S5= T+ 72. TandS10= (M1 +18). Ts+ (2414). 15 (b) S52 71+ (2414). and S10 = (1 +13) Tas (12+ 14). 5 (©) SS=T1+(12+14), Band $10=(12+ 13+ 14). T2+ (M1 +). TA (12 + 14). TB (0) S8=T1+(124/4). TRand $10 =(12 + 13) T2414. T34 (+18). TA + (22 + 14), 5 In a registerimemory type CPU, the instruction lengths are typically variable. This presents a problem when the program counter (PC) of the CPU is incremented during the fetch-execute cycle. Which statements is/are true with regard toPC incrementing? - Objective Practice Sets22. 23, CG oviecivePracice ets | Computer Science & IT (@) PCis incremented by the largest possible fixed value, itrespective of the variability. (©) Increment value is known when the current instruction is decoded within the IR, () Increment value is known when the current instruction has completed execution. (@) The binary loader overcomes the problem by positioning instructions at word boundaries so that PC can be incremented bya constant amount Which statements false in case of microprogram control? (@) In a microprogram control, the control variables that initiate microperations are stored in memory. The control memory is usually a ROM, since the control sequence ispermanentand needs no alternation (0) The control variables stored in memory are read one at a time to initiate the sequence of rmicroperations for the system (©) The words stored in a control memory are micro instructions, and each micro instruction specifies one or more microperations for the ‘components in the systern (@) Once these microoperations are executed, the control unit must determine its next address. Therefore, all bits of the micro instruction are used to control the generation of the address for the next micro instruction Consider the following data path of a CPU a & ooee ks Postal Study Course PDAE] 24, 25. G3MADE EAS (a mabe easy The, ALU, the bus and all the registers in the Gata path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycle are needed for memory read operation - the first one for loading address in the MAR and the next ‘one for loading data from the memory but into the MDR, The instruction “add AD, AI" has the register transfer interpretation FO < = AO + At. The minimum number of clock cycles needed for execution cycle of this instruction is @e2 () 3 @4 (5 ln an enhancement of a design of a CPU, the ‘speed of a floating point unit has been increased ‘by 30% and the speed of a fixed point unit has been increased by 20%, The overall speedup achieved ifthe ratio of the number of fixed point operation to floating point operations is 4 :6 and the floating point operation usad to take twice the time taken by fixed point operation in the original design (upto 2 decimal places) is, ‘Assume that the control memory is 30 bits wide. ‘The microinstruction formats divided into 3 fields. ‘A micro operation field of 15 bits specifies the ‘micro-operations to be performed. An address selection field specifies a condition based on flags and contro! memory address field. There are 8 flags. How many bits are there in address selection field, address field and what is the size of control memory in words respectively? (@) 212.2048 (b) 2, 10,2048 (©) 3,12,4096 (a) 3,10, 1024G3 MADE EASY EREIIEN cPu Design 1 6 2 © 3 @ 4 0 5 @ 10. © 1. 6) 12 @ 13 @ 14 © 19. (b) 20. (@) 21. (©) 22, (@ 23. Wo) EEE c?u Design 1. (b) 13. (40 + 90 + 20) = 150 ns Selection of destination register that takes 30 ns ‘can be done parallelly wth other operations. 3. (a) 00000010 oooo0011 2 doooo1on Overtlow = 0, sign = 0, Half carry = Half carry indicate addition of packed decimal numbers, When carry tekes place out of the lower digit order, this flag is set ue ‘Auxliary carry is also known as haif carry 6. (b) The processor used program counter and instruction register for fetch and execute operations. 10. (c) Initially Ry X, Ry ¥, Rye Z The sequence of operations to compute XY + XYZ + YZis as follows 17. Operation Meaning # clock cycles. MUL Ay, Ry yp = XY 1 MUL Fy, Ry, Re Ay © YZ 1 MUL R,, Fy Ry Re XYZ 1 ADD Fy, Fy Rg Ry XV+XYZ 1 19. ADD Fi, Ay, Ry By XV + XYZ + YZ 2 Total 6 clock cycles 11. (®) Instructions No. of clock cycles AC: = MX) LOADA AG:=AC+MY) ADDY 1 M2) STOREZ 1 Total wwvimadeeesy.in femace Easy Postal Study Course EXD] ‘Computer Organization 6 &) 7% @ & &) % © 15. (@) 16. (©) 17. @ 18 (@) 28. (0) (d) Horizontal microinstructions have following attributes 1, Long formats 2, Ability to express ahigh degree of parallelism 3, Little encoding of the control information (c) Since PLA Is neither a hard-wired model nor a memory. ‘=. We can say control unit with PLA as Hard- Wired or micro programmed control unit, ) Noxt Address Field = 7 Bits ALU Function Fields of 4 Bits (to select possible 1 of 13 ALU fns) Register.in and Registe-outFields of its each Shiter Field of 2 bits to select 1 out of three possibilties Auxiliary Field of 4 Bits Total Bits in instruction 144034 94244223 (a) Hardwired CU use digital logies while Micro- programmed CU uses Control Store Gate propagation delays are much less as compared to Memory access times of control stores. (b) G1: 20signals G2: 70signals GB:2signals G4: 10signals G5: 23 signals Using horizontal microprogramming, 125 bits of control words are used. But using vertical ‘microprograrnming, the number of bits according to groups are: Gt: 20 signals = 5 bits PERERA| Computer Science & IT Ge: G3 Ga Gs 70 signals = 7 bits 2 signals = 1 bits 10 signals = 4 bits 23 signals = 5 bits Total = 22 bits Total 22 bits are needed for vertical micro- programming, So, total bls saved = 125-22 = 103, (b) Add Ry. Ryo Ry+R, | ' 1 1 1 clock cycles Total 3 clock cycles are needed to execute the instruction, (1.27) Let total operation be 100 and total time taken is t= 100 sec. 23, 24, Floating point operations are Fixed point operations are = 4x 100 = 40 Let time taken by floating point is t, and time taken by fixed point ist, So t,+t= 100 Time taken by 60 floating point operation 4 0 Similarly 1 fixed point operation takes = g 1 floating operation = (2) (ER objective Practice sets 3 Postal Study Course EXE] [a mMAoE ERsy From equation 1 and 2 Atter speed-up tre fe - 800_ _ 6000 is/are 104) 400. _ 2000 {2x8 96 6000 , 2000 104 * 96 = a _ xs, 76942083 100 s, x$, = 1.27, =” 7a50*5 25. [aacress ] OM size = 2°? OW = 4096 CW inDE EASY wwwmadeeasy.inrrr) Pipelining improves CPU performance due to (@) reduced memory access time (©) increased clock speed (6) the introduction of paralielism (@) additional functional units An instruction cycle refers to (@) fetching an instruction (0) clock speed (© fetching, decoding and executing an instruction (6) executing an instruction AS stage pipeline with the stages taking 1, 1.3, 4,1, units of time has a throughput of @ 13 17 7 3 Given a stage pipeline with stages taking 1, 2, 3, 1, 1 units of time, the clock period of the pipeline is f@ 8 (0) 1/8 ©) 19 @ 3 Which of the following statements is false with regard to instruction pipelining? (@) The basic goal of instruction pipelining is to achieve a OPI of 1 (©) Instruction set architectures having simple registry/register addressing modes can be easily pipelined than those having complex addressing modes, (©) By the use of hardware special features and compiler design techniques, pipeline hazards can be removed. (@ The basic goal of instruction pipelining is to achieve a CPI of more than 1 The performance of a pipelined processor suffers if eee Le Instruction Pipelining (@) the pipeline stages have different delays (©) consecutive instructions are dependent on each other (©) thepipeline stages share hardware resources: (d) allof the above Consider an unpipelined processor assume that it has a 1 ns clock cycles and that it uses 4 cycles for ALU operation and branches and § cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose due to clock. skew and setup, pipelining the processor adds .2nsofoverhead tothe clock. Ignore any latency impact. What speedup gain alter pipelined the processor? (@) 3.4ns (b) 38ns © 370s (@) 1.2ns Consider a case where (k) 4-segment pipeline with a clock cycle time (tp) 20 ns in each sub ‘operation to execute (n) 100 tasks. Assume that ‘a non pipeline unit that can perform the same operation, Pipelined system will take how much time to completa the task? (@) 2060ns (b) 20008 (©) 20ns (2) 1901 ns Pipelined operation is interupted whenever two operations being attempted in parallel need same hardware component. Such a conflict can occur if (a) The execution phase of an instruction requires access to the main memory, which also contains the nextinstruction that should be felched at the same time (©) The prefetch phase of an instruction requires access to the main memory, which also contains the next instruction that should be fetched at the same time10. ib 12, CF ctiecive race sets | Computer Science & IT (©) The decode phase of an instruction requires access to the main memory, which also contains the next instruction that should be fetched at the same time (@) None of these Consider the unpipelined machine with 10 ns clock cycles. It uses four cycles for ALU ‘operations and branches, whereas five cycles for memory operations. Assume that he relative frequencies of there operations are 40%, 20%, 40% respectively. Suppose that due to clock skew and setup, pipelining the machine adds ‘ns overhead to the clock, How much speed tp in the instruction execution rate will we gain from a pipeline? @) Stimes (©) times (b) 8times (d) 45 times Using a sequential implementation, it takes a total of 320 ns for each instruction, 300 ns for the combinational logic to complete, and 20s to store the result (in a register). This means that a throughput will be about 3.12 millions instructions/second. Assuming you switch toa 3 stage pipeline by splitting the combinational logic into three equal parts and all registers take 20 ns to store result. 300 ne 208 Combinational R tage FEB a Cock How long will it take for a single instruction to execute in the pipelined implementation? (@) 900ns (b) 360ns (©) 100ns (@) 380ns AS stage pipeline Is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched til the current instruction is completed. What is throughput of the system if 20% of instructions are branch instructions? Ignore the overhead of buifer register. Each stage is having same amount delay. The pipeline clock is 10 ns. Branch penalty is of 4 cycles, 13, 14. 15. 16. MADE EASY PSE] G3 mabe ensy (@) 55 Mips (0) 65Mips (0) 45 Mips (d) None of these ‘Assume that the time required for the eight functional units, which operate in each of the eight cycles, are as follows 5ns, 8ns, 6ns, 101s, 18ns, 12ns, 6ns, 8 ns, ‘Assume that pipe lining adds 1 ns of overhead, Find the speedup versus the single cycle data path. (@ 467 © 444 (b) 4375 (@) 4.285 Consider the unpipelined machine with 12 ns clock cycles. It uses four cycles for ALU operations and branches, whereas five cycles for memory operations. Assume that the relative trequencies of there operations are 30%, 20%, 20% respectively. Suppose that due to clock ‘skew and setup, pipelining the machine adds 1 ns overhead to the clock. How much speed Up in the instruction execution rate will we gain from a pipeline? (@) 2.0 times (©) 28 times (b) 3.1 times. (@) 35 times nz bitmachine to execute an instruction the following steps are carried out: Fetch, Decode, Execute and Store, each of which takes one clock period. In a pipelined execution of a four-step task a new instruction is read and its nanosecond and there are 100 instructions in sequence then whatis the speedup ratio of pipeline processing system over an equivalent non-pipeline Processing system? (a) 3.88, (0) 368 (b) 1.88 (9) 2723 ‘A4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used betwoen the stages have a delay of 5 nanoseconds each. Assuming constant clecking rate, the total time taken to process 1000 data items on this pipeline willbe (@) 120.4 microseconds (©) 160.5 microseconds (©) 165.5 microseconds (6) 590.0 microseconds worwmadeeasy.in20. (2 MADE ERSY 17, Consider a pipeline processor with 4 stages $1 to Sd. We want to execute the following loop’ for = 1:4 < = 1000; i++) U1, 12,18, 14} ‘Where the time taken (inns) by instructions I1 to \4 for stages $1 to S4 are given below. St $2 $3 S4 rice 2 ee 0) BR: 2 1 2 4 Bt 1 2 4 eee The output of /1 for i= 2will be available after (@ t1ns (b) 1208 (©) 1308 (d) 28ns The IF, ID and WB stages take 1 clock cycle 18, each. The EX stage takes 1 clock cycle each for the ADD, SUB and STORE operations, and 3 clock cycles each for MUL and DIV operations, Operand forwarding from the EX stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is (@) 10 ©“ (b) 12 (@) 16 19. We have two designs D1 and D2 for a synchronous pipeline processor. Dt has § pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design 02 has 8 pipeline stages each with 2 nsec execution time. How much time can be saved using design D2 over design D1 for executing 100 instructions? (a) 214nsec (0) 202nsec (©) 86nsec (6) 200nsec Suppose that an unpipelined processor has @ cycle time of 25ns, and that its datapath is made up of modules with latencies of 2, 3, 4, 7, 3, 2 and 4 ns (in that order). In pipelining this processor itis not possible to rearrange the order Of the modules (Tor examples, putting the register read stage before the instruction dacode stage) or to divide @ module into muttiple pipeline stages (for complexity reasons). Given pipeline latches with 1 ns latency: wummadeeasy.in Postal Study Course BEA) 24 22. 23. Q24 [mace Easy” Computer Organization Ifthe processor's divided into the rewest number of stages that allow to achieve the minimum latency from part 1, what is the latency of the pipeline? (@) nolatency (©) 40nslatency (©) 36ns latency (@) Séns latency We have two designs P, and P, for a synchronous pipeline processor. P, has & pipeline stages with execution time of Snsec, 2 nsec, 4 nsec, 8 nsec, 2 nsec, 5 nsec, 4 nsec and 1 nsec while design P, has 5 stages each ‘with 5 nsec execution time. How much time (in sec) can be saved using design P, over design P, for executing 500 instructions? (upto 3 git), (@) 2596 (b) 1.365 (©) 1.536, (a) 1.653, A.branch mark programs running on a 40 MHz processor. The executed program consists of 100,000 instruction executions, withthe folowing instruction mix and clock cycle count. insiruelion [instruction] Cycle per ‘yee | Count” | instruction intoger arithmetic | 45000 1 Data wansfer | 32000 2 Froatng point | 15000 2 Control waneer | 8000 2 The execution time in msec is, Consider the following instructions ys, = 100 I: Ry = Rh+ Ry Iy: Fy = Ry +25 Ty: R= R, + Py Ig: Ry =F, +30 Calculate sum of (WAR, RAW and WAW) dependencies the above instructions @ 10 () 12 @7 oe Consider a pipelined system with four stages: IF ID, EX, WB. Following chart shows the clack cycles required by each instruction to complete each stage. Objective Praca Sis