System Verilog

COVERAGE

ROHIT KHANNA
 Coverage

 Coverage is the metric of completeness of verification.

 Why we need coverage?

o Direct Testing is not possible for complex designs.
o Solution is constrained random verification but :
o How do we make sure what is getting verified?
o Are all importance design states getting verified?

 Types of Coverage's:
o Code Coverage.
o Functional Coverage.

System Verilog Coverage

 Code Coverage

 Code Coverage is a measure used to describe how much part

of code has been covered (executed).

 Categories of Code Coverage

o Statement coverage
o Checks whether each statement in source is executed.

o Branch coverage
o Checks whether each branch of control statement (if,
case) has been covered.
o Example: choices in case statements.

System Verilog Coverage

 Code Coverage

o Condition coverage
o Has Boolean expression in each condition evaluated to both
true and false.
o Toggle coverage
o Checks that each bit of every signal has toggled from 0 to 1
and 1 to 0.
o Transition coverage
o Checks that all possible transitions in FSM has been covered.

o State coverage
o Checks that all states of FSM has been covered.
System Verilog Coverage
 Functional Coverage

 Functional Coverage is used to verify that DUT meets all the

described functionality.

 Functional Coverage is derived from design specifications.

o DUT Inputs : Are all interested combinations of inputs
injected.

o DUT Outputs : Are all desired responses observed from

every output port.

o DUT internals : Are all interested design events verified.

e.g. FIFO full/empty, bus arbitration.

System Verilog Coverage

 Examples

 Have I exercised all the protocol request types and

combinations?
o Burst reads, writes etc.

 Have we accessed different memory alignments?

o Byte aligned, word aligned, dword aligned, etc.

 Did we verify sequence of transactions?

o Reads followed by writes.

 Did we verify queue full and empty conditions?

o input and output queues getting full and new requests
getting back pressured.
System Verilog Coverage
 Code vs. Functional Coverage

Needs more Functional

Functional Coverage

High

Coverage points, Check for Good Coverage

unused code
Low

Start of Project Code may be incomplete

Low High

Code Coverage
System Verilog Coverage
 Coverage Driven Verification

From Create initial cover metrics

Verification
Plan Generate Random Tests

Run Tests, Collect Coverage

Coverage Met ?
YES
NO
Verification
Identify Coverage Holes
Complete
Add tests to target holes,
Enhance stimulus generator,
Enhance cover metrics if required
System Verilog Coverage
 SV Functional Coverage Support

 The System Verilog functional coverage constructs provides:

o Coverage of variables and expressions, as well as cross
coverage between them.

o Automatic as well as user-defined coverage bins.

o Associate bins with sets of values, transitions, or cross products.

o Events and sequences to automatically trigger coverage

sampling.

o Procedural activation and query of coverage.

o Optional directives to control and regulate coverage.

System Verilog Coverage
 covergroup

 covergroup construct encapsulates the specification of a

coverage model.

 Covergroup is a user defined type that allows you to

collectively sample all variables/transitions/cross that are
sampled at the same clock (or sampling) edge.

 It can be defined inside a package, module, interface,

program block and class.

 Once defined, a covergroup instance can be created using

new() - just like a class.

System Verilog Coverage

 Example

Syntax:
covergroup cg_name [(port_list)] [coverage_event];
//coverage_specs;
//coverage_options;
endgroup [ : cg_name]

Example:
covergroup cg;
……
endgroup

cg cg1=new;
System Verilog Coverage
 Coverpoint

 A coverage point (coverpoint) is a variable or an expression

that functionally covers design parameters.

 Each coverage point includes a set of bins associated with

its sampled values or its value-transitions.

 The bins can be automatically generated or manually

specified.

 A covergroup can contain one or more coverpoints.

System Verilog Coverage

 Example

Syntax:
[label : ] coverpoint expression [iff (expression)]
[{
//bins specifications;
}] ;

Example:
covergroup cg;
coverpoint a iff(!reset);
endgroup

System Verilog Coverage

 bins

 A used to collect coverage bin is a construct information.

 It allows to organize coverpoint sample values in different

ways.
o Single value bins.
o Values in a range, multiple ranges.
o Illegal values, etc.

 If bin construct is not used inside coverpoint then automatic bins

are created based on the variable type and size.

 For a n-bit variable, 2 ^ n automatic bins are created.

System Verilog Coverage

 Example1

bit [3:0] temp;

covergroup cg;
coverpoint temp; //16 - Automatic bins created
endgroup

cg cg1;
initial cg1=new;

bin[0] to bin[15] are created where each bin stores information

of how many times that number has occurred.

System Verilog Coverage

 Example2

bit [3:0] temp;

covergroup cg;
coverpoint temp
{
bins a= { [0 : 15] }; //creates single bin for values 0-15
bins b [ ]= { [0 : 15] }; //creates separate bin for each
//value 0-15
}
endgroup

System Verilog Coverage

 Example3

bit [3:0] temp;

covergroup cg;
coverpoint temp
{
bins a [ ]= { 0, 1, 2 }; //creates three bins 0, 1, 2
bins b [ ]= { 0, 1, 2, [1:5] }; //creates eight bins 0, 1, 2,
//1, 2, 3, 4, 5
}
endgroup

System Verilog Coverage

 Example4

bit [3:0] temp;

covergroup cg;
coverpoint temp
{
bins a [4]= { [1:10], 1, 5, 7 };
//creates four bins with distribution <1, 2, 3> <4, 5, 6>
<7, 8, 9> <10, 1, 5, 7>
}
endgroup

System Verilog Coverage

 Example5

bit [9:0] temp;

covergroup cg;
coverpoint temp
{
bins a = { [0:63], 65 }; // single bin
bin b [ ]={ [127:150], [148:191] }; // overlapping multiple bin
bin c [ ]={ 200, 201, 202 }; // three bins
bin d [ ]={ [1000:$] }; // multiple bins from 1000
// to $(last value:1023)
bin others [ ] = default; // bins for all other value
}
endgroup
System Verilog Coverage
 Covergroup Arguments

 Parameterized Covergroups can be written using arguments.

 Useful if similar covergroups are needed with different

parameters or covering different signals.

 Example: covergroup for all basic FIFO conditions.

 Actual values can be passed to formal arguments while

covergroup is instantiated.

 ref key word is required if a variable is passed as an argument.

System Verilog Coverage

 Example

bit [16:0] rdAddr, wrAddr;

covergroup addr_cov (int low, int high, ref bit [16:0] address)
@ (posedge clk);
addr_range : coverpoint address {
bins addrbin= { [low: high] };
}
endgroup

addr_cov rdcov=new ( 0, 31, rdAddr );

addr_cov wrcov=new ( 64, 127, wrAddr );
System Verilog Coverage
 Covergroup inside a class

 By embedding covergroup inside class, coverage can be

collected on class members.

 Very useful as it is a nice way to mix constrained random

stimulus generation along with coverage.

 A class can have multiple covergroups.

 For embedded covergroups, instance must be created be

inside the new() of class.

System Verilog Coverage

 Example

class xyz;
bit [3:0] m_x;
int m_y;
bit m_z;
covergroup cov1 @ (m_z); //Embedded Covergroup
coverpoint m_x; //16 bins
coverpoint m_y; //2^32 bins
endgroup
function new(); cov1=new; endfunction
endclass

System Verilog Coverage

 Example

class c1;
bit [7:0] x;
covergroup cv (int arg) @ (posedge clk);
option.at_least=arg;
coverpoint x;
endgroup
function new(int p1); cv=new(p1); endfunction
endclass

initial c1 obj=new(4);

System Verilog Coverage

 Bins for Transition

 In many cases, we are not only interested in knowing if

certain values or value ranges happen.

 But, we are also interested in knowing if transition between,

two values or two value ranges happen.

 Transition coverage is often more interesting in control

scenarios, whereas value coverage is more interesting in data
path scenarios.

System Verilog Coverage

 Specifying Transition

 Single Value Transition

(value1=> value2)

 Sequence of Transitions
(value1=> value2 => value3=> value4)

 Set of Transitions
(value1, value2 => value3, value4)

 Consecutive repetition of Transitions

value[*repeat_time]

System Verilog Coverage

 Example1

bit [4:1] a;
covergroup cg @ (posedge clk);
coverpoint a
{ bins sa [ ]= { ( 4=>5=>6 ), ( [7:9],10=>11,12) };
bins allother= default sequence;
}
endgroup
Sa will be associated with individual bins (4=>5=>6) ,
(7=>11), (7=>12), (8=>11), (8=12), (9=>11), (9=>12),
(10=>11), (10=>12)
System Verilog Coverage
 Example2

 Consecutive Repetition
bins sb={ 4 [*3] } ;
// (4=>4=>4)
bins sc [ ]={ 3 [*2:4] };
// (3=>3) , (3=>3=>3), (3=>3=>3=>3)

 Non-Consecutive Repetition
bins sd [ ]={ 2 [->3] };
//2=>…. =>2 …. =>2

System Verilog Coverage

 Automatic Bin creation

 System Verilog creates implicit bins when coverpoint does not

explicitly specifies it.

 The size of automatic bin creation is:

o In case of enum coverage point it is same as number of
elements in enum.
o In case of integral coverage point it is minimum of 2 ^ no.
of bits and value of auto_bin_max option.
o Automatic bin creation only considers two state value.

o If auto_bin_max is less than 2 ^ no. of bits, then values are

equitably distributed among the bins.
System Verilog Coverage
 Wildcard Bins

 Wildcard bins are where X, Z or ? will be treated as don’t

care.

bit [2:0] num;

covergroup cg;
coverpoint num
{ wildcard bins even={3’b??0};
wildcard bins odd={3’b??1};
}
endgroup

System Verilog Coverage

 Wildcard Bins

bit [3:0] count1;

bit [1:0] count2;

covergroup cg;
coverpoint count1
{ wildcard bins n12_16={4’b11??};
//1100 || 1101 || 1110 || 1111
}
coverpoint count2
{ wildcard bins t =(2’b0x=>2’b1x);
//(0, 1=>2, 3)
}
endgroup
System Verilog Coverage
 Excluding bins

 In some cases all the bins may not be of interest, or design

should never have a particular bin.

 These are two ways to exclude bins

o ignore_bins
o illegal_bins

System Verilog Coverage

 Ignore Bins

 All values or transitions associated with ignored bins are

excluded from coverage.

 Ignored values or transitions are excluded even if they are

also included in another bin.

bit [3:0] num;

covergroup cg;
coverpoint num {
bins val [ ]={ [1:15] }; //7 and 8 are ignored
ignore_bins bins ignoreval={ 7, 8 }; //ignore 7 and 8
ignore_bins bins ignoretran=(3=>4=>5); //ignore transition
} endgroup
System Verilog Coverage
 Ignore Bins

bit [2:0] num;

covergroup cg;
coverpoint num {
options.auto_bin_max=4;
//<0:1> , <2:3>, <4:5>, <6:7>
ignore_bins bins hi={6, 7};
// bins 6 and 7 are ignored from coverage
}
endgroup

System Verilog Coverage

 Illegal Bins

 All values or transitions associated with illegal bins are excluded

from coverage and run-time error is issued if they occur.

 They will result in a run-time error even if they are also included
in another bin.

bit [3:0] num;

covergroup cg;
coverpoint num {
illegal_bins bins illegalval={ 2, 3 }; //illegal bins 2 and 3
illegal_bins bins illegaltran=(4=>5); //4 to 5 is illegal
//transition
} endgroup

System Verilog Coverage

 Cross Coverage

 Coverage points measures occurrences of individual values.

 Cross coverage measures occurrences of combination of values.

 Interesting because design complexity is in combination of

events and that is what we need to make sure is exercised well.

 Examples:
o Was write enable 1 when address was 4’b1101.
o Have we provide all possible combination of inputs to a Full
Adder.

System Verilog Coverage

 Example1

 Cross coverage is specified between two or more coverpoints

in a cover group.

bit [3:0] a, b;
covergroup cg @ (posedge clk);
cross_cov: cross a , b;
endgroup

 16 Bins for each a and b.

 16 X 16=256 bins for cross_cov

System Verilog Coverage

 Example2

 Cross coverage is allowed only between coverage points

defined within the same coverage group

bit [3:0] a, b, c;
covergroup cg @ (posedge clk);
cov_add: coverpoint b+c;
cross_cov: cross a , cov_add;
endgroup

 16 Bins for each a, b and c. 32 Bins for b + c

 16 X 32=512 bins for cross_cov

System Verilog Coverage

 Example3

bit [31:0] a;
bit [3:0] b;
covergroup cg @ (posedge clk);
cova: coverpoint a {bins low [ ]={ [0:9] }; }
cross_cov: cross b, cova;
endgroup

 16 Bins for b. 10 Bins for cova.

 10 X 16=160 bins for cross_cov

System Verilog Coverage

 Cross Coverage

 Cross Manipulating or creating user-defined bins for cross

coverage can be achieved using bins select-expressions.

 There are two types of bins select expression

o binsof
o intersect

System Verilog Coverage

 Binsof and intersect

 The binsof construct yields the bins of expression passed as an

arguments. Example: binsof (X)

 The resulting bins can be further selected by including or

excluding only the bins whose associated values intersect a
desired set of values.

 Examples:
o binsof(X) intersect { Y } , denotes the bins of coverage point
X whose values intersect the range given
o ! binsof(X) intersect { Y }, denotes the bins of coverage point
X whose values do not intersect the range given by Y.

System Verilog Coverage

 Binsof and intersect

 The bins selected can be combined with other selected bins using
the logical operators && and ||.

bit [7:0] a, b;
covergroup cg @ (posedge clk);
cova : coverpoint a
{
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
System Verilog Coverage
 Binsof and intersect

covb : coverpoint b
{
bins b1 = { 0 };
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}

System Verilog Coverage

 Binsof and intersect

covc : cross cova, covb

{
bins c1= ! binsof(crossa) intersect { [100:200] };
//a1*b1, a1*b2, a1*b3, a1*b4
bins c2= binsof(crossa.a2) || binsof(crossb.b2);
//a2*b1, a2*b2, a2*b3, a2*b4
//a1*b2, a2*b2, a3*b2, a4*b2
bins c3= binsof(crossa.a1) && binsof(crossb.b4);
//a1*b4
}
endgroup

System Verilog Coverage

 Excluding Cross products

 A group of bins can be excluded from coverage by specifying a

select expression using ignore_bins.

covergroup cg;
cross a, b;
{
ignore_bins bins ig=binsof(a) intersect { 5, [1:3] };
}
endgroup
 All cross products that satisfy the select expression are excluded
from coverage even if they are included in other cross-coverage
bins of the cross.
System Verilog Coverage
 Illegal Cross products

 A group of bins can be marked illegal by specifying a select

expression using illegal_bins.

covergroup cg(int bad);

cross a, b;
{
ignore_bins invalid=binsof(a) intersect { bad };
}
endgroup

System Verilog Coverage

 Coverage Options

 Options can be specified to control the behaviour of the

covergroup, coverpoint and cross.

 There are two types of options:

o Specific to an instance of a covergroup
o Specify for the covergroup

 Options placed in the cover group will apply to all cover points.

 Options can also be put inside a single cover point for finer
control.

System Verilog Coverage

 option.comment

 Comments can be added to make coverage reports easier to

read.

covergroup cg;
option.comment=“Cover group for data and address”;
coverpoint data;
coverpoint address;
endgroup

System Verilog Coverage

 per instance coverage

 If your testbench instantiates a coverage group multiple times,

by default SystemVerilog groups together all the coverage data
from all the instances.

 Sometime you would that all coverpoints should be hit on all

instances of the covergroup and not cumulatively.

covergroup cg;
option.per_instance=1;
coverpoint data;
endgroup

System Verilog Coverage

 at_least coverage

 By default a coverpoint is marked as hit (100%) if it is hit at

least one time.

 Some times you might want to change this to a bigger value.

 Example: If you have a State machine that can handle some

kind of errors. Covering an error for more number of times has
more probability that you might also test error happening in
more than one state.

option.at_least =10

System Verilog Coverage

 Coverage goal

 By default a covergroup or a coverpoint is considered fully

covered only if it hits 100% of coverpoints or bins.

 This can be changed using option.goal if we want to settle on a

less goal.

bit [2:0] data;

coverpoint cg;
coverpoint data;
option.goal=90; //settle for partial coverage
endgroup

System Verilog Coverage

 option.weight

 If set at the covergroup level, it specifies the weight of this

covergroup instance for computing the overall instance coverage.

 If set at the coverpoint (or cross) level, it specifies the weight of a

coverpoint (or cross) for computing the instance coverage of the
enclosing covergroup.

 Usage: option.weight=2 (Default value=1)

 Usage: Useful when you want to prioritize certain coverpoints

/covergroups as must hit versus less important.

System Verilog Coverage

 Example

covergroup cg;
a: coverpoint sig_a { bins a0= {0};
option.weight=0; //will not compute to
//coverage
}
b: coverpoint sig_b {bins b1= {1};
option.weight=1;
}
ab: cross a , b { option.weight=3; }
endgroup

System Verilog Coverage

 option.auto_bin_max

 Limiting auto bins for coverpoints and crosses

 Usage: auto_bin_max = <number> (Default=64)

 Usage: cross_auto_bin_max=<number> (default= unbounded)

System Verilog Coverage

 Predefined Coverage Methods

System Verilog Coverage

 Example

covergroup packet_cg;
coverpoint dest_addr;
coverpoint packet_type;
endgroup

packet_cg pkt;
initial pkt=new;

always @ (pkt_received)
pkt.sample();

System Verilog Coverage

 Example2

covergroup packet_cg;
coverpoint dest_addr;
coverpoint packet_type;
endgroup

packet_cg pkt;
initial pkt=new;

always @ (posedge clk)

if (port_disable) pkt.stop();
else (port_enable) pkt.start();

System Verilog Coverage

 Coverage system tasks and functions

 $set_coverage_db_name ( name )
Sets the filename of the coverage database into which
coverage information is saved at the end of a simulation run.

 $load_coverage_db ( name )
Load from the given filename the cumulative coverage
information for all coverage group types.

 $get_coverage ( )
Returns as a real number in the range 0 to 100 the overall
coverage of all coverage group types.

System Verilog Coverage

 Cover property

 The property that is used an assertion can be used for coverage

using cover property keyword.

property ab;
@(posedge clk) a => b;
endproperty

cp_ab: cover property(ab) $info(“coverage passed”);

System Verilog Coverage

 Effect of coverage on performance

 Be aware that enabling Functional Coverage slows down the

simulation.
 So know what really is important to cover :
o Do not use auto-bins for large variables.

o Use cross and intersect to weed out unwanted bins.

o Disable coverpoint/covergroup during reset.

o Do not blindly use clock events to sample coverpoint variables.

Instead use selective sampling() methods.
o Use start() and stop() methods to decide when to start/stop
evaluating coverage.
o Do not duplicate coverage across covergroups and properties.

System Verilog Coverage