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DLD LAB Sessional 2

This document is a lab report submitted by Aitazaz Ahmad Qureshi for the course EEE-241 Digital Logic Design. It details the completion of 4 tasks involving digital logic circuits implemented using Verilog behavioral and gate level models as well as in the Proteus simulation tool. The tasks include an 8-to-1 multiplexer, 2-to-4 decoder, 4x4 multiplier, and displaying the student's roll number 050 on 3 seven segment displays. Code and outputs are provided for verification of each task.

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50 views

DLD LAB Sessional 2

This document is a lab report submitted by Aitazaz Ahmad Qureshi for the course EEE-241 Digital Logic Design. It details the completion of 4 tasks involving digital logic circuits implemented using Verilog behavioral and gate level models as well as in the Proteus simulation tool. The tasks include an 8-to-1 multiplexer, 2-to-4 decoder, 4x4 multiplier, and displaying the student's roll number 050 on 3 seven segment displays. Code and outputs are provided for verification of each task.

Uploaded by

Aitazaz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DIGITAL LOGIC DESIGN

EEE-241
[Lab Sessional 2 Report]

Name Aitazaz Ahmad Qureshi

Registration CIIT/FA19-BCE-050/ISB
Number

Class BCE-2A

Instructor’s Name Ma’am Asma Ramay


Task 1:
Implement 8 to 1 multiplexer using behavioral model. (Even roll numbers).
Implement 1 to 8 demultiplexer using behavioral model. (Odd roll numbers).

My Roll number: 050

8 to 1 Multiplexer using Behavioral Level Code:


Test-Bench of 8 to 1 Multiplexer:

Output of 8 to 1 Multiplexer:

Task 2:
Implement 2 to 4 decoder using gate level. (Even roll numbers)
Implement 2 to 4 decoder using behavioral model. (Odd roll numbers)
Also implement on proteus using basic logic gate IC’s .

My Roll number is Even.


2 to 4 Decoder Verilog Gate Level Code:

2 to 4 Decoder Code Test-Bench:


2 to 4 Decoder Output:

2 to 4 Decoder Simulation of Proteus:

Task 3:
Implement a 4x4 multiplier using gate level.
4x4 Multiplier Code on Verilog using Gate Level:
Test-Bench of 4x4 Multiplier:

Output of 4x4 Multiplier:


Task 4:
Write a code to display your roll number on 3 seven segment displays. Consider 3 outputs
(e.g. out1, out2, out3) one for each 7 segment display. If your roll number is 153, find out the
seven segment value for each digit then send value for 1 to out1, 5 to out2 and 3 to out3.

My Roll Number = 050

Roll Number on 3 Seven Segment Display Program Code:


Test-Bench of Q#4:

Output of Q#4:

The END

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