EECS 16B Designing Information Devices and Systems II

Fall 2018 Elad Alon and Miki Lustig Homework 1

This homework is due on Wednesday September 5, 2018, at 11:59PM.
Self-grades are due on Monday, September 10, 2018, at 11:59PM.
1. Digital-Analog Converter
A digital-analog converter (DAC) is a circuit for converting a digital representation of a number (binary)
into a corresponding analog voltage. In this problem, we will consider a DAC made out of resistors only
(resistive DAC) called the R-2R ladder. Here is the circuit for a 3-bit resistive DAC.

R R
Vout

2R 2R 2R 2R

+ V0 + V1 + V2
− − −

LSB MSB

Let b0 , b1 , b2 = {0, 1} (that is, either 1 or 0), and let the voltage sources V0 = b0VDD , V1 = b1VDD , V2 = b2VDD ,
where VDD is the supply voltage.
As you may have noticed, (b2 , b1 , b0 ) represents a 3-bit binary (unsigned) number where each of bi is a
binary bit. We will now analyze how this converter functions.

(a) If b2 , b1 , b0 = 1, 0, 0, what is Vout ? Express your answer in terms of VDD .

Solution:
There are several ways to solve this problem. For this solution set, we are going to solve for the generic
solution rather than solve for each specific case of (a), (b), (c), and (d).
R R
V1 V2
Vout

2R 2R 2R 2R

+ b0VDD + b1VDD + b2VDD

− − −

EECS 16B, Fall 2018, Homework 1 1

 Applying KCL at nodes V1 , V2 , and Vout , we get
V1 V1 − b0VDD V1 −V2
+ + =0
2R 2R R
V2 − b1VDD V2 −V1 V2 −Vout
+ + =0
2R R R
Vout − b2VDD Vout −V2
+ =0
2R R
Solving this system of equations leads to
b2VDD b1VDD b0VDD
+ + = Vout
2 4 8
Plugging in 1, 0, 0 gives the answer.
VDD
Vout =
2
(b) If b2 , b1 , b0 = 0, 1, 0, what is Vout ? Express your answer in terms of VDD .
Solution:
Plugging into the equation from part (a), we get
VDD
Vout = .
4

(c) If b2 , b1 , b0 = 0, 0, 1, what is Vout ? Express your answer in terms of VDD .

Solution:
Plugging into the equation from part (a), we get
VDD
Vout = .
8

(d) If b2 , b1 , b0 = 1, 1, 1, what is Vout ? Express your answer in terms of VDD .

Solution:
Plugging into the equation from part (a), we get
7VDD
Vout = .
8

(e) Finally, solve for Vout in terms of VDD and the binary bits b2 , b1 , b0 .
Solution:
From part (a),
b2VDD b1VDD b0VDD
+ + = Vout .
2 4 8
(f) Explain how your results above show that the resistive DAC converts the 3-bit binary number (b2 , b1 , b0 )
to the output analog voltage Vout .
Solution:
Every increment of 18 VDD on VDD represents an increment of 1 to the 3-bit binary number (b2 b1 b0 ).
For example, if Vout = 85 VDD , the input was 5 in binary (1 0 1)→ (b2 = 1 b1 = 0 b0 = 1).

EECS 16B, Fall 2018, Homework 1 2

2. Logical Comparator
In this problem, we are going to implement a two-bit comparator. We take in two numbers a, b, which are
composed of bits a1 , a0 , b1 , b0 respectively. For example, a1 = 1, a0 = 0 would mean a = 102 = 210 .

(a) Let’s first implement a one-bit comparator. Give a logical expression for the > operator. To be more
specific, create a logical function such that f (a0 , b0 ) will be true if a0 > b0 and false otherwise.
Solution:
The only way f (a0 , b0 ) can be true is if a0 = 1, b0 = 0. Thus, we can say f (a0 , b0 ) = a0 · b0 .
(b) Now, let’s extend this function to implement a two-bit comparator. More specifically, make a function
g(a, b) such that g(a, b) is true if a > b and false otherwise. Recall that a, b can be decomposed to two
digits each. You may optionally use f (a0 , b0 ) to implement g(a, b).
Solution:
a > b only if a1 > b1 or a1 = b1 and a0 > b0 . This in itself is almost a complete logical function, except
we need to express equality. Fortunately, the exclusive or function does the exact opposite, so we can
simply negate it to get an equality function. Thus, g(a, b) = (a1 > b1 ) + (a1 b1 · (a0 > b0 )).
L

We can also use the truth table to find the expression:

a1 a0 b1 b0 g(a, b)
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

Now we can choose the rows which make g(a, b) true, and string them together with OR’s, hence

g(a, b) = a1 · a0 · b1 · b0 + a1 · a0 · b1 · b0 + a1 · a0 · b1 · b0 + a1 · a0 · b1 · b0 + a1 · a0 · b1 · b0 + a1 · a0 · b1 · b0

3. Transistors and Boolean Logic

A boolean formula can be implemented in digital circuitry using nMOS and pMOS transistors. In circuits,
the truth value 1 (true) is represented by a high voltage, called POWER (VDD ). The truth value 0 (false) is
represented by a low voltage, called GROUND (GND). In this problem, we will only use the truth values in
order to simplify notations. That is, if you see A = 1 for a point A, then it means the voltage of A is equal to
VDD . Similarly, if A = 0, then the voltage of A is equal to GND.

EECS 16B, Fall 2018, Homework 1 3

An inverter can be implemented with 1 nMOS and 1 pMOS, as shown in the figure below. When the input A
is 0, then the nMOS is OFF and the pMOS is ON. Thus, the output Y is pulled up to 1 because it is connected
to VDD . Conversely, when A is 1, then the nMOS is ON and the pMOS is OFF, and Y is pulled down to 0.
Therefore, the circuit implements the Boolean formula, Y = A.

VDD
pMOS pull-up network

A Y

nMOS pull-down network

In general, a Boolean-formula circuit has an nMOS pull-down network to connect the output to 0 (GND)
and a pMOS pull-up network to connect the output to 1 (VDD ). The pull-up and pull-down networks in the
inverter example each consist of a single transistor.
In this problem, you will design pull-up networks given the pull-down networks.

(a) The pull-down network of the Boolean formula (a 2-input NAND gate), Y = (A · B), is given below.
Design the pull-up network (the dashed box) with 2 pMOS transistors.

Solution:
From De Morgan’s laws, we have Y = A + B, which means that when A = 0 or B = 0, Y should be
pulled up to 1. Therefore, we connect two pMOS transistors in parallel in the pull-up network.

EECS 16B, Fall 2018, Homework 1 4

 A B

(b) The pull-down network of the Boolean formula (a 2-input NOR gate), Y = (A + B), is given below.
Design the pull-up network (the dashed box) with 2 pMOS transistors.

A B

Solution:
From De Morgan’s laws, we have Y = A · B, which means that when A = 0 and B = 0, Y should be
pulled up to 1. Therefore, we connect two pMOS transistors in series in the pull-up network.

EECS 16B, Fall 2018, Homework 1 5

 A

A B

(c) The pull-down network of the Boolean formula, Y = (A · B) +C , is given below. Design the pull-up
network (the dashed box) with 3 pMOS transistors.

A
C
B

Solution:  
Let Z be Z = A + B. From De Morgan’s laws, we have Y = A + B · C = Z · C, which means that
when Z = 1 and C = 0, Y should be pulled up to 1. For Z, we connect 2 pMOS transistors in parallel
as in part (a). Then, we connect the two pMOS transistors of Z and the one pMOS transistor of C in
series in the pull-up network.

EECS 16B, Fall 2018, Homework 1 6

 A B

A
C
B

(d) The pull-down network of the Boolean formula, Y = (A + B) ·C , is given below. Design the pull-up
network (the dashed box) with 3 pMOS transistors.

A B

Solution:  
Let Z be Z = A · B. From De Morgan’s laws, we have Y = A · B + C = Z + C, which means that
when Z = 1 or C = 0, Y should be pulled up to 1. For Z, we connect 2 pMOS transistors in series as in
part (b). Then, we connect the two pMOS transistors of Z and the one pMOS transistor of C in parallel
in the pull-up network.

EECS 16B, Fall 2018, Homework 1 7

 A

B C

A B

(e) For the circuit below, write the truth table for inputs A and B with output Y. What boolean operation
is this?
Note some of the gate voltages are A and B.

A B

A B

A A

B B

Solution:
In CMOS, if the gate of an nMOS is 1, the switch is closed and acts as a resistor. If the gate voltage is
0, then it acts as an open. The opposite is true for pMOS.
To get the truth table, draw the circuit for each input case and see whether the output is connected to
ground or VDD

EECS 16B, Fall 2018, Homework 1 8

 This is what the circuit should look like for A = 0, B = 0:

Y is connected to ground through resistors, so for the input combination A = 0, B = 0, Y = 0. Repeat

this for the 3 other cases and you will get the following truth table:

A B Y
0 0 0
0 1 1
1 0 1
1 1 0
This circuit is an XOR gate (A ⊕ B).

Mechanical:
4. First-Order Differential Equation Practice

EECS 16B, Fall 2018, Homework 1 9

 (a) Solve the equation 3 dtd f (t) + 6 f (t) = 0 given that f (0) = 7
Solution:
We know that the solution to the first-order differential equation must be of the form f (t) = Aeλt + B.
If we plug in that definition of f (t) into the given equation, we get

3(Aλ eλt ) + 6(Aeλt + B) = 0

(3Aλ + 6A)eλt + 6B = 0

We know that the coefficient of the exponential eλt and the constant must be zero, which means that
3Aλ + 6A = 0 and 6B = 0. Solving these yield λ = −2, B = 0. If we use our initial condition alongside
the parameters we just found, we get 7 = f (0) = Ae−2(0) + 0 = A, implying that A = 7. Therefore,
f (t) = 7e−2t .
(b) Solve the equation 3 f (t) − 6 f 0 (t) = 4 given that f (2) = 1
3
Solution:
f (t) = Aeλt + B

3(Aeλt + B) − 6(Aλ eλt ) = 4

(3A − 6Aλ )eλt + 3B = 4
1
λ=
2
4
B=
3
1 4
f (t) = Ae 2 t +
3
1 1 4
f (2) = = Ae 2 (2) +
3 3
1
A=−
e
1 1t 4
f (t) = − e 2 +
e 3
1 4
= −e 2 t−1 +
3

5. RC Circuit
C
IC (t)
+ −
+ IR (t)
VC (t)
+ Vs V VR (t) R
−

EECS 16B, Fall 2018, Homework 1 10

 (a) Find a differential equation for Vc (t) for t ≥ 0. Solve the differential equation using the initial condition
Vc (0) = 1V. Use component values of C = 1fF (1fF = 10−15 F), R = 10kΩ, and Vs = 2V
Solution:
First, we set one node to ground and label the other two nodes as u1 and u2 .

C
u1 IC (t) u2
+ −
+ IR (t)
VC (t)
+ Vs V VR (t) R
−

Vc (t) = u1 − u2
u1 = Vs
u2 = VR (t)
Vc (t) = Vs −VR (t) (1)

Using Ohm’s law:

VR (t) = RIR (t)

Using KCL at u2

IR (t) = IC (t)
VR (t) = RIC (t)

The current through a capacitor is:

dVC (t)
IC (t) = C
dt
dVC (t)
VR (t) = RC
dt
Plugging back into (1):
dVC (t)
Vc (t) = Vs − RC
dt
Rearranging, we get our differential equation:
dVC (t) VC (t) Vs
+ =
dt RC RC

EECS 16B, Fall 2018, Homework 1 11

 We can convert this to a homogeneous differential equation by using a change of variables:

x = VC (t) −Vs

VC (t) = x +Vs
dVC (t) dx
=
dt dt
substituting VC (t) in our differential equation, we get:

dx x +Vs Vs
+ =
dt RC RC
dx x
+ =0
dt RC
dx 1
=− x
dt RC
dx
The general solution to the differential equation dt = λ x is:

x = Aeλt
1
Where A is a constant determined by initial conditions. In this case, λ = − RC , giving us the solution:
t
x = Ae− RC

Next, we substitute VC (t) back into the equation:

t
VC (t) −Vs = Ae− RC
t
VC (t) = Ae− RC +Vs
Plugging in values for R, C, and Vs gives us:
t
−
VC (t) = Ae 10−11 +2

The final step is to determine A by plugging in the initial condition.

VC (0) = 1 = A + 2

A = −1
The overall answer is then: t
−
VC (t) = 2 − e 10−11 [V]

(b) Instead of having an initial condition of Vc (0) = 1V, we now have an initial condition of IR (0) = 150µA
(1µA = 10−6 A). Find the new expression for VC (t) for t ≥ 0. Use the same component values listed in
part (a)
Solution:
We can use the same general solution as in part (a), but we need to plug in our new initial condition to
solve for A. To do that, we need to determine what VC (0) is using our current’s initial condition.
Using Ohm’s law:
VR (0) = IR (0) ∗ R = 150 ∗ 10−6 ∗ 104 = 1.5 V

EECS 16B, Fall 2018, Homework 1 12

 We know that:
VC (0) = Vs −VR (0) = 2 − 1.5 = 0.5 V
Now we can plug it back into the general solution:

0.5 = A + 2

A = −1.5
This gives us the answer:
t
−
VC (t) = 2 − 1.5e 10−11 [V]

6. Write Your Own Question And Provide a Thorough Solution.

Writing your own problems is a very important way to really learn material. The famous “Bloom’s Tax-
onomy” that lists the levels of learning is: Remember, Understand, Apply, Analyze, Evaluate, and Create.
Using what you know to create is the top level. We rarely ask you any homework questions about the lowest
level of straight-up remembering, expecting you to be able to do that yourself (e.g. making flashcards). But
we don’t want the same to be true about the highest level. As a practical matter, having some practice at
trying to create problems helps you study for exams much better than simply counting on solving existing
practice problems. This is because thinking about how to create an interesting problem forces you to really
look at the material from the perspective of those who are going to create the exams. Besides, this is fun. If
you want to make a boring problem, go ahead. That is your prerogative. But it is more fun to really engage
with the material, discover something interesting, and then come up with a problem that walks others down
a journey that lets them share your discovery. You don’t have to achieve this every week. But unless you try
every week, it probably won’t ever happen.

Contributors:

• Edward Wang.

• Jaymo Kang.

• Yen-Sheng Ho.

• Kyle Tanghe.

EECS 16B, Fall 2018, Homework 1 13