DUAL PORT RAM USING UVM

Output waveforms

module dual_SRAM(input bit clk,rst,wr_en1,wr_en2, [1:0]ps, [3:0]addr1, [3:0]addr2, [7:0]datain1,

[7:0]datain2, output reg [7:0]dataout1,dataout2); // added read_port and write_port

logic[7:0]mem[0:15];

always@(posedge clk)

begin

if(rst==0)

begin

//dataout<=8'b0;

dataout1<=8'b0;

dataout2<=8'b0;

end

else if(ps==2'b00) //else if(prt_slct==2'b00) port1 write port 2 read

begin

if(wr_en1==0) //write_port = 0 is port 1

mem[addr1]<=datain1;

else if(wr_en2==1) //write_port = 1 is port 2

mem[addr2]<=datain2;

end

else if(ps==2'b01)

begin

if(wr_en1==0)

mem[addr1]<=datain1;

if(wr_en1==1) //read_port = 1 is port 2

dataout1<=mem[addr1];

end
 else if(ps==2'b11)

begin

if(wr_en2==0)

mem[addr2]<=datain2;

if(wr_en1==1) //read_port = 1 is port 2

dataout1<=mem[addr1];

end

end

endmodule

module DUT(inter.dut vif);

dual_SRAM vcode(.clk(vif.clk),.rst(vif.rst),.wr_en1(vif.wr_en1),.wr_en2(vif.wr_en2),.ps(vif.ps),

.datain1(vif.datain1), .datain2(vif.datain2),.addr1(vif.addr1),.addr2(vif.addr2),

.dataout1(vif.dataout1),.dataout2(vif.dataout2));

endmodule

INTERFACE

`include "uvm_macros.svh"

import uvm_pkg::*;

interface inter(input clk, rst);

logic wr_en1;

logic wr_en2;

logic[1:0] ps;

logic [7:0] datain1;

logic [7:0] datain2;

logic [7:0] dataout1;

logic [7:0] dataout2;

logic [3:0] addr1;

logic [3:0] addr2;

modport dut(input clk, rst,wr_en1,wr_en2,ps,datain1,datain2, addr1, addr2, output dataout1,dataout2);

endinterface

class seq_item extends uvm_sequence_item;

`uvm_object_utils(seq_item)

rand bit [7:0] addr1;

rand bit [7:0] addr2;

rand bit [7:0] datain1;

rand bit [7:0] datain2;

bit [7:0] dataout1;

bit [7:0] dataout2;

bit wr_en1,wr_en2;

bit[1:0] ps;

function new(string name = "seq_item");

super.new(name);

endfunction

/*

`uvm_object_utils_begin(seq_item)

`uvm_field_int(addr1,UVM_ALL_ON)

`uvm_field_int(addr2,UVM_ALL_ON)

`uvm_field_int(wr_en1,UVM_ALL_ON)

`uvm_field_int(wr_en2,UVM_ALL_ON)

`uvm_field_int(ps,UVM_ALL_ON)
 `uvm_field_int(dataout1,UVM_ALL_ON)

`uvm_field_int(dataout2,UVM_ALL_ON)

`uvm_field_int(datain1,UVM_ALL_ON)

`uvm_field_int(datain2,UVM_ALL_ON)

`uvm_object_utils_end

*/

// constraint addr_1{addr1 inside {[2:5]};};

//constraint data_1{datain1 inside {[2:5]};};

//constraint addr_1{addr1 inside {[6:10]};};

//constraint data_1{datain1 inside {[:18]};};

Endclass

class base_seq extends uvm_sequence#(seq_item);

`uvm_object_utils(base_seq)

function new(string name = "base_seq");

super.new(name);

endfunction

endclass

class mode_1 extends uvm_sequence#(seq_item);

`uvm_object_utils(mode_1)

seq_item pkt;

function new(string name = "mode_1");

super.new(name);

endfunction
task body();

begin

repeat(7) begin

pkt = seq_item::type_id::create("pkt");

start_item(pkt);

assert(pkt.randomize());

pkt.ps=2'b00 ;

pkt.wr_en1 = 0;

//pkt.print(uvm_default_line_printer);

finish_item(pkt);

start_item(pkt);

pkt.ps=2'b00;

pkt.wr_en2 = 1;

//pkt.print(uvm_default_line_printer);

finish_item(pkt);

end

end

endtask

endclass

class mode_2 extends uvm_sequence#(seq_item);

`uvm_object_utils(mode_2)

seq_item pkt;

function new(string name = "mode_2");

super.new(name);

endfunction

task body();

begin

repeat(7) begin

pkt = seq_item::type_id::create("pkt");

start_item(pkt);

assert(pkt.randomize());

pkt.ps=2'b01;

pkt.wr_en1 = 0;

//pkt.print(uvm_default_line_printer);

finish_item(pkt);

start_item(pkt);

pkt.ps=2'b01;

pkt.wr_en1 = 1;

//pkt.print(uvm_default_line_printer);

finish_item(pkt);
end

end

endtask

endclass

class mode_3 extends uvm_sequence#(seq_item);

`uvm_object_utils(mode_3)

seq_item pkt;

function new(string name = "mode_3");

super.new(name);

endfunction

task body();

begin

repeat(7) begin

pkt = seq_item::type_id::create("pkt");

start_item(pkt);

assert(pkt.randomize());

pkt.ps=2'b10;

pkt.wr_en2 = 0;

//pkt.print(uvm_default_line_printer);

finish_item(pkt);

start_item(pkt);
pkt.ps=2'b10;

pkt.wr_en2 = 1;

//pkt.print(uvm_default_line_printer);

finish_item(pkt);

end

end

endtask

endclass

class mode_4 extends uvm_sequence#(seq_item);

`uvm_object_utils(mode_4)

seq_item pkt;

function new(string name = "mode_4");

super.new(name);

endfunction

task body();

begin

repeat(7) begin

pkt = seq_item::type_id::create("pkt");

start_item(pkt);

assert(pkt.randomize());

pkt.ps = 2'b11;

pkt.wr_en1 = 1;
//pkt.print(uvm_default_line_printer);

finish_item(pkt);

start_item(pkt);

pkt.ps = 2'b11;

pkt.wr_en2 = 0;

//pkt.print(uvm_default_line_printer);

finish_item(pkt);

end

end

endtask

endclass

SEQUENCE

class base_seq extends uvm_sequence#(seq_item);

`uvm_object_utils(base_seq)

function new(string name = "base_seq");

super.new(name);

endfunction

endclass

SEQUENCER

class sequencer extends uvm_sequencer#(seq_item);

`uvm_component_utils(sequencer)
function new(string name = "sequencer", uvm_component parent);

super.new(name,parent);

endfunction

endclass

DRIVER

class driver extends uvm_driver#(seq_item);

`uvm_component_utils(driver)

seq_item pkt;

virtual inter vif;

function new(string name = "driver", uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

uvm_config_db#(virtual inter)::get(this, "", "vif", vif);

endfunction

task run_phase(uvm_phase phase);

pkt = seq_item::type_id::create("pkt");

forever

begin

seq_item_port.get_next_item(pkt);

@(posedge vif.clk);

if(pkt.ps == 2'b00)

begin
 if(pkt.wr_en1==0)

begin

vif.wr_en1 = pkt.wr_en1;

vif.addr1 = pkt.addr1;

vif.datain1 = pkt.datain1;

$display($time,"Packet driven with addr1 = %d, datain1 = %d",pkt.addr1, pkt.datain1);

end

else if(pkt.wr_en2==1)

begin

vif.wr_en2= pkt.wr_en2;

vif.addr2 = pkt.addr2;

$display($time,"Packet driven with addr2 = %d",pkt.addr2);

end

end

if(pkt.ps== 2'b01)

begin

if(pkt.wr_en1==0)

begin

vif.wr_en1 = pkt.wr_en1;

vif.addr1 = pkt.addr1;

vif.datain1 = pkt.datain1;

//vif.addr1 = pkt.addr1;
 $display($time," Packet driven with addr1 = %d,datain1=%d",pkt.addr1,pkt.datain1);

end

/* else if (pkt.read_port ==1)

begin

vif.wr_en = pkt.wr_en;

vif.read_port = pkt.read_port;

if(pkt.write_port ==0)

vif.addr2 = pkt.addr1;

else if(pkt.write_port ==1)

vif.addr2 = pkt.addr2;

$display(" Packet driven with addr2 = %d",pkt.addr2);

end*/

else if(pkt.wr_en1==1)

begin

vif.addr2 = pkt.addr2;

$display($time,"Packet driven with addr2 = %d",pkt.addr2);

end

end

if(pkt.ps== 2'b10)

begin

if(pkt.wr_en2==0)

begin

vif.wr_en2 = pkt.wr_en2;

vif.addr2= pkt.addr2;

vif.datain2 = pkt.datain2;
 //vif.addr1 = pkt.addr1;

$display(" Packet driven with addr2 = %d,datain2=%d",pkt.addr2,pkt.datain2);

end

else if(pkt.wr_en2==1)

begin

vif.addr2 = pkt.addr2;

$display($time,"Packet driven with addr2 = %d",pkt.addr2);

end

end

if(pkt.ps== 2'b11)

begin

if(pkt.wr_en1==1)

begin

vif.wr_en1 = pkt.wr_en1;

// vif.addr2= pkt.addr2;

vif.datain1 = pkt.datain1;

//vif.addr1 = pkt.addr1;

$display(" Packet driven with addr1 = %d",pkt.addr1);

end

else if(pkt.wr_en2==0)

begin

vif.wr_en2 = pkt.wr_en2;

vif.addr2 = pkt.addr2;

vif.datain2 = pkt.datain2;
 $display($time,"Packet driven with addr2 = %d, datain2 = %d",pkt.addr2, pkt.datain2);

end

end

seq_item_port.item_done();

end

endtask

endclass

MONITOR1

class monitor1 extends uvm_monitor;

`uvm_component_utils(monitor1)

seq_item pkt;

uvm_analysis_port#(seq_item) analysis_port1;//ip port

virtual inter vif;

function new(string name = "monitor1", uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

uvm_config_db#(virtual inter)::get(this, "", "vif", vif);

analysis_port1 = new("analysis_port1", this); //create my ip port

endfunction

virtual task run_phase(uvm_phase phase);

pkt = seq_item::type_id::create("pkt");

forever

begin

@(posedge vif.clk);

pkt.wr_en1= vif.wr_en1;

pkt.wr_en2= vif.wr_en2;

pkt.ps = vif.ps;

if(pkt.ps==2'b00)

begin

if(pkt.wr_en1 ==0)

begin

pkt.addr1 = vif.addr1;

pkt.datain1 = vif.datain1;

analysis_port1.write(pkt);

`uvm_info(get_name(),$sformatf("monitor1 to analysis port addr1 = %d, datain1 = %d", pkt.addr1,

pkt.datain1), UVM_NONE)

end

else if(pkt.wr_en2 ==1)

begin

pkt.addr2 = vif.addr2;

pkt.datain2 = vif.datain2;

analysis_port1.write(pkt);

`uvm_info(get_name(),$sformatf("monitor1 to analysis port addr2 = %d, datain2 = %d", pkt.addr2,

pkt.datain2), UVM_NONE)

end

end

if(pkt.ps==2'b01)

begin

if(pkt.wr_en1 ==0)
 begin

pkt.addr1 = vif.addr1;

pkt.datain1 = vif.datain1;

analysis_port1.write(pkt);

`uvm_info(get_name(),$sformatf("monitor1 to analysis port addr1 = %d, datain1 = %d", pkt.addr1,

pkt.datain1), UVM_NONE)

end

else if(pkt.wr_en1 ==1)

begin

pkt.addr2 = vif.addr2;

//pkt.datain2 = vif.datain2;

analysis_port1.write(pkt);

`uvm_info(get_name(),$sformatf("monitor1 to analysis port addr1 = %d", pkt.addr2), UVM_NONE)

end

end

if(pkt.ps==2'b10)

begin

if(pkt.wr_en2 ==0)

begin

pkt.addr2 = vif.addr2;

pkt.datain2 = vif.datain2;

analysis_port1.write(pkt);

`uvm_info(get_name(),$sformatf("monitor1 to analysis port addr2 = %d, datain2 = %d", pkt.addr2,

pkt.datain2), UVM_NONE)

end

else if(pkt.wr_en2 ==1)

begin

pkt.addr2 = vif.addr2;

//pkt.datain2 = vif.datain2;
 analysis_port1.write(pkt);

`uvm_info(get_name(),$sformatf("monitor1 to analysis port addr2 = %d", pkt.addr2,), UVM_NONE)

end

end

if(pkt.ps==2'b11)

begin

if(pkt.wr_en1 ==1)

begin

pkt.addr1 = vif.addr1;

//pkt.datain1 = vif.datain1;

analysis_port1.write(pkt);

`uvm_info(get_name(),$sformatf("monitor1 to analysis port addr1 = %d", pkt.addr1), UVM_NONE)

end

else if(pkt.wr_en2 ==0)

begin

pkt.addr2 = vif.addr2;

pkt.datain2 = vif.datain2;

analysis_port1.write(pkt);

`uvm_info(get_name(),$sformatf("monitor1 to analysis port addr2 = %d, datain2 = %d", pkt.addr2,

pkt.datain2), UVM_NONE)

end

end

end

endtask

endclass

MONITOR2

class monitor2 extends uvm_monitor;

`uvm_component_utils(monitor2)
seq_item pkt1;

uvm_analysis_port#(seq_item) analysis_port2; ///op port monitor 2 collecting port

virtual inter vif;

function new(string name = "monitor2", uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

uvm_config_db#(virtual inter)::get(this, "", "vif", vif);

analysis_port2 = new("analysis_port2", this);

endfunction

virtual task run_phase(uvm_phase phase);

pkt1 = seq_item::type_id::create("pkt1");

forever

begin

@(posedge vif.clk);

pkt1.wr_en1 = vif.wr_en1;

pkt1.wr_en2 = vif.wr_en2;

pkt1.ps = vif.ps;

if(pkt1.wr_en1 ==1)

begin

if(pkt1.ps ==2'b01 && pkt1.ps==2'b11) //port2 read

begin

pkt1.addr1 = vif.addr1;

pkt1.dataout1 = vif.dataout1;
 analysis_port2.write(pkt1);

`uvm_info(get_name(),$sformatf("monitor2 to analysis port addr1 = %d, dataout1 = %d",

pkt1.addr1, pkt1.dataout1), UVM_NONE)

end

/*else if (pkt.ps ==2'b11)

begin

pkt.addr2 = vif.addr2;

pkt.dataout = vif.dataout;

analysis_port2.write(pkt);

`uvm_info(get_name(),$sformatf("monitor2 to analysis port addr2 = %d, dataout = %d", pkt.addr2,

pkt1.dataout), UVM_NONE)

end*/

end

else if(pkt1.wr_en2==1)

begin

if(pkt1.ps==2'b10 && pkt1.ps==2'b00)

begin

pkt1.addr2 = vif.addr2;

pkt1.dataout2 = vif.dataout2;

analysis_port2.write(pkt1);

`uvm_info(get_name(),$sformatf("monitor2 to analysis port addr2 = %d, dataout2 = %d",

pkt1.addr2, pkt1.dataout2), UVM_NONE)

end

end

end

endtask

endclass
AGENT1

class agent1 extends uvm_agent;

`uvm_component_utils(agent1)

driver drv;

sequencer seqr;

monitor1 mon1;

function new(string name = "agent1", uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

drv = driver::type_id::create("drv", this);

mon1 = monitor1::type_id::create("mon1", this);

seqr = sequencer::type_id::create("seqr", this);

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

drv.seq_item_port.connect(seqr.seq_item_export);

endfunction

endclass

AGENT2

class agent2 extends uvm_agent;

`uvm_component_utils(agent2)

monitor2 mon2;
function new(string name = "agent2", uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

mon2 = monitor2::type_id::create("mon2", this);

endfunction

endclass

SCOREBOARD

class scoreboard extends uvm_scoreboard;

`uvm_component_utils(scoreboard)

int datain1_queue[$];

int datain2_queue[$];

uvm_tlm_analysis_fifo#(seq_item) ip_fifo;

uvm_tlm_analysis_fifo#(seq_item) op_fifo;

seq_item pkt, pkt1;

function new(string name = "scoreboard", uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

ip_fifo = new("ip_fifo", this);

op_fifo = new("op_fifo", this);

endfunction

virtual task run_phase(uvm_phase phase);

super.run_phase(phase);

pkt = seq_item::type_id::create("pkt1");

pkt1= seq_item::type_id::create("pkt2");

forever

begin

`uvm_info(get_full_name(),"SCR run_phase", UVM_NONE)

fork

ip_fifo.get(pkt);

`uvm_info(get_full_name(), $sformatf($time,"mon1 pkt : datain1 = %d,datain2=%d, addr1 = %d,addr2=

%d, dataout1 = %d,dataout2=%d",pkt.datain1,pkt.datain2, pkt.addr1,pkt.addr2,
pkt.dataout1,pkt.dataout2), UVM_NONE)

op_fifo.get(pkt1);

`uvm_info(get_full_name(), $sformatf($time,"mon2 pkt1 : datain1= %d, addr1 = %d, dataout1 =

%d",pkt1.datain1,pkt1.datain2, pkt1.addr1,pkt1.addr2, pkt1.dataout1,pkt1.dataout2), UVM_NONE)

join

//datain1 and datain 2stored in queue

if(pkt.wr_en1 ==0 && pkt1.wr_en1==0)

datain1_queue.push_front(pkt.datain1);

else if(pkt.wr_en2==0 && pkt1.wr_en2==0)

datain2_queue.push_front(pkt.datain2);
 $display("compare task starting");

compare();

end

endtask

task compare();

begin

pkt.dataout1 = datain1_queue.pop_back(); //now pkt have dout1

@(pkt.dataout1)

//mon2 has op so pkt1

$display("Packets to scr");

if(pkt.dataout1 == pkt1.dataout1)

`uvm_info(get_full_name(),$sformatf("Matched pkt.datain1=%d,pkt1.dataoout2=
%d",pkt.datain1,pkt1.dataout2),UVM_NONE)

else

`uvm_error(get_full_name(), "Mis-Matched;; data")

pkt.dataout2 = datain2_queue.pop_back(); //now pkt have dout2

@(pkt.dataout2)

//mon2 has op so pkt1

$display("Packets to scr");

if(pkt.dataout2 == pkt1.dataout2)

`uvm_info(get_full_name(), $sformatf("Matched pkt.datain2=%d,pkt1.dataoout2=

%d",pkt.datain2,pkt1.dataout2),UVM_NONE)

else
 `uvm_error(get_full_name(), "Mis-Matched;; data")

end

endtask

endclass

ENVIRONMENT

class environment extends uvm_env;

`uvm_component_utils(environment)

scoreboard sb;

agent1 agt1;

agent2 agt2;

function new(string name="environment",uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

sb=scoreboard::type_id::create("sb",this);

agt1=agent1::type_id::create("agt1",this);

agt2=agent2::type_id::create("agt2",this);

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

agt1.mon1.analysis_port1.connect(sb.ip_fifo.analysis_export);

agt2.mon2.analysis_port2.connect(sb.op_fifo.analysis_export);
endfunction

endclass

TEST1

class my_test1 extends uvm_test;

`uvm_component_utils(my_test1)

environment env;

function new(string name="my_test1",uvm_component parent);

super.new(name,parent);

endfunction

mode_1 bs;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

env = environment::type_id::create("env", this);

endfunction

virtual function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);

this.print();

endfunction

virtual task run_phase(uvm_phase phase);

super.run_phase(phase);

bs = mode_1::type_id::create("bs");

phase.raise_objection(this);

bs.start(env.agt1.seqr);

#20;

phase.drop_objection(this);
endtask

endclass

TEST2

class my_test2 extends uvm_test;

`uvm_component_utils(my_test2)

environment env;

function new(string name="my_test2",uvm_component parent);

super.new(name,parent);

endfunction

mode_2 bs;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

env = environment::type_id::create("env", this);

endfunction

virtual function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);

this.print();

endfunction

virtual task run_phase(uvm_phase phase);

super.run_phase(phase);

bs = mode_2::type_id::create("bs");

phase.raise_objection(this);

bs.start(env.agt1.seqr);

#20;

phase.drop_objection(this);

endtask
endclass

TEST3

class my_test3 extends uvm_test;

`uvm_component_utils(my_test3)

environment env;

function new(string name="my_test3",uvm_component parent);

super.new(name,parent);

endfunction

mode_3 bs;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

env = environment::type_id::create("env", this);

endfunction

virtual function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);

this.print();

endfunction

virtual task run_phase(uvm_phase phase);

super.run_phase(phase);

bs = mode_3::type_id::create("bs");

phase.raise_objection(this);

bs.start(env.agt1.seqr);

#20;

phase.drop_objection(this);

endtask

endclass
TEST4

class my_test4 extends uvm_test;

`uvm_component_utils(my_test4)

environment env;

mode_4 bs;

function new(string name="my_test4",uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

env = environment::type_id::create("env", this);

endfunction

virtual function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);

this.print();

endfunction

virtual task run_phase(uvm_phase phase);

super.run_phase(phase);

bs = mode_4::type_id::create("bs");

phase.raise_objection(this);

bs.start(env.agt1.seqr);

#20;

phase.drop_objection(this);

endtask
endclass

import uvm_pkg ::*;

`include "uvm_macros.svh"

`include "dual_intrf.sv"

`include "dual_dutuv.sv"

`include "dual_design.sv"

`include "dual_sequence_item.sv"

`include "dual_sequence.sv"

`include "sequence_mode1.sv"

`include "sequence_mode2.sv"

`include "sequence_mode3.sv"

`include "sequence_mode4.sv"

`include "sequencer.sv"

`include "dual_driver.sv"

`include "dual_monitor1.sv"

`include "dual_monitor2.sv"

`include "dual_agent1.sv"

`include "dual_agent2.sv"

`include "dual_scbd.sv"

`include "dual_envmt.sv"

`include "dual_test1.sv"

`include "dual_test2.sv"

`include "dual_test3.sv"

`include "dual_test4.sv"

TOP MODULE

module top;

bit clk,rst;
initial begin

clk = 0;

forever

#5 clk = ~clk;

end

initial

begin

rst = 0;

#4;

rst = 1;

end

inter vif(clk, rst);

DUT dut(vif);

initial begin

$dumpfile("dump.vcd");

$dumpvars;

uvm_config_db#(virtual inter)::set(uvm_root::get(),"*", "vif", vif);

run_test("my_test1");

end

endmodule

My_test1:
----------------------------------------------------------------

# UVM-1.0p1

# (C) 2007-2011 Mentor Graphics Corporation

# (C) 2007-2011 Cadence Design Systems, Inc.

# (C) 2006-2011 Synopsys, Inc.

# ----------------------------------------------------------------

# ** Error: (vsim-PLI-3494) acc_fetch_size(): The object_handle parameter is not a handle to a net,

register, or port, or a bit-select thereof. : dual_top.sv(45)

# Time: 0 ns Iteration: 0 Instance: /top

# ** Error: (vsim-PLI-3494) acc_fetch_size(): The object_handle parameter is not a handle to a net,

register, or port, or a bit-select thereof. : dual_top.sv(45)

# Time: 0 ns Iteration: 0 Instance: /top

# UVM_INFO @ 0: reporter [RNTST] Running test my_test1...

# ------------------------------------------------------------------

# Name Type Size Value

# ------------------------------------------------------------------

# uvm_test_top my_test1 - @460

# env environment - @469

# agt1 agent1 - @484

# drv driver - @500

# rsp_port uvm_analysis_port - @515

# sqr_pull_port uvm_seq_item_pull_port - @507

# mon1 monitor1 - @523

# analysis_port1 uvm_analysis_port - @643

# seqr sequencer - @530

# rsp_export uvm_analysis_export - @537

# seq_item_export uvm_seq_item_pull_imp - @631

# arbitration_queue array 0 -

# lock_queue array 0 -

# num_last_reqs integral 32 'd1

# num_last_rsps integral 32 'd1

# agt2 agent2 - @491

# mon2 monitor2 - @659

# analysis_port2 uvm_analysis_port - @668

# sb scoreboard - @477

# ip_fifo uvm_tlm_analysis_fifo #(T) - @677

# analysis_export uvm_analysis_imp - @716

# get_ap uvm_analysis_port - @708

# get_peek_export uvm_get_peek_imp - @692

# put_ap uvm_analysis_port - @700

# put_export uvm_put_imp - @684

# op_fifo uvm_tlm_analysis_fifo #(T) - @724

# analysis_export uvm_analysis_imp - @763

# get_ap uvm_analysis_port - @755

# get_peek_export uvm_get_peek_imp - @739

# put_ap uvm_analysis_port - @747

# put_export uvm_put_imp - @731

# ------------------------------------------------------------------

# UVM_INFO dual_scbd.sv(26) @ 0: uvm_test_top.env.sb [uvm_test_top.env.sb] SCR run_phase

# UVM_INFO dual_scbd.sv(30) @ 0: uvm_test_top.env.sb [uvm_test_top.env.sb]

# UVM_INFO dual_scbd.sv(34) @ 0: uvm_test_top.env.sb [uvm_test_top.env.sb]

# 5Packet driven with addr1 = 34, datain1 = 2

# UVM_INFO dual_monitor1.sv(34) @ 5: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis port

addr1 = 2, datain1 = 2

# 15Packet driven with addr1 = 34, datain1 = 2

# UVM_INFO dual_monitor1.sv(34) @ 15: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 2, datain1 = 2

# 25Packet driven with addr1 = 123, datain1 = 154

# UVM_INFO dual_monitor1.sv(34) @ 25: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 11, datain1 = 154

# 35Packet driven with addr1 = 123, datain1 = 154

# UVM_INFO dual_monitor1.sv(34) @ 35: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 11, datain1 = 154

# 45Packet driven with addr1 = 248, datain1 = 253

# UVM_INFO dual_monitor1.sv(34) @ 45: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 8, datain1 = 253

# 55Packet driven with addr1 = 248, datain1 = 253

# UVM_INFO dual_monitor1.sv(34) @ 55: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 8, datain1 = 253

# 65Packet driven with addr1 = 72, datain1 = 142

# UVM_INFO dual_monitor1.sv(34) @ 65: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 8, datain1 = 142

# 75Packet driven with addr1 = 72, datain1 = 142

# UVM_INFO dual_monitor1.sv(34) @ 75: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 8, datain1 = 142

# 85Packet driven with addr1 = 118, datain1 = 134

# UVM_INFO dual_monitor1.sv(34) @ 85: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 6, datain1 = 134

# 95Packet driven with addr1 = 118, datain1 = 134

# UVM_INFO dual_monitor1.sv(34) @ 95: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis
port addr1 = 6, datain1 = 134

# 105Packet driven with addr1 = 243, datain1 = 9

# UVM_INFO dual_monitor1.sv(34) @ 105: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 3, datain1 = 9

# 115Packet driven with addr1 = 243, datain1 = 9

# UVM_INFO dual_monitor1.sv(34) @ 115: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 3, datain1 = 9

# 125Packet driven with addr1 = 10, datain1 = 42

# UVM_INFO dual_monitor1.sv(34) @ 125: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 10, datain1 = 42

# 135Packet driven with addr1 = 10, datain1 = 42

# UVM_INFO dual_monitor1.sv(34) @ 135: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 10, datain1 = 42

# UVM_INFO dual_monitor1.sv(34) @ 145: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 10, datain1 = 42

# UVM_INFO C:/questasim_10.0b/verilog_src/uvm-1.0p1/src/base/uvm_objection.svh(1116) @ 155:

reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase

# UVM_INFO dual_monitor1.sv(34) @ 155: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to analysis

port addr1 = 10, datain1 = 42

# --- UVM Report Summary ---

# ** Report counts by severity

# UVM_INFO : 21

# UVM_WARNING : 0

# UVM_ERROR : 0

# UVM_FATAL : 0

# ** Report counts by id

# [RNTST] 1

# [TEST_DONE] 1

# [mon1] 16
# [uvm_test_top.env.sb] 3

# ** Note: $finish : C:/questasim_10.0b/verilog_src/uvm-1.0p1/src/base/uvm_root.svh(392)

# Time: 155 ns Iteration: 44 Instance: /top

#1

My_test2:

UVM_INFO @ 0: reporter [RNTST] Running test my_test2...

# ------------------------------------------------------------------

# Name Type Size Value

# ------------------------------------------------------------------

# uvm_test_top my_test2 - @460

# env environment - @469

# agt1 agent1 - @484

# drv driver - @500

# rsp_port uvm_analysis_port - @515

# sqr_pull_port uvm_seq_item_pull_port - @507

# mon1 monitor1 - @523

# analysis_port1 uvm_analysis_port - @643

# seqr sequencer - @530

# rsp_export uvm_analysis_export - @537

# seq_item_export uvm_seq_item_pull_imp - @631

# arbitration_queue array 0 -

# lock_queue array 0 -

# num_last_reqs integral 32 'd1

# num_last_rsps integral 32 'd1

# agt2 agent2 - @491

# mon2 monitor2 - @659

# analysis_port2 uvm_analysis_port - @668

# sb scoreboard - @477

# ip_fifo uvm_tlm_analysis_fifo #(T) - @677

# analysis_export uvm_analysis_imp - @716

# get_ap uvm_analysis_port - @708

# get_peek_export uvm_get_peek_imp - @692

# put_ap uvm_analysis_port - @700

# put_export uvm_put_imp - @684

# op_fifo uvm_tlm_analysis_fifo #(T) - @724

# analysis_export uvm_analysis_imp - @763

# get_ap uvm_analysis_port - @755

# get_peek_export uvm_get_peek_imp - @739

# put_ap uvm_analysis_port - @747

# put_export uvm_put_imp - @731

# ------------------------------------------------------------------

# UVM_INFO dual_scbd.sv(26) @ 0: uvm_test_top.env.sb [uvm_test_top.env.sb] SCR run_phase

# UVM_INFO dual_scbd.sv(30) @ 0: uvm_test_top.env.sb [uvm_test_top.env.sb]

# UVM_INFO dual_scbd.sv(34) @ 0: uvm_test_top.env.sb [uvm_test_top.env.sb]

 # 5 Packet driven with addr1 = 34,datain1= 2

# UVM_INFO dual_monitor1.sv(34) @ 5: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 2, datain1 = 2

# 15Packet driven with addr2 = 132

# UVM_INFO dual_monitor1.sv(34) @ 15: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 2, datain1 = 2

# 25 Packet driven with addr1 = 123,datain1=154

# UVM_INFO dual_monitor1.sv(34) @ 25: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 11, datain1 = 154

# 35Packet driven with addr2 = 247

# UVM_INFO dual_monitor1.sv(34) @ 35: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 11, datain1 = 154

# 45 Packet driven with addr1 = 248,datain1=253

# UVM_INFO dual_monitor1.sv(34) @ 45: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 8, datain1 = 253

# 55Packet driven with addr2 = 84

# UVM_INFO dual_monitor1.sv(34) @ 55: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 8, datain1 = 253

# 65 Packet driven with addr1 = 72,datain1=142

# UVM_INFO dual_monitor1.sv(34) @ 65: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 8, datain1 = 142

# 75Packet driven with addr2 = 211

# UVM_INFO dual_monitor1.sv(34) @ 75: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 8, datain1 = 142

# 85 Packet driven with addr1 = 118,datain1=134

# UVM_INFO dual_monitor1.sv(34) @ 85: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 6, datain1 = 134

# 95Packet driven with addr2 = 188

# UVM_INFO dual_monitor1.sv(34) @ 95: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 6, datain1 = 134

# 105 Packet driven with addr1 = 243,datain1= 9

# UVM_INFO dual_monitor1.sv(34) @ 105: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 3, datain1 = 9
 # 115Packet driven with addr2 = 255

# UVM_INFO dual_monitor1.sv(34) @ 115: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 3, datain1 = 9

# 125 Packet driven with addr1 = 10,datain1= 42

# UVM_INFO dual_monitor1.sv(34) @ 125: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 10, datain1 = 42

# 135Packet driven with addr2 = 230

# UVM_INFO dual_monitor1.sv(34) @ 135: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 10, datain1 = 42

# UVM_INFO dual_monitor1.sv(34) @ 145: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 10, datain1 = 42

# UVM_INFO C:/questasim_10.0b/verilog_src/uvm-1.0p1/src/base/uvm_objection.svh(1116) @
155: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase

# UVM_INFO dual_monitor1.sv(34) @ 155: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 10, datain1 = 42

# --- UVM Report Summary ---

# ** Report counts by severity

# UVM_INFO : 21

# UVM_WARNING : 0

# UVM_ERROR : 0

# UVM_FATAL : 0

# ** Report counts by id

# [RNTST] 1

# [TEST_DONE] 1

# [mon1] 16

# [uvm_test_top.env.sb] 3

# ** Note: $finish : C:/questasim_10.0b/verilog_src/uvm-1.0p1/src/base/uvm_root.svh(392)

# Time: 155 ns Iteration: 44 Instance: /top

My_test3:
UVM_INFO @ 0: reporter [RNTST] Running test my_test3...

# ------------------------------------------------------------------

# Name Type Size Value

# ------------------------------------------------------------------

# uvm_test_top my_test3 - @460

# env environment - @469

# agt1 agent1 - @484

# drv driver - @500

# rsp_port uvm_analysis_port - @515

# sqr_pull_port uvm_seq_item_pull_port - @507

# mon1 monitor1 - @523

# analysis_port1 uvm_analysis_port - @643

# seqr sequencer - @530

# rsp_export uvm_analysis_export - @537

# seq_item_export uvm_seq_item_pull_imp - @631

# arbitration_queue array 0 -

# lock_queue array 0 -

# num_last_reqs integral 32 'd1

# num_last_rsps integral 32 'd1

# agt2 agent2 - @491

# mon2 monitor2 - @659

 # analysis_port2 uvm_analysis_port - @668

# sb scoreboard - @477

# ip_fifo uvm_tlm_analysis_fifo #(T) - @677

# analysis_export uvm_analysis_imp - @716

# get_ap uvm_analysis_port - @708

# get_peek_export uvm_get_peek_imp - @692

# put_ap uvm_analysis_port - @700

# put_export uvm_put_imp - @684

# op_fifo uvm_tlm_analysis_fifo #(T) - @724

# analysis_export uvm_analysis_imp - @763

# get_ap uvm_analysis_port - @755

# get_peek_export uvm_get_peek_imp - @739

# put_ap uvm_analysis_port - @747

# put_export uvm_put_imp - @731

# ------------------------------------------------------------------

# UVM_INFO dual_scbd.sv(26) @ 0: uvm_test_top.env.sb [uvm_test_top.env.sb] SCR run_phase

# UVM_INFO dual_scbd.sv(30) @ 0: uvm_test_top.env.sb [uvm_test_top.env.sb]

# UVM_INFO dual_scbd.sv(34) @ 0: uvm_test_top.env.sb [uvm_test_top.env.sb]

# Packet driven with addr2 = 132,datain2=196

# UVM_INFO dual_monitor1.sv(34) @ 5: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# 15Packet driven with addr2 = 132

# UVM_INFO dual_monitor1.sv(34) @ 15: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# Packet driven with addr2 = 247,datain2= 92

# UVM_INFO dual_monitor1.sv(34) @ 25: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# 35Packet driven with addr2 = 247

# UVM_INFO dual_monitor1.sv(34) @ 35: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0
 # Packet driven with addr2 = 84,datain2= 67

# UVM_INFO dual_monitor1.sv(34) @ 45: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# 55Packet driven with addr2 = 84

# UVM_INFO dual_monitor1.sv(34) @ 55: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# Packet driven with addr2 = 211,datain2= 67

# UVM_INFO dual_monitor1.sv(34) @ 65: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# 75Packet driven with addr2 = 211

# UVM_INFO dual_monitor1.sv(34) @ 75: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# Packet driven with addr2 = 188,datain2= 53

# UVM_INFO dual_monitor1.sv(34) @ 85: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# 95Packet driven with addr2 = 188

# UVM_INFO dual_monitor1.sv(34) @ 95: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# Packet driven with addr2 = 255,datain2=219

# UVM_INFO dual_monitor1.sv(34) @ 105: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# 115Packet driven with addr2 = 255

# UVM_INFO dual_monitor1.sv(34) @ 115: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# Packet driven with addr2 = 230,datain2=152

# UVM_INFO dual_monitor1.sv(34) @ 125: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# 135Packet driven with addr2 = 230

# UVM_INFO dual_monitor1.sv(34) @ 135: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# UVM_INFO dual_monitor1.sv(34) @ 145: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0
 # UVM_INFO C:/questasim_10.0b/verilog_src/uvm-1.0p1/src/base/uvm_objection.svh(1116) @
155: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase

# UVM_INFO dual_monitor1.sv(34) @ 155: uvm_test_top.env.agt1.mon1 [mon1] monitor1 to

analysis port addr1 = 0, datain1 = 0

# --- UVM Report Summary ---

# ** Report counts by severity

# UVM_INFO : 21

# UVM_WARNING : 0

# UVM_ERROR : 0

# UVM_FATAL : 0

# ** Report counts by id

# [RNTST] 1

# [TEST_DONE] 1

# [mon1] 16

# [uvm_test_top.env.sb] 3

# ** Note: $finish : C:/questasim_10.0b/verilog_src/uvm-1.0p1/src/base/uvm_root.svh(392)

# Time: 155 ns Iteration: 44 Instance: /top