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CS8491 CA Syllabus 2017 Reg

This document outlines the syllabus for the course CS8491 - Computer Architecture at a university. The course is divided into 5 units that cover topics such as basic computer structure, arithmetic operations, processor and control unit design, parallel processing architectures, and memory and I/O systems. The course aims to help students understand computer fundamentals and design aspects of processors, memory, and I/O communication. It runs for 45 class periods over 15 weeks and references 3 textbooks for additional reading.

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195 views1 page

CS8491 CA Syllabus 2017 Reg

This document outlines the syllabus for the course CS8491 - Computer Architecture at a university. The course is divided into 5 units that cover topics such as basic computer structure, arithmetic operations, processor and control unit design, parallel processing architectures, and memory and I/O systems. The course aims to help students understand computer fundamentals and design aspects of processors, memory, and I/O communication. It runs for 45 class periods over 15 weeks and references 3 textbooks for additional reading.

Uploaded by

sathya priya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CS8491- COMPUTER ARCHITECTURE Syllabus 2017 Regulation

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CS8491                                COMPUTER ARCHITECTURE                                  L T P C


                                                                                                                            3 0 0 3

UNIT I BASIC STRUCTURE OF A COMPUTER SYSTEM                                                 


                         9
Functional Units – Basic Operational Concepts – Performance – Instructions: Language of the Computer –
Operations, Operands – Instruction representation – Logical operations – decision making – MIPS
Addressing.

UNIT II ARITHMETIC FOR COMPUTERS                       9


Addition and Subtraction – Multiplication – Division – Floating Point Representation – Floating Point
Operations – Subword Parallelism

UNIT III PROCESSOR AND CONTROL UNIT                 9


A Basic MIPS implementation – Building a Datapath – Control Implementation Scheme – Pipelining –
Pipelined datapath and control – Handling Data Hazards & Control Hazards – Exceptions.

UNIT IV PARALLELISIM                                                  9
Parallel processing challenges – Flynn‘s classification – SISD, MIMD, SIMD, SPMD, and Vector Architectures –
Hardware multithreading – Multi-core processors and other Shared Memory Multiprocessors –
Introduction to Graphics Processing Units, Clusters, Warehouse Scale Computers and other Message-
Passing Multiprocessors.

UNIT V MEMORY & I/O SYSTEMS                                  9


Memory Hierarchy – memory technologies – cache memory – measuring and improving cache performance
– virtual memory, TLB‘s – Accessing I/O Devices – Interrupts – Direct Memory Access – Bus structure – Bus
operation – Arbitration – Interface circuits – USB.

                                                                                                     TOTAL : 45 PERIODS

OUTCOMES:

On Completion of the course, the students should be able to:

Understand the basics structure of computers, operations and instructions.


Design arithmetic and logic unit.
Understand pipelined execution and design control unit.
Understand parallel processing architectures.
Understand the various memory systems and I/O communication.

TEXT BOOKS:

1. David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software
Interface, Fifth Edition, Morgan Kaufmann / Elsevier, 2014.
2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky and Naraig Manjikian, Computer Organization and
Embedded Systems, Sixth Edition, Tata McGraw Hill, 2012.

REFERENCES:

1. William Stallings, Computer Organization and Architecture – Designing for Performance, Eighth
Edition, Pearson Education, 2010.
2. John P. Hayes, Computer Architecture and Organization, Third Edition, Tata McGraw Hill, 2012.
3. John L. Hennessey and David A. Patterson, Computer Architecture – A Quantitative Approachǁ,
Morgan Kaufmann / Elsevier Publishers, Fifth Edition, 2012.

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