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DLD Question Bank: Unit 1

This document contains questions from 5 units on digital logic design. Unit 1 covers topics like positional and non-positional weighted codes, Demorgan's theorem, error correcting codes, and logic gates. Unit 2 covers minimization techniques, adders, decoders, multiplexers and comparators. Unit 3 discusses sequential circuits like latches, flip-flops, and their characteristics. Unit 4 covers shift registers, counters, and memory. Unit 5 is about finite state machines, Moore and Mealy models, and state minimization methods. The questions range from short 1-mark definitions to longer 12-mark problems involving circuit design and analysis.

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Mahadev Reddy
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1K views

DLD Question Bank: Unit 1

This document contains questions from 5 units on digital logic design. Unit 1 covers topics like positional and non-positional weighted codes, Demorgan's theorem, error correcting codes, and logic gates. Unit 2 covers minimization techniques, adders, decoders, multiplexers and comparators. Unit 3 discusses sequential circuits like latches, flip-flops, and their characteristics. Unit 4 covers shift registers, counters, and memory. Unit 5 is about finite state machines, Moore and Mealy models, and state minimization methods. The questions range from short 1-mark definitions to longer 12-mark problems involving circuit design and analysis.

Uploaded by

Mahadev Reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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DLD QUESTION BANK

UNIT 1
PART A (EACH QUESTION CARRIES 1 MARK)
1. Explain about positional weighted codes and non-positional weighted codes with an example
2. What do you mean by weighted code? Give example
3. Convert the following to the required form.
i).(11001.001)2= ( )10 ii) (126)8 = ( )10
4. State and Prove Demorgan’s theorem
5. What is Gray code?
6. What are the different illegal states of BCD and XS-3?
7. What is self-complementing code? Give example.
8. Find the 2’s complement of i).11101010 ii) 01111110
9. What do you mean by cyclic code?
10. How many types of parity are there? Name them.
11. What do mean by error-correcting code?
12. Which gate is called any or all gate? Why?
13. Write the properties of X-OR gate
14. What is AOI logic?
15. What is universal logic?

PART B (EACH QUESTION CARRIES 12 MARKS)


1. Convert the gray number 101101 into decimal, hex, octal, and (A0CB.EE)16 =( )10
2. Perform the subtraction in BCD using 9′s complement method for 592.6-887.9
3. Perform the following addition using excess-3 code i) 386+756 ii)1010 + 444
4. The message below has been coded in the 7 bit Hamming code and transmitted through noisy channel.
Decode the message assuming that at most a single error has occurred in each code word 1001001,
0111001, 1110110, and 0011011
5. Derive the Boolean expression for a two input Ex-OR gate to realize with the two input NAND gates
without using complemented variables and draw the circuit
6. Why a NAND and NOR gates are known as universal gates? Simulate all the basic Gates
7. Simplify the following Boolean expressions using the Boolean theorems.
(i) (A+B+C) (B+C) + (A+D) (A+C) (ii) (A+B) (A+B) (A+B)
UNIT -2
PART A (EACH QUESTION CARRIES 1 MARK)
1. What is a standard SOP form?
2. What is min term?
3. What are don’t cares?
4. What is a prime/essential implicant in K- map?
5. What is a full adder?
6. Why are subtractor ICs not available?
7. What is a parallel adder?
8. What is a comparator?
9. What is parity bit generator?
10. What is parity encoder?
11. What are applications of multiplexer (MUX)
12. What is decoder?
13. What is meant by combinational logic circuit?
14. What is ripple carry adder?
15. What is static hazards?

PART B (EACH QUESTION CARRIES 12 MARKS)


1. Minimize the following expression using K-map and realize using NAND Gates.
F (A,B,C,D) = ∑m (0,1,2,9,11) +d(8,10,14,15)
2. Simplify the following Boolean function using Tabular method.
F(A,B,C,D)=∑m(0,1,2,5,7,8,9,10,13,15)
3. Explain the priority encoder with a neat logic diagram
4. Realize a 3 to 8 decoder using 2 to 4 decoder and other required gates
5. Design a 32:1 multiplexer using two 4:1 multiplexer
6. Design 2-bit digital comparator and explain with neat sketch.
7. Design a full adder using two half adders and realize a full adder using only NAND gates.
8. Design 4-bit BCD to XS-3 code converter.
9. Explain about 3X8 Decoder.

UNIT -3
PART A (EACH QUESTION CARRIES 1 MARK)
1. What is meant by sequential circuits?
2. Compare latch and flip flop.
3. What is meant by clocked flip flops?
4. What do you mean by stable state?
5. What is race around condition in flip-flops?
6. What is an excitation table?
7. Convert D flip-flop to T flip flop
8. What is an active High latch? And an active low latch?
9. What are the applications of flip flop?
10. What do you mean by toggling?
11. What is master slave flip flop?
12. What is the characteristics equation of SR Flip flop?
13. What are the PRESET and CLEAR inputs
14. What do you mean by clock skew?
15. Define Level trigger, Edge trigger flip flops?

PART B (EACH QUESTION CARRIES 12 MARKS)


1. Draw the logic diagram of a S-R latch using NOR gates. Explain its Operation using excitation
table.
2. What is the drawback of JK flip-flop? How is it eliminated in Master Slave flip-flop? Explain
3. Obtain the characteristic equations of JK, SR, D and T flip-flops. Also explain excitation
tables of all these flip-flops
4. Convert JK flip-flop to T flip-flop and SR flip-flop to D flip-flop
5. What is meant by ‘edge triggered’? Differentiate SR-FF and JK-FF with their functional
operation and excitation tables.
6. Draw and explain the operation of the Master Slave J-K flip-flops with block diagram.

UNIT -4
PART A (EACH QUESTION CARRIES 1 MARK)
1. What are registers? Write any two applications.
2. What are the basic types of shift registers?
3. Write a short note on SISO
4. What is bidirectional shift register?
5. What is universal shift register?
6. What is a static shift register?
7. What is UART?
8. What is counter? Write any two applications?
9. What is other name of asynchronous counters? Why is that name?
10. What is a Ring Counter? What are applications of Ring counters?
11. What are the drawbacks of ripple counters?
12. Compare between synchronous and asynchronous counters?
13. What is ROM?
14. What is a PLD?
15. How is the memory size specified?

PART B (EACH QUESTION CARRIES 12 MARKS)


1. What is a shift register? Explain about the following modes of operations in a four bit shift
register i) shift right (ii) shift left (iii) bidirectional
2. What do you mean by universal shift register? Draw and explain its circuit diagram and
operation?
3. Design a mod-12 Ripple counter using T flip flops and explain its operation
4. Design and explain a synchronous MOD-10 down-counter using JK flip-flop
5.explain and design a synchronous BCD up-down counter using T flip flops & Design a
synchronous counter with T-flip flops that goes through the binary repeated sequence
0,1,3,7,6,4,0,1….
6. Explain the differences between ring and Johnson counters

UNIT- 5
PART A (EACH QUESTION CARRIES 1 MARK)
1. What is sequential machine?
2. Compare the Moore and mealy machine
3. What is meant by FSM?
4. List the capabilities of finite state machine
5. What is a state diagram? Describe w ith an example
6. Write Application of sequence detector
7. Define i) state table ii) state diagram.
8. What do you mean by successor?
9. What is a merger table?
10. What is minimal cover table?
11. What is closed sub graph?
12. Define state compatibility
13. What are incompletely specified machines?
14. What is the advantage of unspecified outputs?
15. Write Hazards types in sequential circuits

PART B (EACH QUESTION CARRIES 12 MARKS)


1. What are the Moore and mealy machines? Compare them
2. What are the capabilities and limitations of finite state machines?
3. Explain the procedure of state minimization using partition technique.
4. Explain the procedure of state minimization using the merger graph and merger table.
5. Write the steps in analyzing of sequential circuits

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