Scribd
Upload
870 views3 pages

Experiment 6: Adders: Figure 5.1: Half Adder

The document describes an experiment to realize half adders and full adders using basic gates and NAND gates. A half adder performs addition of two bits and produces a sum and carry output. A full adder performs addition of three bits - two input bits and a carry in bit - and produces a sum and carry out output. The experiment involves designing the circuits on Proteus and verifying the truth tables.

Uploaded by

Hassan Tariq
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
870 views3 pages

Experiment 6: Adders: Figure 5.1: Half Adder

The document describes an experiment to realize half adders and full adders using basic gates and NAND gates. A half adder performs addition of two bits and produces a sum and carry output. A full adder performs addition of three bits - two input bits and a carry in bit - and produces a sum and carry out output. The experiment involves designing the circuits on Proteus and verifying the truth tables.

Uploaded by

Hassan Tariq
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

Experiment 6: Adders

6.1 Aim:
To realize the working of Half Adder and Full Adder by using Basic gates and NAND gates

6.2 Learning Objective:


1. To realize the adder circuits using basic gates and universal gates.

2. To realize full adder using two half adders.

6.3 Components Required:


3. Proteus

4. IC 7400, IC 7408, IC 7486, IC 7432.

6.4 Theory:
Half Adder: A combinational logic circuit that performs the addition of two data bits, AandB, is called a
half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is the
carry bit Cr. The Boolean functions describing the half-adder are:

S = A xor B
Cr = A.B

Figure 5.1: Half adder

Full Adder: The half-adder does not take the carry bit from its previous stage into account. This carry
bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A
and B, and a carry-in bit, Cin , is called a full-adder. The Boolean functions describing the full-adder
are:
S = (A xor B) xor Cin Cout = A.B + Cin (A xor B)

Figure 5.2: Full adder


6.5 Procedure:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs .
5. Design the circuit on proteus and complete the Truth table

Half Adder
Inputs Outputs
A B S C
0 0
0 1
1 0
1 1

Table5.1:HalfAdder

Full Adder
Inputs Outputs

A B C S Co
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table5.2:Full Adder

VIVA QUESTIONS:
1. What is a half adder?

2. What is a full adder?


3. What are the applications of adders?

You might also like