2017 International Conference on Computer Communication and Informatics (ICCCI -2017), Jan.

05 – 07, 2017, Coimbatore, INDIA

VLSI Architecture for FFT using Radix-2

Butterfly of Complex Valued Data
Kausar Ali Dr. Paresh Rawat
PG Scholar Associate Professor & HOD
Electronics and Communication Department Electronics and Communication Department
Truba College of Science and Technology, Bhopal Truba College of Science and Technology, Bhopal
[email protected] [email protected]

Abstract— The Discrete Fourier Transform (DFT) is an description language in an easy manner. In the recent years,
important technique in the field of Digital Signal Processing the communication systems need to transmit voice and video
(DSP) and Telecommunications, especially for applications in signals of high quality in an efficient manner. In present day
Orthogonal Frequency Division Multiplexing (OFDM) systems. the efficient module is a high speed, reliable technology of
The Fast Fourier Transform (FFT) is an efficient algorithm to communication [4].
compute the DFT and its inverse. The FFT processor plays a key
role in the field of communication systems such as Digital Video
Orthogonal Frequency Division Multiplexing (OFDM) is such
or Audio Broadcasting, Wireless LAN with Standards of IEEE a reliable option to accomplish the above requirement. The
802.11, High Speed Digital Subscriber Lines etc. In this paper algorithms of FFT can be grouped into fixed-radix, mixed-
involves the implementation of a area efficient 8-point, 16-point, radix and split radix algorithms in a rough manner [5]. The
32-point, 64-point and 128-point single path delay feedback basic categories of algorithms of FFT include - Decimation in-
(SDF) and folding technique using radix-2 DIT FFT algorithm. frequency (DIF) and the Decimation-in-time (DIT) as shown
The proposed algorithms are used in radix-2 butterfly in all in Figure 1. Both of these algorithms depend on disintegration
stage. The proposed algorithm is area efficient and consumed of transformation of an N-point sequence into many
delay in previous algorithm. The all design are implementation subsequences in a successive manner. There is no major
vertex-2p device family Xilinx software.
difference between them as far as complexity of computation
Index Terms— FFT, Folding Technique, Single Path Delay is concerned. Generally DIT deals with the input and output in
Feedback (SDF), Serial in Serial out Shift Register reverse sequence and normal sequence respectively, while DIF
deals with input and output in normal sequence and reverse
sequence respectively. Only Decimation-in-frequency (DIF)
I. Introduction algorithm will be taken into consideration.
The Fourier Transform is an inevitable approach in signal
processing, particularly for applications in Orthogonal Output DIT-
DIF-FFT Output
Frequency Division Multiplexing (OFDM) systems [1]. The Unit Reorder Reorder- FFT
Discrete Fourier Transform decomposes a set of values into -ing ing Unit
different components of frequency. The Fast Fourier transform
(FFT) is an appropriate technique to do manipulation of DFT. (a) (b)
The algorithm of FFT was devised by Cooley and Tukey in
x1 y1 y1 y1
order to decrease the amount of complexity with respect to
time and computations [2]. w k

The hardware of FFT can be implemented by two types of wk

classifications- memory architecture and pipeline architecture. x2 y2 y2 y2
The memory architecture comprises a single processing (c) (d)
element and various units of memory [3]. The merits of
memory architecture include low power and low cost when Figure 1: (a) DIF FFT processing (b) DIT FFT processing
(c) DIF FFT butterfly (d) DIT FFT butterfly
compared to that of other styles. The specific demerits are
greater latency and lower throughput. The above demerits of
the memory architecture are totally eliminated by pipeline
architecture at the expense of extra hardware in an acceptable
II. FAST FOURIER TRANSFORM
way. The various types of pipeline architecture include Single There are two types with respect to FFT algorithm devised by
delay feedback (SDF), Single delay commutator (SDC) and Cooley and Tukey - Decimation-in-Time algorithm (DIT) and
multiple delay commutator (MDC). The pipeline architecture Decimation-in-Frequency algorithm (DIF). The computation
is a regular structure which can be adopted by using hardware of a sequence of N-point can be obtained by means of a dual

978-1-4673-8855-9/17/$31.00 ©2017 IEEE

 2017 International Conference on Computer Communication and Informatics (ICCCI -2017), Jan. 05 – 07, 2017, Coimbatore, INDIA

approach. The input sequence x(n) of size ‘N’ is decomposed types of multiplier, Kogge stone (KS) adder, subtractor, single
into samples of odd and even and the corresponding sub-
path delay feedback (SPD) pipeline and folding architecture.
sequences f1(n) and f2(n) are given by:
SISO: - SISO technique depends on the binary input. Suppose
f1 (n) = x(2n) the binary input of the system is 8 word length, then eight
(1)
delay flip flops are used in SISO register.
N
f1 (n) = x(2n + 1), n = 0,1............. − 1
2 (2)

Figure 2: Butterfly of Radix-2 DIT FFT Algorithm

Figure 4: Flow Chart of Proposed Algorithm

Different types of Multiplier:- there are three types of

multiplier are used in proposed algorithm, i.e. array multiplier,
sign (Baugh) multiplier and complex multiplier. Another name
of array multiplier is binary unsigned multiplied.
The Baugh - Wooley algorithm for the signed binary
multiplication is based on the concept shown in figure 5. The
algorithm specifies that all possible AND terms are created
white cell and all possible NAND terms are created gray cell.
The white cell consists of full adder and AND gate, but the
gray cell consists of full adder and NAND gate.

Figure 3: Butterfly of Radix-2 DIF FFT Algorithm

In figure 2, show the butterfly of radix-2 DIT FFT algorithm.

In this figure we used eight inputs and eight outputs. In case of
DIT the input sample is used bit reversal order while the
output of DIT FFT coefficients is generated in natural order.
In Figure 3, show the butterfly of radix-2 DIF FFT algorithm.
In case of DIF the input sample is used in natural order while
the output of DIF FFT coefficient is generated in bit reversed
order.

III. PROPOSED METHODOLOGY

In proposed method are used in binary input is going to the F F
F F F
serial input serial output (SISO) shift register as shown in
Figure 4. In proposing algorithm consist of SISO, different
Figure 5: Block Diagram of Sign Multiplier
 2017 International Conference on Computer Communication and Informatics (ICCCI -2017), Jan. 05 – 07, 2017, Coimbatore, INDIA

Complex multiplication is consisting of 4 multiplications, 2

adders and 1 subtraction. But in the proposed complex
multiplication is consisting of 3 multiplications, 1 adder and 1
subtraction in shown in figure 6.

Figure 6: Block Diagram of Complex Multiplication

Subtractor:- Subtractor is consist of half subtractor and full

subtractor depends on word length in proposed algorithm.
Single-path Delay Feedback Pipeline Architecture:- Herbert L. Figure 9: Proposed DIT Radix-2 FFT algorithm using Radix-2 Butterfly
Groginsky and George A. Works introduced a feedback
mechanism in order to minimize the number of delay
elements. In the proposed architecture one half of outputs from
each stage are fed back to the input data buffer when the input IV. SIMULATION RESULT
data are directly sent to the butterfly. The simulation results for various FFT algorithms have been
tested practically by implementing in the Vertex-2p Xilinx
software. Also these software outputs can be verified with
simulation results obtained using MODELSIM. Some of the
snapshots of results in the Xilinx software and simulation are
as follows

TABLE I: COMPUTATIONAL DELAY OF MULT-ADD AND ADD-

MULT OPERATIONS

Architecture TMA TAM TAM- TMA %

Difference
Figure 7: Flow Graph of the Radix-2 SDF Pipeline Architecture
8-bit

Folding Architecture:- Folding is a transformation technique Pramod Kumar 8.345 8.967 0.622 6.9%
using in DSP architecture, implementation for minimizing the Meher et al. [1]
number of functional blocks in synthesizing DSP architecture. Proposed Design 8.048 8.343 0.295 3.5%
Folding was first developed by Keshab K. Parhi and his
students in 1992. 16-bit

Pramod Kumar 9.453 10.32 0.868 8.4%

Meher et al. [1] 1

Proposed Design 8.653 9.240 0.587 6.3%

32-bit

Pramod Kumar 14.53 14.98 0.45 3.0%

Meher et al. [1]
Figure 8: (a) Without folding technique (b) With folding technique
Proposed Design 13.37 14.01 0.633 4.5%
 2017 International Conference on Computer Communication and Informatics (ICCCI -2017), Jan. 05 – 07, 2017, Coimbatore, INDIA

TABLE II: SHOW THE RESULT FOR PROPOSED ALGORITHM IN

ARRAY MULTIPLIER WITH VERTEX-2P DEVICE FAMILY V. CONCLUSION
The Fast Fourier transformation (FFT) is a frequently used
Design N Number of Number of MCPD
Digital signal processing (DSP) algorithms for the applications
slices 4 input (nsec)
of Orthogonal Frequency Division multiplexing (OFDM). The
LUTs
combination of Orthogonal Frequency Division Multiplexing
8 97 192 15.598 (OFDM) with Multiple Input Multiple Output (MIMO) signal
processing is a definite approach of enhancing the data rates of
Proposed 16 260 512 19.260 various communication systems such as Wireless LAN, e
structure Mobile, 4G etc.
32 656 1280 22.806
Since FFT processor is a complex module in OFDM, it is
64 1564 3072 26.319 highly inevitable to design the processor in an efficient way.
128 3141 6152 31.453 This research work involved the implementation of a low
delay and area efficient 128-point pipelined FFT processor
using radix-2 algorithm. The proposed algorithm is about 14-
15% consumed de in existing algorithm.
7000
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6000
5000 [1] Charles. Roth Jr., “Digital Systems Design using VHDL”,
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4000
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Figure 10: Bar Graph of proposed DIT Radix-2 FFT algorithm Mathematics”, Center for VLSI and Embedded System
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published by International Joural of Computer Applications®
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Figure 11: Bar Graph of proposed Complex DIT Radix-2 FFT RSA Encryption System Using Ancient Indian Vedic
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Technologies, International Institute of Information Technology
Hyderabad, India.
 2017 International Conference on Computer Communication and Informatics (ICCCI -2017), Jan. 05 – 07, 2017, Coimbatore, INDIA

[12] JagadguruSwami Sri Bharati Krishna Tirthaji Maharaja, “Vedic

Mathematics: Sixteen simple Mathematical Formulae from the
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