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A Notebook on Microprocessor System

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A Notebook on
Microprocessor System
(With 8085 & 8086 Programming)

Prepared By
Er. Shree Krishna Khadka
teaching.official @gmail.com

Inside
1. Microprocessor – An Introduction
2. Microprocessor Instructions
3. Assembly Language Programming
4. Bus Structure and Memory Devices
5. Input/Output Interface
6. Interrupts
7. Programming with 8085 and 8086
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Chapter: 1 Introduction
1.1 Introduction to Development of Computer -------------- 002
1.1.1 Historical Background -------------------------- 002
1.1.2 Automated Calculator --------------------------- 003
1.1.3 Stored Program Computer ------------------------ 003
1.1.4 The Von-Neumann Architecture ------------------- 004
1.1.5 Harvard Architecture --------------------------- 004
1.1.6 Von-Neumann Architecture Vs Harvard Architecture 005
1.2 Microprocessor --------------------------------------- 006
1.2.1 Introduction ----------------------------------- 006
1.2.2 Microcomputer ---------------------------------- 006
1.2.3 Evolution of Microprocessor -------------------- 007
1.2.4 Microprocessor as Programmable Device ---------- 007
1.2.5 Microprocessor as CPU -------------------------- 007
1.3 Microprocessor Based System -------------------------- 008
1.3.1 Address Bus ------------------------------------ 009
1.3.2 Data Bus --------------------------------------- 009
1.3.3 Control Bus ------------------------------------ 009
1.4 Microprocessor Architecture -------------------------- 010
1.4.1 8085A CPU -------------------------------------- 010
1.4.2 Description of 8085A Block Diagram ------------- 012
1.4.3 Description of 8085A Pin Diagram --------------- 014
1.4.4 Application of 8085A Microprocessor: MCTS ------ 018
1.4.5 INTEL 8086 CPU --------------------------------- 020
1.4.6 Description of 8086 Block Diagram -------------- 020
1.4.7 Description of 8086 Pin Diagram -------- 024

Chapter: 2 Microprocessor Instructions

2.1 Definitions ------------------------------------------ 028
2.1.1 Instruction ------------------------------------ 028
2.1.2 Instruction Cycle ------------------------------ 028
2.1.3 Machine Cycle ---------------------------------- 028
2.1.4 T-States --------------------------------------- 029
2.2 Instruction Descriptions ----------------------------- 029
2.3 Instruction Sheet & Formats -------------------------- 030
2.4 Register Transfer Language --------------------------- 031
2.5 8085 Addressing Modes -------------------------------- 032
2.6 8086 Addressing Modes -------------------------------- 034
2.7 8085 Instruction Sets -------------------------------- 037
2.8 8085 Machine Cycles & Timing Diagram ----------------- 041
2.8.1 Opcode Fetch Machine Cycle --------------------- 041
2.8.2 Memory Read Machine Cycle ---------------------- 043
2.8.3 Memory Write Machine Cycle --------------------- 044
2.8.4 Input/Output Read Machine Cycle ---------------- 045
2.8.5 Input/Output Write Machine Cycle --------------- 047
2.8.6 Fetch Execution Overlap ------------------------ 049
2.9 8085 Microprocessor Machine Code---------------------- 050
2.10 Counter and Time Delays ------------------------------ 051

Chapter: 3 Assembly Language Programming

3.1 Computer Programs & Programming Languages: A Review –- 055
3.2 Types of Programming Languages ----------------------- 055
3.2.1 Low Level Language ----------------------------- 055
3.2.2 High Level Language ---------------------------- 057

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3.3 Compiler & Interpreter ------------------------------- 058

3.4 Assembly Language Programming ------------------------ 058
3.4.1 Tools for Developing Assembly Language Program - 059
3.5 Assembler Instruction Format ------------------------- 061
3.6 Assembler Types -------------------------------------- 062
3.7 Assembler Directives --------------------------------- 065
3.8 Sample Assembly Language Program --------------------- 067
Chapter: 4 Bus Structure & Memory Devices
4.1 Bus Structure ---------------------------------------- 070
4.2 Memory & Its Types ----------------------------------- 072
4.3 Memory Interfacing ----------------------------------- 076
4.3.1 Requirement of Memory Chip --------------------- 076
4.3.2 Memory Map & Addresses ------------------------- 077
4.3.3 Memory & Instruction Fetch --------------------- 077
4.3.4 Control Signal Generation ---------------------- 082
4.4 Address Decoding ------------------------------------- 084
4.4.1 Input/Output (Peripheral) Mapped I/O ----------- 085
4.4.2 Memory Mapped I/O ------------------------------ 086
4.4.3 Unique Address Decoding ------------------------ 087
4.4.4 Non Unique Address Decoding -------------------- 087
Chapter: 5 Input/Output Interfaces
5.1 Input/Output Devices --------------------------------- 090
5.2 Input/Output Interfaces ------------------------------ 091
5.3 Serial Interface ------------------------------------- 091
5.3.1 Synchronous Data Transmission ------------------ 092
5.3.2 Asynchronous Data Transmission ----------------- 092
5.3.3 Synchronous Vs Asynchronous Data Transmission -- 095
5.4 8251A Programmable Communication Interface ----------- 097
5.5 RS 232-C Standard Interface -------------------------- 100
5.6 Parallel Interface ----------------------------------- 102
5.6.1 Method of Parallel Data Transfer --------------- 103
5.6.2 Synchronizing the Computer with Peripherals ---- 105
5.7 8279A Programmable Keyboard/Display Interface -------- 106
5.8 IEE-488 Bus Interface -------------------------------- 110
5.9 Serial Vs Parallel Communication --------------------- 111
5.10 8255A Programmable Peripheral Interface -------------- 112
Chapter: 6 Interrupt
6.1 Introduction ----------------------------------------- 123
6.2 8085A Interrupts ------------------------------------- 123
6.2.1 SIM Instructions ------------------------------- 127
6.2.2 RIM Instructions ------------------------------- 128
6.2.3 Interrupt Priority ----------------------------- 128
6.2.4 Interrupt Response ----------------------------- 129
6.3 Interrupt Service Routine & Its Requirement ---------- 130
6.3.1 Call & Return Instructions --------------------- 130
6.4 Interrupt Structure ---------------------------------- 132
6.4.1 Polling ---------------------------------------- 133
6.4.2 Chaining --------------------------------------- 134
6.5 8086 Interrupt System -------------------------------- 135
6.5.1 Pre Defined Interrupt -------------------------- 135
6.5.2 User Defined Software Interrupt ---------------- 136
6.5.3 User Defined Hardware Interrupt ---------------- 136
6.6 Interrupt Vector & Vector Table ---------------------- 136

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6.7 Interrupt Procedure in 8086 -------------------------- 136

6.8 8259A Programmable Interrupt Controller -------------- 137
6.8.1 Block Diagram Description ---------------------- 137
6.8.2 Interrupt Operation ---------------------------- 138
Chapter: 7 Programming Exercises
7.1 Programming with 8085 MP ----------------------------- 140
7.2 Programming with 8086 MP ----------------------------- 145

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Introduction
Contents:

o Introduction to Development of Computer

o Microprocessor: Introduction
o Microprocessor Based System
o Microprocessor Architecture
o 8085 & 8086 CPU

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Introduction to Development of a Computer

Historical Background

Computer is the most efficient and versatile electronic machine, basically developed by the
enhancement of calculator. Charles Babbage, the father of computer developed the
mechanical computer named “Difference Engine” and “Analytical Engine”.

o The Difference engine could perform the arithmetic operations like add and subtract. But
it could perform only single algorithm. Its output system was compatible to write on
medium such as punch card and early optical disk.
o The Analytical engine provides more advanced features in comparison to Difference
engine. It consists of mainly four components.

 The store (Memory)

 The mill (Computation Unit)
 Input section
 Output section

The store is used to hold the variables and results. The mill accepts operands from the store
and performs addition, subtraction, multiplication or division and returns a result back to store.
It reads the instruction and data from punched cards operates on it and have the results back to
the store or writes to the punch card.

The evolution of vacuum tubes led to the development of computer of new era. The world
first general purpose computer was ENIAC (Electronic Numerical Integrator and
Calculator). It was constructed in 1940 under the supervision of John Mauchly and John
Presper Eckert at the Universities of Pennsylvania. The ENIAC built by using vacuum tubes
was enormous in size and consumed very high power. However it was faster than mechanical
computers. The ENIAC was a decimal machine in which numbers were decimal number system
and the operation was performed in the same numbering system. Its memory consisted of 20
accumulators each capable of holding 10 digit decimal numbers. The major drawback of ENIAC
was that it had to be programmed manually by setting switches and plugging and unplugging
cables.

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Automated Calculator

An automated calculator is a data processing device that carries out logic and arithmetic
operation but has limited capability for the user. The calculator accepts data from a small
keyboard one digit at a time performs the arithmetic and logic calculation and shows the result
on the visual display i.e. LCD or LED. The calculators programs are stored in ROM while the
data that the user enters in RAM.

Features:

- Able to interface easily with keyboards and displays.

- Able to handle decimal digit as units.
- Able to execute the standard program store in ROM.
- Extendible so that mathematical function such as percentage, square root, trigonometric
etc. can be easily executed.
- Low cost, small in size and consumes low power.
- Flexible and can be used in any application like engineering, business etc.

Stored Program Computer

Store program computer is one of the most important breakthroughs in the entire field of
information technology. Stored program computer are those where the program (instruction) are
stored in same memory locations and brought into processor and decoded to perform the
intended operations. The idea was first glimpsed by Ada Lovelace & Charles Babbage in
1840’s; later in 1946 Von Neumann and his colleagues began the design of new stored
program computer called IAS (Institute of Advance Studies) in Princeton, NJ, USA.

Main Memory ALU I/O Equipments

Program
Control Unit

Fig: Structure of IAS Computer

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The Von-Neumann Architecture

Since, the task of entering and altering the programs for the ENIAC was extremely tedious.
The programming process could be facilitated if the program could be facilitated if the program
could be represented in a form suitable for storing in memory alongside the data. Then a
computer could get its instructions by reading them from the memory and a program could be
set or altered by setting the values of a portion of memory. This approach was based on
“Stored Program Concept” and was first adopted by John Von Neumann. The general
structure of Von Neumann’s machine is shown below.

CPU Data Bus

Program
ALU &
Data
PCU Address Bus Memory

Fig: Von Neumann Architecture

The main memory is used to store both data and instructions. The arithmetic logic unit is
capable of performing arithmetic and logical operations on binary data. The program control
unit interprets the instructions in memory and causes them to be executed. The I/O unit gets
operated from the control unit.

Harvard Architecture

This architecture based computer consists of separate memory spaces for the program and
data. Each memory space has its own address and data buses. As a result of this both instruction
and data can be fetched from memory concurrently. This feature provides a significant
processing speed improvement when compared with microprocessor devices based on Von-
Neumann type architecture.

Program memory Data memory

C
Program Data Bus Data Bus Data
P
Memory Program memory Data memory Memory
Address Bus U Address Bus

Fig: Harvard Architecture

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Von Neumann Architecture Vs Harvard Architecture

Von-Neumann Architecture SN Harvard Architecture

It is designed by John Von Neumann. 1. It is designed by Harvard.

The Von Neumann architecture uses 2. The structure where different data bus is
the single data bus for instruction and used for data and instruction are referred
data as Harvard architecture.
In this architecture there is only one 3. In this architecture data and instruction
shared memory for instruction are stored in different memories.
(program) and data.
In this architecture on bus is used so 4. The parallel bus used for code words
data cannot be fetched until the code and data words allows instruction and
fetch is completed. data to be fetched at the same time.
This architecture is referred as 5. This architecture is also referred as
“Stored Program Computer”. “Superscalar” as it can perform more
than one instruction per cycle.
Instruction and data have to be 6. Different program and data bus width is
fetched in sequential order, limiting possible, allowing program and data to
the operational bandwidth. be better optimized to the architectural
requirements.
Its design is simpler. 7. Its design is complex than Von
Neumann’s architecture.
Example: 8085, 8086. 8. Example: TMS320CXX from Texas
instrumentation

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Microprocessor

Introduction

A microprocessor is a multipurpose, programmable, clock driven, register based electronic

device that reads binary information from a storage device called memory, accepts binary data
as input and processes data according to those instruction and provides results as output. Thus a
microprocessor is an LSI chip that has capability to control, process and decision making
similar to that of human mind.

A typical programmable machine can be represented with four components as show in

figure below. They work together or interact with each other to perform a given task; thus they
comprise a system.

Memory

Micro-
processor Input

Output

Fig: A Programmable Machine

This system may be simple or sophisticated, depending on its applications and recognized
by various names depending upon the purpose for which it is designed. The microprocessor
applications are classified primarily in two categories:

o Reprogrammable Systems.
o Embedded Systems.

In reprogrammable systems, such as microcomputers, the microprocessor is used for

computing and data processing. These systems include general purpose microprocessors capable
of handling large data, mass storage devices and peripherals. A personal computer is a typical
illustration.

In embedded systems, the microprocessor is a part of a final product and is not available for
reprogramming to the end user. A copying machine is a typical example of an embedded
system.

Microcomputer
The microprocessor when embedded in a larger system can be a standalone unit controlling
processes or it can function as a CPU of a computer is called microcomputer. So, a computer
designed using a microprocessor as its CPU is the microcomputer.

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Evolution of Microprocessor

The microprocessor is essentially the product of research and development in two allied
fields: digital computer and semiconductor technology. Recognition as the first digital computer
is given to a machine called ENIAC, which was designed in 1940. After the development of
transistor in 1948 and development of integrated circuit, mainframe computer was developed in
1960’s and mainframe followed it.

The first microprocessor Intel 4004 was announced in 1971 by Intel Corporation. The
Intel 4004 was the first chip to contain the entire component on a CPU in a single chip. It was a
4-bit microprocessor which was shortly replaced by Intel 4040. At the same time Rockwell
International’s PPS4 and Toshiba’s T3 472 were developed.

The first 8-bit microprocessor 8008 was introduced again by Intel in 1972 that was followed
by a better version the 8080 from the same company. Some other 8-bit microprocessor like
Motorola’s M6800, National Semiconductors SC/MP, Zilog Corporation’s Z800, Fair
Child’s F8 and Intel 8005. Since then Intel & Motorola are leading companies for developing
microprocessor. After that Intel 8086, 80186, 80286, 80386, 80486 & Pentium Series whereas
Motorola 6802, 68000 etc. were developed.

Microprocessor as a Programmable Device

Microprocessor is a multipurpose electronic device used to perform various sophisticated

function as well as simple task that has been programmed during the manufacturing processes.
A programmer can select appropriate instructions and ask the microprocessor to perform various
tasks on a given set of data.

Microprocessor has a several set of instruction embedded in its memory to perform the
various task intended by the programmer. Thus the fact that the microprocessor is
programmable means it can be instructed to perform given tasks within its capability.

Microprocessor as a CPU (MPU)

In a traditional computer we can view microprocessor as a primary component of a

computer. It consists of various elements like ALU, Control Unit and various registers to hold
data and to operate on them. Figure below shows microprocessor used as a CPU. In the late
1960’s, using the advance feature of integrated circuit technology various discrete elements
were added on a single chip that can be used as a CPU.

A computer with a microprocessor as a CPU is called microcomputer. The microprocessor

is thus sometimes referred as microprocessor unit (MPU) or microcontroller unit (MCU). A
microcontroller is essentially an entire computer on a single chip that includes additional
devices such as analog to digital converter, serial I/O and timers.

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Microprocessor
Input Output
as a CPU

Memory

Fig: Block Diagram of Computer with Microprocessor as a CPU

Microprocessor Based System (Microcomputer System)

A microcomputer based system or microcomputer system consists of different units working

together to perform various operation in correct order. Basically the microcomputer system
includes four components. They are:
 Microprocessor
 Memory
 Input unit
 Output unit

ADDRESS BUS

I/O Port
M
M E
M Input
P O Port
U R
Y
Output
Port

CONTROL BUS

DATA BUS

Fig: Microprocessor Based System

The jobs that a microcomputer system performs can be listed as follows.

o To read instruction and data.
o Store inputted data and instruction.
o Executing the instruction i.e. processing the data.
o Storing the result of processing.
o To output the result of processing.

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All these operations part of the communication and processing of data between the
microprocessor and peripheral devices (including memory). To communicate with the
peripheral or a memory, the microprocessor needs to perform the following steps.
Step 1: Identify the peripheral or memory location with its address.
Step 2: Transfer binary information (data and instruction) using buses.
Step 3: Provide timing and synchronization signals.
In 8085 microprocessor all these functions are performed by using three sets of
communication lines called Buses. They are Address Bus, Data Bus and Control Bus as shown
in figure. In other word, it can also be called as “Three Bus Architecture System”.

Address Bus
In a microcomputer system each peripheral or memory location is identified by a binary
number called an address and the address bus is used to carry the address. The address bus is
unidirectional i.e. bit flows in one direction from the microprocessor to memory or peripheral
devices. The microprocessor uses the address bus to perform the first function mentioned in step
one. The width of the address bus clearly determines the maximum possible memory capacity of
the system.

In Intel 8085, there is 16-bit address, so it has capability of addressing memory up to 64 KB.

Data Bus

The data bus is a group of lines used to carry the data between various components of
microcomputer system. Data bus is bidirectional i.e. data flows in both direction between the
microprocessor and memory and peripheral devices. The microprocessor uses the data bus to
perform the second function mentioned in step 2.

In Intel 8085, there is 8-bit data bus so it can process 8-bit of data at a time. That’s why it is
called 8-bit microprocessor.

Control Bus

The control lines are somewhat different from address bus and data bus. The control bus is
comprised of various single lines that carry timing or synchronization signals. The
microprocessor uses the control bus to perform the third function mentioned in step 3.
The microprocessor generates specific control signals for every operation such as memory
read\write or I\O read\write. Some of the control signals are:

o Memory Read: It causes data from the memory to be placed on the data bus.
o Memory write: It causes the data on the data bus to be loaded into the memory.
o I\O Read: It causes data from the addressed I\O port to be placed on data bus.
o I\O Write: It causes the data on the data bus to be outputted to the addressed I\O port.
o Interrupt Request: Indicate that interrupt has been pending.

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Microprocessor Architecture

o A microprocessor has general purpose and special purpose registers. The general purpose
registers are use for storing intermediate data and operands. The special purpose registers
are the Accumulator, Program Counter and Stack Pointer.

o The Accumulator is used to store operands and/or to store the result of operations.

o The program counter and stack pointer registers are used to keep track of the memory
location from where the next instruction is to be fetched and location of the most recent
stack entry, respectively.

o The ALU in the microprocessor can add and operand and operand in the accumulator to an
operand in another register or add and operand in the accumulator with data specified by the
program. It can also carryout the Boolean operations and shift operations.

o The control circuitry in the microprocessor is responsible for issuing signal to control
functions of various components within as well as external to the microprocessor as per the
instruction executed. All the operations are coordinated by clock signals.

The 8085A CPU

The Intel 8085 is a general purpose 8-bit microprocessor capable of addressing up to 64 Kb

of memory. The internal logic design of a microprocessor is called architecture which
determines how and where various operations are performed by the microprocessor. The main
components of 8085 is shown in the functional block diagram and described below.

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Fig: The 8085A microprocessor functional block diagram

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Description of 8085A Block Diagram

1. Register
The 8085A has both 8-bit and 16-bit registers. It has 8-bit registers: B, C, D, E, H, L, A
(Accumulator) & F (Flag) and 16-bit registers: PC (Program Counter), SP (Stack Pointer)
& IR (Instruction Register). The PC and SP are addressable while IR is not. The registers of
8085A can be classified as:
o General Purpose Registers
o Special Purpose Register
1.1 General Purpose Registers

B, C, D, E, H and L are 8-bit general purpose registers and can be used either single
or as 16-bit register pairs BC, DE and HL. When used in the register pair mode, the high
order byte resides the first register and the low order byte in the second.
High Low
Order Order
Byte Byte

B C
Fig: BC Register Pair

Whereas register pair HL can be used as two independent 8-bit registers, functions
as a data pointer. It can hold memory addresses that are referred to a number of instructions,
which use ‘Register Indirect Addressing’. Hence, general purpose registers are used to
temporarily store operands or intermediate data in calculations.

1.2 Special Purpose Registers

o Accumulator
The accumulator (register A) is an 8-bit register accessible to the programmer. This
register is used to store 8-bit data and to perform arithmetic and logical operations. It is part
of the arithmetic and logical unit because one of the operand in the ALU operation is an
accumulator. The result of the operations is also stored in the accumulator. It is also to
access the data from the input output ports. When the data is read from input port, it is first
moved to the accumulator. Similarly, when data is send to the output port, it must be first
placed in the accumulator.

o Flags
Registers containing of five flip-flops which are set or reset according to the arithmetic
and logical operation and result in accumulator is known as flag register and each flip-flops
are flags. These flags are Carry (CY), Zero (Z), Sign (S), Parity (P) and Auxiliary carry
(AC). The microprocessor uses these flags to test data condition and for decision making
processes. These are described below.

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S Z × AC × P × CY
D7 D6 D5 D4 D3 D2 D1 D0

The Carry Flag (CY): If an arithmetic operation results in a carry, the carry flag is set
otherwise it is reset. The carry flag also serves as a borrow flag for subtraction.

The Zero Flag (Z): The zero flag is set if the ALU operation results in zero otherwise it
is reset. This flag is modified by the results in the accumulator as well as in other
registers.

The Auxiliary Carry (AC): In an arithmetic operation when a carry is generated by digit
D3 and passed onto the digit D4, the AC flag is set otherwise it is reset. This flag is used
in BCD arithmetic.

The Parity Flag (P): Since 8085 operates in even parity, parity flag is set when the result
of arithmetic and logical operation has even number of 1’s. Otherwise it is reset.

The Sign Flag (S): If the bit D7 or MSB (most significant bit) of the result is 1, the sign
flag is set. This flag is used with signed number. If D7 is 1, the number will be viewed as
negative; if it is 0, then it will be viewed as positive.

o Program Counter:
This is 16-bit register and used by microprocessor to sequence the execution of
instructions. A computer program consists of sequence of coded instruction. These
instructions are stored sequentially in the memory location. As the 8085 begins to execute an
instruction, the memory address of the first instruction to be executed is placed in program
counter. So it contains the memory address from which the next byte is to be fetched. Hence
the microprocessor uses these registers to sequences the execution of instruction.

o Stack Pointer
A stack is an area of memory set aside for the purpose of storing data by operation
known as stacking. As data is stored and retrieved, its location is specified by a 16-bit
register known as the stack pointer. The beginning of the stack is defined by loading a 16-bit
address on the stack pointer.
The stack pointer register holds the address of the last byte written into the stack. The
stack pointer is decremented automatically each time data is pushed onto the stack and is
incremented automatically when the data is popped off the stack.

o Temporary Register
The temporary register is an 8-bit register which is not accessible to the programmer.
These registers are internally used by the microprocessor to hold 8-bit data during the
execution of some instruction as a ‘Memory Reference’ instruction such as reading data
from a given address of memory or writing data to a given address of memory.

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o Instruction Register & Instruction Decoder

When an instruction is fetched from a memory it is loaded in the memory register. The
IR receives the operation codes of instructions from the internal data bus and passes it to the
instruction decoder and machine cycle encoding circuit. The instruction decoder decodes the
instruction so that microprocessor knows which type of operation is to be performed before
executing it. The output of the instruction decoder is fed to the control and timing unit. Then
control and timing unit then generates the necessary control and timing signals. This register
is not accessible to the programmer.

2. Arithmetic & Logic Unit (ALU)

The ALU performs the arithmetic operations like add, subtract etc and logical operations
like AND, OR, XOR etc. Besides this ALU carries out left and right shifting of the 8-bit data
stored in accumulator. When ALU perform arithmetic and logical operations one of the data is
stored in accumulator and the result of the operations is also referred to the accumulator itself.
The flags are affected by the arithmetic and logical operations in ALU.

3. Timing & Control Unit

This unit synchronizes all the microprocessor operations with the clock and generates the
control signals necessary for communications between the microprocessor and peripherals. The
RD and WR signals are sync pulses indicating the availability of data on the data bus.

The control circuitry is responsible for all the operation. All the operations are driven by the
clock signal. All operations are synchronously timed according to the clock signals. This
includes the following stages:

- Instruction Fetching Operations

- Instruction Decoding and
- Instruction Execution.

The control circuitry is also responsible for interaction with signals external to the CPU e.g.
receiving signals like interrupt request and wait request.

Description of 8085A Pin Diagram

Instructions can be categorized according to their method of addressing the hardware

registers and/or memory. Figure below shows the logic pin out of 8085 microprocessor. All the
signals can be classified into six groups.
1. Address Bus 2. Multiplexed Address/Data Bus
3. Control & Status Signals 4. Power Supply & Clock Frequency
5. External Initiated Signals Including Interrupts 6. Serial Input/Output Ports

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X1 1 40 VCC (+5V)

X2 2 39 HOLD

RESET OUT 3 38 HLDA

SOD 4 37 CLK (OUT)

SID 5 36 RESET IN

TRAP 6 35 READY

RST 7.5 7 34 IO/M

RST 6.5 8 33 S1

RST 5.5 9 32 RD

10 31
INTR 8085A WR

INTA 11 30 ALE

AD0 12 29 S0

AD1 13 28 A15

AD2 14 27 A14

AD3 15 26 A13

AD4 16 25 A12

AD5 17 24 A11

AD6 18 23 A10

AD7 19 22 A9

(GND) VSS 20 21 A8

FIG: 8085A PIN DIAGRAM

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1. Address Bus

The 8085 has eight signal lines (A15-A8), which are unidirectional and used as a higher order
address bus.

2. Multiplexed Address/Data Bus

The signal lines AD7-AD0 are bidirectional. They serve for a dual purpose. They are used as a
low order address bus in earlier part of the cycle and as a data bus in the later part of the cycle,
while executing an instruction. This process is known as multiplexing the bus.

3. Control & Status Signal

This group of signal includes two control signals ( RD & WR ), three status signals ( IO / M ,
S1 & S0) to identify the nature of operation and one special signal (ALE) to indicate the
beginning of the operation. These signals are described below.

o ALE - Address Latch Enable

This is a positive going pulse generated every time the 8085 begins an operation (machine
cycle) indicating that the bits on AD7-AD0 are address bits. This signal is used primarily to
latch the low order address bus from the multiplexed bus and generate a separate set of eight
address lines A7-A0.

o RD - Read
This is an active low Read control signal that indicates the selected I\O or memory device is
to be read and data are available on the data bus.

o WR - Write
This is a write control signal (active low). This signal indicates that the data on the data bus
are to be written into a selected memory or I\O location.

o IO / M - Input/Output & Memory

This is a status signal used to differentiate between I\O and memory operations. When it is
high it indicates an I\O operation and when it is low it indicates a memory operation. This
signal is combined with RD (Read) and WR (Write) to generate I\O and memory control
signals.

o S1 & S0 - Switch Status

These status signals similar to IO / M can identify various operations but they are rarely
used in small system.

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Machine Cycle Status

IO / M S1 S0 Control signal
Op-code Fetch 0 1 1 RD =0
Memory Read 0 1 0 RD =0
Memory Write 0 0 1 WR =0
I/O Read 1 1 0 RD =0
I/O Write 1 0 1 WR =0
Interrupt Acknowledge
1 1 1 INTA =0
Halt
Hold Z 0 0
Reset Z × × RD =Z, WR =Z, INTA =1
Z × ×
Table: 8085 Machine Cycle and Control signals
Note: Z = Tristate (High Impedance), × = Unspecified

4. Power Supply & Clock Frequency

The power supply and frequency signals are as follows:

o Vcc: +5v Power Supply

o Vss: Ground Reference
o X1, X2: A crystal (or RC, LC Network) is connected at these two pins. The frequency is
internally divided by two; therefore, to operate a system at 3MHz, the crystal should
have a frequency of 6MHz.
o CLK (OUT): Clock Output: This signal can be used as system clock for other devices.

5. Externally Initiated Signals, Including Interrupts

Externally initiated signals are described below.

o INTR (Input): This pin is interrupt request used as a general purpose interrupt.
o INTA (Output): This is an interrupt acknowledge pin used to acknowledge an
interrupt.
o Restart Interrupt: There are three restart interrupt; RST7.5, RST6.5 and RST5.5 in
8085. These are vectored interrupt and transfer the program control to specific memory
locations. They have higher priorities than the INTR interrupt. Among these three the
priority order is as 7.5, 6.5 and 5.5.
o TRAP (Input): This is a non mask able interrupt and has a highest priority.
o HLDA (Output): This hold acknowledge signal. This signal acknowledges the HOLD
request.
o READY (Input): This signal is used to delay the microprocessor read or write cycles
until a slow responding peripheral is ready to send or accept data. When this signal goes
low, the microprocessor waits for an integral number of clocks until it goes high.
o RESET IN: When the signal on this pin goes low, the program counter is set to zero, the
buses are tri-stated and the microprocessor is reset.
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o RESET OUT: This signal indicates that the microprocessor is being reset. This signal
can also be used to reset other devices.

6. Serial Input/Output Ports

The 8085 has two signals to implement the serial transmission; SID (Serial Input Data) and
SOD (Serial Output Data).

Application of 8085 Microprocessor

o Directly compatible with TTL IC’s leading to low cost of integrating the complete
microprocessor based system.
o 8085- based microprocessor
o Performing the high speed arithmetic and logic operations.

8085 Microprocessor Control Temperature System (MCTS)

Based on the concepts we discussed in the general instrumentation system, we can examine
a typical microprocessor controlled temperature system. This system is expected to read the
temperature in a room, display the temperature ate a liquid crystal display (LCD) panel, turn on
fan if the temperature is above a set point, and turn on a heater if the temperature is below a set
point.
Temperature
Sensor

A/D
Fan Heater
Converter

Input Output Output

Port I Port II Port II

Micro
Processor

ROM/ R/W Output

EPROM Memory Port III

LCD
Fig: Microprocessor Controlled Temperature System

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Microprocessor:
The above figure shows a processor with a system bus. The processor will read the binary
instructions from memory and execute those instructions continuously. It will read the
temperature, display it at the LCD display panel, and turn on/off the fan and the heater based on
the temperature.

Memory:
The system includes two types of memory. ROM will be used to store the program, called
the monitor program that is responsible for providing the necessary instructions to the processor
to monitor the system. This will be a permanent program stored in ROM and will not be altered.
The R/W memory is needed for temporary storage of data.

Input:
In this system, we need a device that can translate temperature into an equivalent electrical
signal; a device that translates one form of energy into another form is called a transducer. On
these days temperature sensors are available as integrated circuits. A temperature sensor is a
three-terminal semiconductor electronic device that generates a voltage signal that is
proportional to the temperature However, this is an analog signal and since the processor is
capable of handling only binary bits. Therefore, this signal must be converted into digital bits.
The analog-to-digital converter performs that function. It is an electronic semiconductor chip
that converts an input analog signal into the equivalent eight binary output signals. In
microprocessor-based systems, devices that provide binary inputs are connected to the processor
using devices such as buffers called input ports. In our system A/D converter is an input port,
and it will be assigned a binary number called an address. The microprocessor reads this digital
signal from the input port.

Output:
The above figure shows three output devices: fan, heater and liquid crystal display (LCD).
These devices are connected to the processor using latches called output ports.

Fan: This is an output device, identified as Port 1 that is turned on by the processor when
the temperature reaches a set higher limit.
Heater: This is also an output device, identified as Port 2 that is turned on by the processor
when the temperature reaches a set lower limit.
Liquid Crystal Display (LCD): This display is made of crystal material placed between
two plates in the form of a dot matrix or segments. It can display letters, decimal digits, or
graphic characters. The LCD in above figure will be used to display temperatures.

System Software (Programs):

The program that runs the system is called monitor program or system software. Generally,
the entire program is divided into subtasks and written as independent modules, and it is stored
in ROM or EPROM. When the system is reset, the microprocessor reads the binary command
from the first memory location of ROM and continues in sequence to execute the program.

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INTEL 8086 CPU

The 8086 is a far more powerful 16-bit machine with 1 MB memory capacity, in addition to
wider data path and larger registers. It has a feature of instruction pipelining. For this purpose it
consists of an instruction cache that pre-fetches a few instructions before they are executed. It
has 16- bit wide data bus and can operate on 16-bit of data from memory and ports.

Description of 8086 Block Diagram

This 16-bit 8086 microprocessor is divided internally into two functional units

o Bus Interface Unit (BIU)

o The Execution Unit (EU)

Both these units are designed to work simultaneously. The BIU is designed to function as
the external interface of the processor. The BIU generates address and sends them on the
address bus and then reads (or writes) data from memory (and ports) through the data bus.
Therefore BIU acts an interface of execution unit to the outside world.

The EU handles all controlling functions such as reading and writing the data, decoding the
instruction and executing the instruction. Block diagram of internal architecture of 8086
microprocessor is shown and described below.

1. Bus Interface Unit

The Bus Interface Unit can be divided into the following sub-units.

1. Instruction Queue:
The Instruction Queue is a 6-byte First-In-First-Out (FIFO) register which fetches
6 bytes of instruction from memory ahead of time. It helps to speed up execution of
program by overlapping instruction fetch with execution and this mechanism is known
as pipelining.
t1 t2 t3 t4 t5 t6

Inst. fetch Execution Inst. fetch Execution Inst. fetch Execution

Fig: Sequential Execution
8085

BIU Inst. fetch Inst. fetch Inst. fetch Inst. fetch Inst. fetch
EU Execution Execution Execution Execution Execution
Pipelined Execution
8086

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2. Instruction Pointer:
The instruction pointer stores the offset of the physical address in the segment of
memory as defined by the segment registers.

3. Segment Registers:
The 8086 has memory segmentation. Memory segmentation allows the 8086
microprocessor to be able to access four 64 Kbytes segments within its 1 MB memory
range at any given time. These four segments registers are:

o Code Segment Register (CS): All the instruction are located in memory (Code
Segment) pointed by the 16-bit code segment register and a 16-bit offset contained
in the instruction pointer (IP). The BIU computes 20-bit address called physical
address by using the content of CS and IP register.

o Data Segment Register (DS): The data segment register points to the current data
segment. Operands for the instruction are fetched from this segment.

o Stack Segment Register (SS): The stack segment register points to the current
stack.

o Extra Segment Register (ES): The extra segment register points to the extra
segment in which data (in excess of 64 K pointed to the DS) is used. String
instruction always uses extra segment.

4. Bus Control and Address Generator:

This unit handles the external bus as well as calculates the effective address from
where the instruction has to be fetched.
Example: Segment register × 1011 + offset value = Physical Address

2. The Execution Unit

The execution unit of 8086 may be divided into the following subunits.

1. General Purpose Registers:

The 8086 has four 16-bit general purpose registers AX, BX, CX and DX. These 16-
bit registers can also be used as 8-bit registers as:

AX - AH and AL (Accumulator Register)

BX - BH and BL (Base Register)
CX - CH and CL (Counter Register)
DX - DH and DL (Data Register)

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2. Special Purpose Registers:

o Pointer Registers:
The two pointer registers; Stack Pointer (SP) and Base Pointer (BP) are used to
access data in the stack segment. These registers are used to store 16-bit data but not 8-
bit data.

o Index Registers:
The two index register Source Index (SI) and Destination Index (DI) are used in
indexed addressing mode.

o Flag Register:
The 8086 has a 16-bit flag register which contains nine active flags. These active
flags can be divided into two types.

× × × × OF DF IF TF SF ZF × AF × PF × CF
Fig: 8086 flag register
 Conditional Flags:
The flag register in the EU, holds the conditional/status flags. These flags are
set or reset on the basis of result generated from the ALU. Out of nine, the 8086
has six status flags. They are:
1. Auxiliary Carry Flag-AF: It is set if a carry from the lower nibble into the
higher nibble or borrow from higher nibble into the lower nibble of the low
or high 8-bits of 16-bit number. This flag is used by BCD arithmetic
instruction; otherwise it remains reset.
2. Carry Flag-CF: It is set if a carry from addition or borrow from subtraction
is produced otherwise remains reset.
3. Overflow Flag-OF: It is set if arithmetic overflows, i.e. if the size of the
result exceeds the capacity of the destination location.
4. Sign Flag-SF: It is set if the most significant bit of the result is 1; otherwise
it is zero.
5. Parity Flag-PF: It is set if the result has even parity and remains zero for odd
parity of the result.
6. Zero Flag-ZF: It is set if the result is 0. Zero flag is 0 for non zero result.

 Control Flags:
The 8086 contains three control flags which are used for controlling the
microprocessor. The control bits in the flag register can be set or cleared by the
programmer.
1. Trap Flag-TF: It is used for single stepping through a program.
2. Interrupt Flag-IF: When the interrupt flag is set a program can be interrupted
for other more important operations.
3. Direction Flag-DF: It is used with string operation.

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3. Arithmetic & Logic Unit (ALU)

The arithmetic and logic unit of 8086 microprocessor can perform various arithmetic and
logical operation on 16-bit data.

System Buses

Address Data
Bus Bus

Address Generation & Bus Control

System

External
Control
Signal
General
Purpose
Register
I
AH AL 6 N
S
BH BL T
5 R
CH CL U
Instruction C
6
Decoder 4 T
-
DH DL I
B
and 3 O
Y
BP Control T
CS N
E
Index subsystem
DI 2 Q
and ES Segment U
Pointer SI Register E
SS 1 U
Register E
SP DS

Instruction Pointer

ALU

Flags

Execution Unit (EU) Bus Interface Unit (BIU)

Fig: Block Diagram of 8086 Microprocessor

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Description of Intel 8086 Pin Diagram

The Intel 8086 has two modes of operations:

o Minimum Mode and

o Maximum Mode

In microcomputer system, where only one 8086-microprocessor works as CPU, it operates

in minimum mode of operation. But in multiprocessor system, the 8086-microprocessor works
in maximum mode of operation.
The status of the pin MN/MX decides the operating mode of 8086. When the signal in this
pin goes high, 8086 operates in minimum mode. When the signal goes low, it operates in
maximum mode.

Minimum Mode of Operation

o AD15-AD0 (Bidirectional): These lines are time-multiplexed address/data bus. During T1

clock cycle, it carries lower order 16-bits of address and during T2, T3 & T4; it carries 16-bit
data (During Op-code Fetch).
o A19/S6-A16/S3 (Unidirectional): These lines are also time-multiplexed lines. They carry high
order 4-bits of memory address and during T2, T3 & T4; these lines carries status signals.

Encoding of S3 and S4
S5 and S6
S4 S3 Segment Register Employed
0 0 ES The S5 status signal is
0 1 SS the interrupt enable flag
1 0 CS or None bit whereas bit S6 is
always at logic 0.
1 1 DS

o BHE (Bus/Bank High Enable)/S7: The 8086 has a 20-bit address bus and each address can
store 8-bits of data. So when the instruction is executed, the word is actually written into
two consecutive memory locations. It will take two machine cycles, as it needs to write the
data two times in memory. So to make it possible to read or write a word in one machine
cycle, the memory for 8086 is set up as two ‘Banks’.
One memory bank contains all the bytes which have even addresses. The data lines of
this memory bank are connected to the lower eight data line D0-D7of 8086.
The memory bank contains all the bytes which have odd addresses. The data lines of this
memory bank are connected to the higher eight data line D8-D15 of 8086.
Address line A0 is used to enable the memory device in the lower bank. When A0
become low, it selects the lower bank memory devices as it indicates the even address.
Address lines A1 through A19 are used to select the desired memory location in upper and
lower bank of memory.

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BHE signal is use to enable the upper memory bank. BHE in conjunction with A0
determines whether a byte or words will be transferred from/to memory location as show
below.

BHE A0 Word/Byte Access

0 0 Whole word (from/to upper and lower bank)
0 1 Upper byte from/to odd address
1 0 Lower byte from/to even address
1 1 None (Both memory will be unselected)

During T2 and T4, the status line S7 is transmitted and it remains always high.

o NMI: Non Maskable Interrupt Request

o INTR: Interrupt Request

o CLK: Clock for 8086

o RESET: It is a system reset and an active high signal. When it goes high the microprocessor
goes into reset state.

o READY: It is an acknowledgement received from the addressed memory or I/O device. It is

an active high signal. When it goes high, it indicates that the peripheral or memory device is
ready to receive or transfer a data.

o TEST: This signal is used to test the status of math coprocessor 8087. The BUSY pin of
8087 is connected to the TEST pin of 8086.
Sometimes the 8086 needs the result of some computations that 8087 is doing,
before it could go to the next instruction of the program. When 8087 is busy, it sends the
high signal on TEST pin, which cause 8086 to wait in an idle state. When 8087 complete
computation, it makes BUSY signal low, thereby making TEST signal low. When TEST
signal become low the 8086 goes to the next instruction.

o INTA (Interrupt Acknowledge): On receiving interrupt request signal, the microprocessor

issues an interrupt acknowledge signal through this pin.

o ALE: This signal is used to latch the address into the address latch (8282/8283).

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GND 1 40 VCC

AD0 2 39 AD15

AD1 3 38 A19/S6

AD2 4 37 A18/S2

AD3 5 36 A17/S1

AD4 6 35 A16/S3

AD5 7 34 BHE/S7

AD6 8 33 MN/MX

AD7 9 32 RD

AD0-AD15 AD8 10 31 HOLD (RQ/GT0)

AD9 11 30 HLDA (RQ/GT1)

AD10 12 29 WR (LOCK)
INTEL 8086
AD11 13 28 M/IO (S2)

AD12 14 27 DT/R (S1)

AD13 15 26 DEN (S0)

AD14 16 ×

NMI 17 ×

INTR 18 ×

CLK 19 ×

GND 20 ×

RESET 21 ×

READY 22 ×

TEST 23 ×

(QS1)INTA 24 ×

(QS0)ALE 25 ×

FIG: INTEL 8086 PIN DIAGRAM

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Microprocessor Instruction
Contents:

o Definitions
o Instruction Description
o Instruction Sheets & Instruction Format
o Register Transfer Language
o 8085 & 8086 Addressing Modes
o 8085 Instruction Set
o 8085 Machine Cycles & Timing Diagram
o 8085A MP Machine Codes
o Counters & Time Delays

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Definitions

Instruction

An instruction is a binary pattern designed inside a microprocessor to perform a specific

function. In another word it can be defined as command in binary (i.e. machine language) that is
recognized and executed by a computer to accomplish a task.

Computer instructions are normally stored in central memory locations and are executed
sequentially one at a time. The control reads an instruction from a specific address in memory
and executes it. It then continues by reading the next instruction in sequence and executes it, and
so on. This type of instruction sequencing needs a counter to calculate the address of the next
instruction after the execution of the current instruction is completed. Thus execution of a
program consists of a sequence of instruction cycles, with one machine instruction per cycle.

Instruction Cycle

The entire group of instruction that determines what functions the microprocessor can
perform is called instruction set. Instruction cycle is defined as the time required completing the
execution of an instruction. The 8085 instruction cycle consists of one to six machine cycles or
one to six operations. Since, instruction is decoded in binary form and stored in memory; on the
basis of its clock speed computer takes a certain period to complete the task such as fetching,
decoding and execution.
The instruction cycle is combination of different smaller units. Basically, the instruction
cycle consists of two cycles, they are:

o Fetch and Decode Cycle

o Execute Cycle

The essential component of every instruction cycle is the fetch cycle. In the fetch cycle the
central processing unit obtains the instruction code from the memory for its execution. Once the
instruction code is fetched from memory, it is then executed.
The Execution cycle thus consists of different operations such as calculating the address of
the operands, fetching them, performing operations on them and finally outputting the results to
a specified location.

Machine Cycle

Machine cycle is defined as the time required for completing one operation of accessing
memory, I\O or acknowledging an external request. This cycle may consist of three to six T-
states. It consists of four operations: Op-code Fetch, Memory Read, Memory Write, I/O Read and
I/O Write. These micro operations will be discussed later.

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T-States
T1 T2 T3 T4 T5 T6

Fetch Cycle Execute Cycle

Instruction Cycle
Fig: Instruction Description

T-State

T-state is defined as the sub division of the operation performed in one clock period. During
T-second microprocessor (a sequential machine) stays in a particular state called T-state. So a
T-state lasts for a period of one clock cycle. T state and clock cycle are used synonymously.

Instruction Description

An instruction manipulates stored data and a sequence of instructions constitutes a program.

In general an instruction has two components, they are:

o Operation Code Field (Op-code)

o Address Field ( Operand)

The Op-code field specifies how data is to be manipulated. A data item may reside within a
microprocessor register or in the main memory. Thus, the purpose of the address field is to
indicate the address of a data item. The address field may contain more than one address to store
a data. For example let us consider the following example.

ADD R1 R0
Op-code Operand

If R0 is the source register and R1 is the destination register. The instruction then adds the
contents of register R0 with that of R1 and stores result in R1. Here, the combination of source
register (R0) and destination register (R1) is an operand whereas the command ADD is an Op-
code. Finally, Op-code and Operand form an instruction.

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Instruction Sheet & Instruction Formats

Each microprocessor can handle predefined number of instructions. For example an 8085A
can handle at the maximum of 256 instructions (2word length). The sheet which contains all these
instructions with their hex code, mnemonics, descriptions and functions is called an instruction
sheet.

Depending upon the number of address specified in instruction sheet, the instruction format
can be classified into three categories, they are:

o One Address Format (1 Byte Instruction)

o Two Address Format (2 Byte Instruction)
o Three Address Format (3 Byte Instruction)

1 Byte Instruction:
One byte will be Op-code and Operand will be default for that instruction. A one byte
instruction includes the Op-code and Operand in the same byte. These instructions are stored
in 8-bit binary format in memory; each requires one memory location.

Examples:
Task Op-Code Operand Binary Code Hex Code
Copy The contents of the accumulator
MOV C, A 0100 1111 4FH
in register C.
Add the contents of register B to the
ADD B 1000 0000 80H
contents of the accumulator.
Invert/Compliment each bit in the
CMA - 00101111 2FH
accumulator.

2 Byte Instruction:
In two byte instruction, the first byte specifies the operation code and the second byte
specifies the operand. These instructions would require two memory locations each to store
the binary codes.

Examples:
Task Op-Code Operand Binary Code Hex Code
Load an 8-bit data byte in the 0011 1110 3E
MVI A, 32H
accumulator. 0011 0010 32
Load an 8-bit data byte in the register 0000 0110 06
MVI B, F2H
B. 1111 0010 F2

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2 Byte Instruction:
In three byte instruction, the first byte specifies the operation code and the following two
bytes specify the 16-bit address where the second byte is the low order address and the third
byte is the high order address.

Examples:
Task Op-Code Operand Binary Code Hex Code
0011 1010 3A
Load contents of memory 2050H into A LDA 2050H 0101 0000 50
0010 0000 20
1100 0011 C3
Transfer the program sequence to
JMP 2085H 1000 0101 85
memory location 2085H. 0010 0000 20

Register Transfer Language (RTL)

A digital system is an interconnection of digital hardware modules that accomplish a

specific information processing task. Digital modules are best defined by the register they
contain and the operations that are performed on the data stored in them.

A language that uses the symbolic notation to literally define, express and describe the
transfer of data among the register called register transfer language. RTL describes the micro
operations. The operations executed on data stored in registers are called microoperations.
Microoperations are the functional or atomic operations of a processor, which is an elementary
operation performed on information stored in one or more registers e.g. shift, count, clear, load
etc. In micro operation each step is very simple and accomplishes very literally.

The term “Register Transfer” implies the availability of hardware logic circuits that can
perform a stated microoperation and transfer the result of the operation to the same or another
register. The word “Language” is borrowed from programmers, who apply this term to
programming language.

Example: A B; denotes a transfer of the content of register B into register A. It

designates a replacement of the content of A by the content of B.

Function of Control Unit of Microprocessor

The control unit of microprocessor performs the following two tasks.

o Causes the microprocessor to execute the micro operation in a proper sequence
determined by the program being executed.
o Generate the control signal that causes each micro operation to be executed. The control
signal generated by the control unit causes the opening and closing of logic gates, thus
resulting in the transfer of data to and from register and the operation of ALU.

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8085 Addressing Modes

As we know, instructions are command to the microprocessor to perform a certain task. The
instruction consists of Op-code and Data called Operand. It deals with the Source-register or
input port or a memory location and the Destination-a register or an output port or a memory
location. The various formats for specifying the operands for an instruction are called addressing
modes. The 8085 instruction set has different addressing modes which are described below.

o Direct Addressing (Absolute Addressing)

o Register Indirect Addressing
o Register Direct Addressing
o Implied Addressing (Inherent Addressing)
o Immediate Addressing

1) Direct or Absolute Addressing:

In this mode 8 or 16-bit address of an operand will be given just after the Op-code. It
means address is written directly in instruction. These instructions are of 2 or 3 byte with
first byte as the Op-code followed by 1 or 2 bytes of address of data.

Examples:

(i) LDA 2035H

This instruction loads the accumulator with the contents of the memory location having 16-
bit address of 2035H.
(ii) IN FCH
This is an example which has only one byte address. This will read the data at port FCH and
store the data at the accumulator.
(iii) OUT FFH
This instruction will display/write the data stored in accumulator at port address FFH.

2) Register Indirect Addressing:

In this mode, the address part of instruction specifies the memory location whose content
is the address of the operand. So this type of addressing mode contains a register pair which
stores the address of actual data. Since register pair is used indirectly to store the address of
data, it is called register indirect addressing.

Examples:

(i) MOV A, M
This instruction moves the contents of the memory location whose address is specified by
the contents of the register H & L to the accumulator. If register H & L contains 20H and
50H respectively then the contents of memory location 2050H will be transferred to the
accumulator.

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(ii) ADD M
This instruction adds the contents of the memory location whose address is specified by the
content of the register H & L to the content of the accumulator.
(iii) MVI M, 8bit data
This instruction moves the immediate 8-bit data to the memory location whose address is
specified by the contents of the register H & L.

3) Register Direct Addressing:

This mode of addressing specifies the register or register pair that contains the actual
data to be manipulated or operated on by the microprocessor.

Examples:

MOV A, B
This instruction moves the contents of the register B directly to register A (Accumulator).
ADD B
This instruction adds the contents of the register B with the contents of accumulator directly
and stores the result in accumulator.
ORA B
This instruction stores the result in accumulator after bitwise OR-operation between the
contents of register B and Accumulator.

4) Implied or inherent addressing:

The instruction of this mode does not require operand and the operand is implicitly
implied in the instruction. It implicitly assumes that the operand is accumulator. These
instructions are 1-byte instruction.

Examples

HLT: Halt the operation.

EI: Enable interrupt
STC: Set the carry flat.

5) Immediate Addressing:
In this mode the data is specified immediately after Op-code in the instruction. For an 8-
bit data, this mode uses 2-bytes instruction, with first byte as the Op-code followed by 1 or
2 byte of data whereas for 16-bit data, this mode uses 3-bytes instruction with first byte as
the Op-code followed by 2 bytes of data. In both cases, the actual data is part of the
instruction, and hence called immediate addressing.
Examples:
MVI A, 05H (8-bit Data)
This instruction moves the immediate data 05H to the accumulator.
LXI H, 7A21J (16-bit Data)
This instruction loads register H with 7AH and register L with 21H.

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8086 Addressing Modes

The addressing mode is a way of specifying a rule for interpreting or modifying the address
field of the instruction before the operand is actually referenced. The way the operands are
chosen during program execution is dependent on the addressing mode of the instruction.

Purpose:
- To give programming versatility to the user by providing such facilities as pointers to
memory, counters for loop control, indexing of data and program relocation.
- To reduce the number of bits in the addressing field of the instruction.
- To provide flexibility for writing programs that are more efficient with respect to the
number of instructions and execution time.

The 8086 processors let us access memory in many different ways. The 8086 memory
addressing modes provide flexible access to memory, allowing us to easily access variables,
arrays, records, pointers and other complex data types. The 8086 provides various addressing
modes to access instruction operands. Operands may be contained in registers, within the
instruction Op-code, in memory or in I/O ports.
The 8086 has twelve addressing modes. These modes can be classified into five groups.
They are:

o Register & Immediate Mode

o Memory Addressing Mode
o Port Addressing Mode
o Relative Addressing Mode
o Implied Addressing Mode

1. Register & Immediate Mode

In register mode source operands, destination operands or both may be contained in
registers. For example, MOV AX, BX moves the 16-bit contents of BX into AX. On the
other hand, MOV AL, BL moves the 8-bit contents of BL into AL.
In immediate mode, 8- or 16-bit data can be specified as part of the instruction. For
example, MOV CX, 5062H moves the 16-bit data 506216 into register CX.

2. Memory Addressing Mode

The execution unit (EU) has direct access to all registers and data for register and
immediate modes. However, the EU cannot directly access the memory operands. For
example, when the EU needs a memory operand, it sends an offset value to the bus interface
unit (BIU). This offset is added to the contents of a segment register after shifting it 4 times
toe the left, generating a 20-bit physical address. For example, suppose that the content of a
segment register is 205216 and the offset is 002016. Now, in order to generate the 20-bit
physical address, the EU passes this offset to the BIU. The BIU then shifts the segment
register 4 times to the left, obtains 2052016 and then adds the 002016 offset to provide the 20-
bit physical address 2054016. The 8086 must use as segment register whenever it accesses
the memory. Also, every memory addressing mode has a standard default segment register.

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However, a segment override instruction can be placed before most of the memory
operand instructions whose default segment register is to be overridden. For example, INC
BYTE PTR [START] will increment the 8-bit contents of a memory location in data segment
(DS) with offset START by one. However, segment DS can be overridden by extra segment
(ES) as follows: INC ES: BYTE PTR [START]. Segments cannot be overridden for stack
reference instructions such as PUSH and POP. The destination segment of a string segment,
which must be ES (if a prefix is used with a string instruction, only the source segment DS
can be overridden) cannot be overridden. The code segment (CS) register used in program
memory addressing cannot be overridden.
The EU calculates an offset from the instruction for a memory operand. This offset is
called the operand’s effective address (EA). It is a 16-bit number that represents the
operand’s distance in bytes from the start of the segment in which it resides.
The various memory addressing modes are as follows:
 Memory Direct Addressing
 Register Indirect Addressing
 Based Addressing
 Indexed Addressing
 Based Indexed Addressing
 String Addressing
1. Memory Direct Addressing:
In this mode, EA is taken directly from the displacement field of the
instruction. No registers are involved. For example, MOV BX, START moves the
contents of the 20-bit address computed from DS and START to BX.

2. Register Indirect Addressing:

EA of a memory operand may be taken directly from one of the base or
indeed registers (BX, BP, SI, DI). For example, consider MOV CX, [BX]. If [DS] =
200016, [BX] = 00416, and [2000416] = 022416, then after MOV CX, [BX], the contents
of CX is 022416. Here the segment register used in MOV CX, [BX] can be overridden,
such as MOV CX, ES: [BX]. Now, the MOV instruction will use ES instead of DS. If
[ES] = 100016 and [1000416] = 000216, then after MOV CX, ES: [BX], the register CX
will contain 000216.

3. Based Addressing:
EA is the sum of a displacement value (signed 8-bit or unsigned 16-bit) and
the contents of register BX or BP. For example, MOV AX, 4[BX] moves the
contents of 20-bit address computed from a segment register and [BX+4] into AX.
The segment register is DS or SS. If a displacement (4 in this case) is 8-bit, then the
8086 sign extends this to 16-bit in order to use SS register when the stack is
accessed; otherwise, this mode uses segment register DS. When memory is accessed,
the 20-bit physical address is computed from BX and DS. On the other hand, when
the stack is accessed, the 20-bit physical address is computed from BP and SS. The
BP may be considered as the user stack pointer while SP is the system stack pointer.

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4. Indexed Addressing:
EA is calculated from the sum of a displacement value and the contents of
register SI or DI. For example, MOV AX, VALUE [SI] moves the contents of the 20-
bit address computed from VALUE, SI and the segment register into AX. The
segment register is DS. The displacement (VALUE in this case) can be unsigned 16-
bit or sign-extended 8-bit.

5. Base Indexed Addressing:

EA is computed from the sum of a base register (BX or BP), and index
register (SI or DI), and a displacement. For example, MOV AX, 4[BX] [SI] moves
the contents of the 20-bit address computed from the segment register and [BX] +
[SI] + 4 into AX. The segment register is ES. The displacement can be unsigned 16-
bit or sign-extended 8-bit.

6. String Addressing:
This mode uses index registers. SI is assumed to point to the first byte or
word of the source string ad DI is assumed to point to the first byte or word of the
destination when a string instruction is executed. The SI or DI is automatically
incremented or decremented to point to the next byte or word depending on DF. The
default segment register for source is DS and it may be overridden. The segment
register for destination must be ES.

3. Port Addressing Mode

Two I/O port addressing modes can be used: the direct port and indirect port modes. In
either case, 8-or 16-bit I/O transfers must take place via AL or AX, respectively.

In direct port mode, the port number is an 8-bit immediate operand to access 256 ports.
For example, IN AL, 02 move the contents of port 02 to AL.

In indirect port mode, the port number is taken from DX allowing 64K bytes or 32
words or ports. For example, suppose [DX] = 0020, [port 0020] = 0216, and [port 0021]
= 0316, then after IN AX, DX register AX contains 030216. On the other hand, after IN
AL, DX, register AL contains 0216.

4. Relative Addressing Mode

Instructions using this mode specify the operand as a signed 8-bit displacement relative
to PC. An example is: JNC START. This instruction means that if carry = 0, then PC is
loaded with current PC contents plus the 8-bit signed value of START; otherwise, the next
instruction is executed.

5. Implied Addressing Mode

Instructions using this mode have no operands. An example is CLC, which clears the
carry flag to zero.

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8085 Instruction Set

An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The entire group of instruction is called instruction set, which determines what
functions the microprocessor can perform. The 8085 instruction set can be classified into
following five functional categories

o Data Transfer Operation

o Arithmetic Operation
o Logical Operation
o Branching Operation
o Machine Control Operation

1. Data Transfer Operations:

This group of instructions copies data from a location called a source to another location,
called a destination, without modifying the contents of the source. The data transfer
operations in 8085 consists of 88 different Op-codes. The transfer of data may be between
the registers or between register and memory or between and I/O device and accumulator.
None of these instructions changes the flags.

Data transfer group consists of following set of instructions.

Mnemonics Operation Examples

1. MVI r, data (8 bit) Move data immediate to register MVI B, 4FH
2. MVI M, data (8 bit) Move data immediate to memory, whose address is in H MVI M, 3AH
&L
3. MOV r1, r2 Move data from register to register (r2 to r1) MOV B, A
4. MOV M, r Move data from register r to memory whose address is in MOV M, C
H&L
5. MOV r, M Move data from location specified by H&L register to MOV B, M
register r.
6. LXI rp, data Load immediate register pair with double byte data. LXI B 2050H
7. STA addr Store the data from A direct at the address that follows. STA 2070H
8. LDA addr Load the data into A direct from the address that LDA 2050H
follows.
9. SHLD addr Store H & L direct. SHLD 2050H
10. LHLD addr Load H & L direct. LHLD 2040H
11. LDAX rp Load A with the contents of the memory location whose LDAX B
address is in rp.
12. STAX rp Store the contents of A in memory whose address is in STAX D
rp.
13. XCHG Exchange the content of H with D and L with E. XCHG
14. IN 8bit (port addr) Read the data from input device and store in IN 07H
accumulator.
15. OUT 8bit (port addr) Write the data from an accumulator to output device. OUT 32H

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2. Arithmetic Operations:
Arithmetic Operation performs following task

o Addition
o Subtraction
o Increment (Add by 1)
o Decrement (Subtract by1)

This group consists of following set of instruction

Mnemonics Operation Examples

1. INR r Increment the contents of register INR D
2. INR M Increment the contents of memory, the address of which is in INR M
HL.
3. INX rp Increment the contents of register pair. INX H
4. DCR r Decrement the contents of register pair DCR E
5. DCR M Decrement the contents of memory, which address is in HL. DCR M
6. DCX rp Decrement the contents of register pair DCX H
7. ADD r Add the contents of register to the contents of accumulator. ADD B
8. ADD M Add the contents in memory to A; the address of which is in ADD M
HL.
9. ADI data Add data immediate to A. ADI 37H
10. ADC r Add register r with carry to A. ADC B
11. ADC M Add data in memory to A with carry. ADC M
12. ACI data Add immediate data to A with carry. ACI 05H
13. DAD rp Add register pair rp to H and H. here rp can be BC, DE, HL or DAD H
SP.
14. SUB r Subtract register r from A. SUB C
15. SUB M Subtract the contents of memory from A; the address of SUB M
memory is in HL.
16. SUI data Subtract data immediate from A. SUI 37H
17. SBB r Subtract register r from A with borrow SBB D
18. SBB M Subtract the contents of memory from A with borrow. SBB M
19. SBI data Subtract immediate data from A with borrow. SBI 37H
20. DAA Decimal adjust accumulator. DAA

This adjusts A to packed BCD after addition of two BCDs. It functions in two steps.

a) If the lower 4-bit of A are greater than 9 or the auxiliary carry is set, then it adds 06H to A.
b) Subsequently if the higher 4-bits of A are now greater than 9 or the carry flag is set, it adds
60H to A.
Example:
A = 39BCD
Add 12BCD
A = 39BCD = 0011 1001
+ 12BCD = 0011 0010
51BCD = 0100 1011 = 4B

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The binary sum is 4BH. The value of low order four bit is larger than 9. Add 06 to low order
4-bits.

0011 1001
+ 0001 0010
4B 0100 1011
+06 0110
51H 0101 0001

3. Logical Instructions:
This instruction performs following operations

o AND
o OR
o XOR (Exclusive OR)
o Compare
o Rotate Bits
o Complement

This group consists of following set of instructions:

Mnemonics Operation Example

1. ANA r Logically AND the contents of a register with the contents of A. ANA B
2. ANA M Logically AND the contents of A with the contents of memory ANA M
whose address is in HL register.
3. ANI data AND immediate with A. ANI 32H
4. XRA r Exclusive OR register with A. XRA B
5. XRA M Exclusive OR memory with A. XRA M
6. XRI data Exclusive OR immediate with A. XRI 07H
7. ORA r OR register r with A. ORA B
8. ORA M Logically OR the contents of memory with contents of A; the ORA M
address of which is in HL register.
9. ORI data Logically OR immediate data with the contents of A. ORI 20H
10. CMP r Compare the contents of register r with the contents of A. CMP B
11. CMP M Compare the contents of memory with contents of A; the address CMP M
of which is in HL.
12. CPI data Compare data immediate with A CPI 27H
13. STC Set carry STC
14. CMC Complement carry CMC
15. CMA Complement A. CMA
16. RLC Rotate A left without carry. RLC
17. RRC Rotate A right without carry. RRC
18. RAL Rotate A left through carry. RAL
19. RAR Rotate A right through carry. RAR

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4. Branching Instruction:
This group consists of following set of instructions.
o JMP 16 bit address Jump unconditionally to the address.
o JCond. Address; Jump conditionally to the address given.
This instruction causes a jump to the given address if a specified condition is satisfied.
The condition could be:
JC Jump on carry C=1
JNC Jump on not carry C=0
JP Jump on positive S=0
JM Jump on minus S=1
JPE Jump on parity even P=1
JPO Jump on parity Odd P=0
JZ Jump on zero Z=1
JNZ Jump on not zero Z=0
o PCHL: Copies the contents of HL into the following program counter.
o CALL address: Call unconditionally a sub routine at the address given.
o Ccond. Address: Call sub routine at the given address conditionally.
This instruction calls the subroutine at the given address if a specified condition is
satisfied. The following conditional calls can be made
CC Call on carry C=1
CNC Call on no carry C=0
CP Call on positive S=0
CM Call on minus S=1
CPE Call on parity even P=1
CPO Call on parity odd P=0
CZ Call on Zero Z=1
CNZ Call on no zero Z=0
o RET: Return from the subroutine unconditionally.
o Rcond. : Return from the subroutine conditionally.
This instruction returns the control to the main program if the specified condition is
satisfied.
RC Return on carry C=1
RNC Return on no carry C=0
RP Return on positive S=0
RM Return on minus S=1
RPE Return on parity even P=1
RPO Return on parity odd P=0
RZ Return on zero Z=1
RNZ Return on no zero Z=0

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5. Stack Operations And Machine Control Instruction:

o Stack Operations:

This group consists of the following set of instructions

 PUSH rp: Push registers pair rp onto stack.

 PUSH PSW: Push processor status word onto stack
 POP rp: Pop register pair off the stack
 XTHL: Exchange top of stack with H and L.
 SPHL: H and L to stack pointer.

o Machine Control:

 NOP: No Operation
 HLT: Halt the processor

8085 Machine Cycle & Timing Diagram

To execute an instruction the 8085 needs to perform various operations such as memory
read\write and I\O read\write. All instructions are divided into a few basic machine cycles and
these machine cycles are divided into precise clock period.
Basically, the microprocessor external communication functions can be divided into three
categories.
1.) Memory read and write
2.) Input output read and write
3.) Request acknowledge
These functions are further divided into various operations (machine cycles) as shown below.

Status
Machine cycle Control signals
IO\M S1 S0
Op-code fetch 0 1 1 RD = 0
Memory Read 0 1 0 RD = 0
Memory Write 0 0 1 WR = 0
I\O Read 1 1 0 RD = 0
I\O Write 1 0 1 WR = 0
Interrupt Acknowledge 1 1 1 INTA = 0

Op-Code Fetch Machine Cycles

The first operation in any instruction is Op-code fetch. The microprocessor needs to get
(fetch) this machine cycle code from the memory register where it is stored before the
microprocessor can begin to execute the instruction. Therefore the Opcode fetch cycle
constitutes the first machine cycle of an instruction cycle, i.e. M1. This Opcode fetch cycle
begins from T-state T1 by placing the content of program counter on address bus and continues
till the Opcode decoding and execution process.

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For example to fetch the byte, the processor needs to identify the memory location 2005H
and enable the data flow from memory. The data flow is shown in figure and the timing diagram
is also shown below.
Data Bus

4F

Internal Data Bus

Memory
B C
A 2000
Instruction D E
L Decoder H L
U Stack
Pointer
2004
Program 4F 2005
counter
Control
Logic Address Bus

RD
4F
Fig: Data Flow from memory to MPU

T1 T2 T3 T4

A15 - A8

Low order
AD 7 - AD 0 05H 4FH Opcode
mem. address

ALE

IO \ M

Status IO\ M = 0, S0 = 1, S1 =1 Opcode fetch

RD

Fig: Timing Diagram for Opcode Fetch

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To fetch a byte, the processor performs the following steps:

Step 1: The program counter places the 16-bit memory address on the address bus.
Step 2: The control unit sends the control signal RD to enable the memory chip.
Step 3: The byte from the memory location is placed on the data bus.
Step 4: The byte is placed in the instruction decoder of the microprocessor and the task is
carried out according to the instruction.
Note:
 The crossover of the lines indicates that a new byte (information) is placed on the bus.
 The dashed straight line indicates the high impedance state.

Memory Read Machine Cycles

A memory read cycle is a process of transferring a byte from memory to the microprocessor.
To read a data from memory, microprocessor needs to identify and enable the memory cell. For
this purpose microprocessor places the address of memory cell on address bus and issues
different control signal from control unit.
The MPU performs the following steps to read the data from memory. Suppose the memory
read cycle need to perform to read the data byte 32h stored in memory location 2000h.

Step 1: The microprocessor places the content of program counter on the address bus. In our
case, it is 2000h. The lower address byte ‘00’ is latched with the help of ALE signal. If it is
not latched, the lower address byte will disappear or lost when microprocessor places the
data in data bus.

Step 2: The address decoding unit decodes the address bits and find out the desired memory
cell.

Step 3: The control unit sends the control signal RD to enable the memory. The status signal
IO/M goes low to indicate that it is memory related operations. The next two status signals
go high and low respectively to indicate that it is read operation.

Step 4: The data byte from memory location 2000h is placed on the data bus and transfer to
the microprocessor.

To illustrate the memory read machine cycle, we need to examine the execution of a 2 byte
or 3 byte instruction because in a 1 byte instruction the machine code is an Op-code fetch. Let us
illustrate with an example:

Memory Location Machine Code Instruction

2000H 3EH MVI A, 32H; Load 32H in
2001H 32H accumulator

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M 1 (Opcode Fetch) M2 (Memory Read)

T1 T2 T3 T4 T1 T2 T3

Clock

A 15 - A 8 20H High Order Unspecified High Order

mem. address 20H mem. address

Low order Low order

AD7 - AD0 00H 3EH Opcode 01H 3 2 H Opcode
mem. address mem. address

A LE

IO \ M
S1 , S 0 Status IO \ M = 0, S 0 = 1, S 1 =1 Opcode fetch IO \ M = 0 , S0 = 0, S 1= 1 Status

RD

Fig: Timing Diagram for MVI A 32 h

Memory Write Machine Cycles

To write into a register, the microprocessor performs similar steps as it reads from a register.
The following example shows the memory write cycle with an example of STA instruction. In
the write operation, the 8085 places the address & data and asserts the IO/M signal. After
allowing sufficient time for data to become stable, it asserts the write (WR) signal. The IO/M
and WR signals can be combined to generate the MEMW control signal that enables the input
buffer of the memory chip and stores the byte in the selected memory register.

Timing Diagram for STA Instruction

Memory Address Machine Code Mnemonics Comment

2050H 32 STA 8000H
Store Contents of Accumulator in
2051H 00 -
Memory Location 8000H
2052H 80 -

Here it is assumed that the instruction is stored in memory location 2050H, 2051H and
2052H. The timing diagram for instruction STA 8000H is shown below:

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I/O Read Machine Cycle

The purpose of I/O Read is to read data from input device such as keyboard and places the
data in the accumulator. To illustrate the timing diagram for I/O Read, we examine the
execution of instruction IN 84h, stored at memory location: 2065.

Timing Diagram For IN Instruction

IN Instruction: IN 8-bit address

2 Byte Instruction
M - Cycles: 3 (Op-Code Fetch + Memory Read + I\O Read)
T-States: 10

Example: IN 84H

Memory Address Machine Code Mnemonics Memory Contents

2065H DBH In 84H 2065: 1101 1011H = DBH
2066H 84H - 2066: 1000 0100H = 84H

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The timing diagram for instruction IN 84H is shown below:

M 1 (Opcode Fetch) M 2 (Memory Read) M 3 (I\ O Read)

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

A 15 - A8 20H Unspecified 20H Port address 84H

AD 7 – AD0 65H Opcode 66H 84H

Port address
84 H
Data from
input port
DBH

ALE

IO\ M

RD

MEMR

IOR

Fig: Timing Diagram of IN 84 h

Explanation:
 The First Machine Cycle (M1): Op-Code Fetch
The 8085 places the high order memory address 20H on A15 –A8 and the low order
address 50H on AD7-AD0. At the same time, ALE goes high and IO/ M goes low. The
IO\ M low indicates that it is a memory operation. At T2, the microprocessor sends the RD
control signal which is combined with IO\ M to generate the MEMR signal and the
processor fetches the instruction code D3 using the data bus and the instruction is decoded.
 The Second Machine Cycle (M2): Memory Read
In the second machine cycle, M2 (Memory Read), the 8085 places the next address
2051H on the address bus and get the device address 84H via data bus.
 The Third Machine Cycle (M3): I/O Write
In the third machine cycle, M3 (I\O Write), the 8085 places the device address 84H on the
low order (AD7 – AD0) as well as the high order (A15 – A8) address bus. The IO\ M signal
goes high to indicate that it is an I\O operation. The IOR signal is generated combining RD
and IO/M. The IOR signal enables the input port and data from input port are placed on the
data bus and transformed into the accumulator.

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Input/Output Write Machine Cycle

The purpose of I/O write is to send the content of accumulator to an O/P device such as LED
display. To illustrate the timing diagram for I/O write, we examine the execution of instruction
OUT 01h, stored in memory location: 2050as follows:

Timing Diagram For OUT Instruction

OUT Instruction: OUT 8-bit address

2 Byte Instruction
M-Cycles: 3 (Op-Code Fetch + Memory Read + I\O Write)
T-States: 10

Example: OUT 01H

Memory Address Machine Code Mnemonics Memory Contents

2050H D3 OUT 01H 2050: 1101 0011H = D3H
2051H 01 - 2051: 0000 0001H = 01H

The timing diagram for OUT 01h is shown below:

M1 (Opcode Fetch) M2 (Memory Read) M 3 (I\ O Write)

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

A 15 - A8 20H Unspecified 20H Port address 01H

AD 7 – AD0 Opcode 51H 01H Port address Accumulator

50 H D3H 01H Content

ALE

IO \ M

RD

MEMR

WR

IOW

Fig: Timing Diagram for OUT 01 h

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Explanation:
 The First Machine Cycle (M1): Op-Code Fetch
The 8085 places the high order memory address 20H on A15 –A8 and the low order
address 50H on AD7-AD0. At the same time, ALE goes high and IO/ M goes low. The
IO\ M low indicates that it is a memory related operation. At T2, the microprocessor sends
the RD control signal which is combined with IO\ M to generate the MEMR signal and
the processor fetches the instruction code D3 using the data bus and instruction is decoded.
 The Second Machine Cycle (M2): Memory Read
In the second machine cycle, M2 (Memory Read), the 8085 places the next address
2051H on the address bus and get the device address 01h via data bus.
 The Third Machine Cycle (M3): I/O Write
In the third machine cycle, M3 (I\O Write), the 8085 places the device address 01H on the
low order (AD7 – AD0) as well as the high order (A15 – A8) address bus. The IO\ M signal
goes high to indicate that it is an I\O operation. At T2, the accumulator contents are placed
on the data bus (AD7 – AD0) followed by the control signal WR . By adding the IO\ M and
WR signals, the IOW signal can be generated to enable an output device and data from
accumulator are displayed on O/P device such as LEDs.

Regular Examination: 2004 [Draw the Timing Diagram of OUT 23H Instruction]
Memory Address Machine Code Mnemonics Memory Contents
2050H D3 OUT 23H 2050: 1101 0011H = D3H
2051H 01 - 2051: 0010 0011H = 23H

M1(Opcode Fetch) M 2 (Memory Read ) M 3 (I\ O Write)

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

A 15 - A8 20H Unspecified 20H Port address 01H

AD 7 – AD0 Opcode 51H 23H Port address Accumulator

50H D3H 23H Content

ALE

IO \ M

RD

MEMR

WR

IOW

Fig: Timing Diagram of OUT 23 h

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Fetch Execution Overlap

As we know that the specified task is performed during the execution cycle i.e. at the end of
last T-state of the instruction cycle. But this may not be always true. This is just the
generalization for easier purpose.
Let’s consider the instruction MOV Rd, Rs which takes one machine cycle M1 and consists of
4 T-states as shown in following timing diagram.

MOV Rd, Rs Next Instruction

T1 T2 T3 T4 T1 T2 T3

Clock

A15 - A8 PCH Unspecified PCH

AD0 – AD7 PCL Opcode PC L Opcode

ALE

IO\ M Status IO \ M = 0, S 0 = 1, S 1 = 1 Opcode fetch IO \M = 0, S 0 = 0, S = 1 Status

1

RD

PC Out PC + 1  PC Opcode  IR Rs  TR PC Out Rd  TR

PC + 1  PC Opcode  IR

FEO

Fig: Fetch Execution Overlap

The T4, T-state is used as instruction decoding cycle and least duration of T4 is used to
perform the specified task. But for the MOV Rd, Rs instruction, at the end of T4, only the contents
of source register (Rs) is transferred to temporary register (Tr). The transferring of data from
temporary register (Tr) to destination register (Rd) is done at the T2 state of first machine cycle
next instruction. We know that the next immediate machine cycle is Op-code fetch as MOV Rd,
Rs is one byte instruction. It is clear from the timing diagram that T1 and T2 of the fetch cycle of
next instruction is used to fetch the Op-code as well as transferring of data from temporary
register to destination register of previous instruction. This is called fetch execution overlap
(FEO).

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Counters and Time Delays

Designing a counter is frequent programming application. Counters are used primarily to

keep track of events; time delays are important in setting up reasonably accurate timing between
two events. The process of designing counters and time delays using software instructions is far
more flexible and less time consuming than the design process using hardware.

Counter

A counter is designed simply by loading an appropriate number into one of the registers and
using the INR (Increment by One) or the DCR (Decrement by One) instructions. A loop is
established to update the count and each count is checked to determine whether it has reached
the final number; if not, the loop is repeated.

The flowchart shown below illustrates these steps. However, this counter has one major
drawback; the counting is performed at such high speed that only the last count can be observed.
To observe counting, there must be appropriate time delay between counts.

Initialize

Display

Update

No Is this
Final
Count?

Yes

Fig: Flowchart of a
Counter

Time Delay

The procedure used to design a specific delay is similar to that used to set up a counter. A
register is loaded with a number, depending on the time delay required, and then the register is
decremented until it reaches zero by setting up a loop with a conditional Jump instruction. The
loop causes the delay, depending upon the clock period of the system.

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Time Delay Using One Register

A count is loaded in a register and the loop is executed until the count reaches zero. An
example of set of instructions necessary to set up the loop is given below with an 8085-based
microcomputer with 2 MHz clock frequency:
Label Op-Code Operand Comments T-States
MVI C, FFH ; Load Register C 7
LOOP: DCR C ; Decrement C 4
JNZ LOOP ; Jump Back to Decrement C 10/7

Delay Calculation:
Clock Frequency of the System (f) = 2 MHz
Clock Period (T) = 1/f = 1/(2x10-6) = 0.5 s
Time to Execute MVI = 7 T-States x 0.5 = 3.5 s

To calculate the time delay in a loop, we must account for the T-states required for each instruction
and for the number of times the instructions are executed in the loop. In above example, register C is
loaded with the count FFH (25510) by the instruction MVI, which is executed once and takes seven T-
states. The next two instructions, DCR and JNZ, form a loop with a total of 14 (4+10) T-states. The loop
is repeated 255 times until register C = 0.

Now, the time delay in the loop TL with 2 MHz clock frequency is calculated as:
TL = (T x Loop T-states x N10)

Where, TL = Time Delay in the Loop

T = System Clock Period
N10 = Equivalent Decimal Number of the Hexadecimal Count Loaded in the Delay Register.

 TL = (0.5 x 10-6 x 14 x 255)

= 1785 s
= 1.8 ms

Note: The T-states for JNZ instruction are shown as 10/7. This is why the 8085 microprocessor requires
10 T-states to execute a conditional Jump instruction when it jumps or changes the sequence of the
program and 7 T-states when the program falls through the loop (goes to the instruction following the
JNZ). This difference can be accounted for the delay calculation by subtraction the execution time of
three states. There for, adjusted loop delay is:
TLA = TL – (3 T-states x Clock Period)
= 1785 s – 1.5 s
= 1783.5 s
Now the total delay must take into account the execution time of the instructions outside the loop. In the
above example, we have only one instruction (MVI C) outside the loop. Therefore, the total delay is:
Total Delay = Time to Execute Instructions Outside Loop + Time to Execute Loop Instructions
TD = TO + TLA
= (7 x 0.5) + 1783.5 = 1787 s
= 1.8 ms

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Time Delay Using Register Pair

The time delay can be considerably increased by setting a loop and using a register pair with
a 16-bit number (maximum FFFFH). The 16-bit number is decremented by using the instruction
DCX. However, the instruction DCX does not set the Zero Flag and without the test flags, Jump
instructions cannot check desired data conditions. Additional techniques, therefore, must be
used to set the Zero Flag.
The following set of instructions uses a register pair to set up a time delay.
Label Op-Code Operand Comments T-States
LXI B, 2384H ; Load BC with 16-bit count 10
LOOP: DCX B ; Decrement BC by one 6
MOV A,C ; Place Contents of C in A 4
ORA B ; OR (B) with (C) to Set zero Flag 4
JNZ LOOP ; If result = 0, Jump Back to LOOP 10/7

Delay Calculation:
The loop includes four instructions: DCX, MOV, ORA and JNZ and takes 24 clock periods for
execution. The loop is repeated 2384H times, which is converted to decimal as:
2384H = 2 x (16)3 + 3 x (16)2 + 8 x (16)1 + 4 x (16)0
= 909210
If the clock period of the system = 0.5 s, the delay in the loop T is:
TL = (0.5 x 24 x 909210)
= 109 ms (without adjusting for the last cycle)

Total Delay (TD) = 109 ms + TO

= 109 ms (The instruction LXI adds only 5 s)

Time Delay Using a Loop within a Loop Technique

A time delay similar to that of a register pair can also be achieved by using two loops; one
loop inside the other loop as shown in example below.
Label Op-Code Operand T-States
MVI B, 38H 7
LOOP2: MVI C, FFH 7
LOOP1: DCR C 4
JNZ LOOP1 10/7
DCR B 4
JNZ LOOP2 10/7

Delay Calculation:
The delay in LOOP1 is TL1 = 1783.5 s as per the previous calculation. Now the calculation for the
delay in LOOP2 is as follows:
TL2 = 56(TL1 + 21 T-states x 0.5 s)
= 56 (1783.5 s + 10.5 s)
= 100.46 ms

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Assembly Language Programming

Contents:

o Computer Programs & Programming Languages

o Types or Levels of Programming Languages
o Compiler & Interpreter
o Assembly Language Programming
o Assembler Instruction Format
o Assembler & Its Types
o Assembler Directives
o Sample Assembly Language Program

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Computer Program & Programming Languages: A Review

Computer program is a set of instructions that, when executed, causes the computer to
behave in a predetermined manner. Without programs, computers are useless and can do
nothing. Most people are confused that computers are intelligent devices and can do anything;
but this concept is wrong. Computer can do anything, but only after it has appropriate
program(s). Without programs, it can not even add two numbers.

Computer cannot understand human natural languages like English or Nepali. To instruct a
computer to perform a certain job, we need languages which can be understood by the
computer. The languages which are used to instruct the computer to do certain jobs are called
“Computer Programming Languages”. There are many programming languages like C, C++,
Pascal, BASIC, FORTRAN, COBOL, LISP, etc.

Types or Levels of Programming Languages

There are mainly two types of programming languages – High-Level Programming
Languages & Low-Level Programming Languages. Low-level languages are closer to the
hardware than high-level programming languages.

Programming
uag

Low-level High-level

Machine-level Assembly-level

Low-Level Language

Low-level language is a programming language in which each statement or instruction is

directly translated into a single machine code. It is machine dependent, i.e. a particular low-level
language works only for a certain machine.

Machine-level Language
Machine language is a language that a computer actually understands. The least possible
level at which we can program a computer is in its own native machine code, consisting of
strings of 1's and 0's, and are stored as binary numbers. Thus, machine language is a
sequence of instructions written in the form of binary numbers consisting of 1’s and 0’s to
which the computer responds directly. The main advantage of machine languages is that
they execute fast as the computer understands them and doesn’t need translation into other
forms. However, machine languages are difficult to write.

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Example: To add two numbers 3 and 6 in machine language, program may be like –

11 10111001 110
3 machine code for addition (say) 6

There are many different instruction sets (machine codes) for each operation. It is
difficult to remember them for programming.

Advantages of Machine Language

The CPU directly understands machine instructions, and hence no translation is required.
Therefore, the computer directly starts executing the machine language instructions, and it
takes less execution time.

Disadvantages of Machine Languages

Difficult to use: As computer instructions are written in binary forms, it is hard to write,
understand, and debug.
Machine dependent: The code written for one processor may be incompatible for other.
The programmer has to remember machine characteristics while developing a program.
As the internal design of the computer is different across types, which in turn is
determined by the actual design or construction of the ALU, Control Unit and size of the
word length of the memory unit, the machine language also varies from one type of
computer to another.
Difficult to debug and modify: Checking machine instructions to determine errors are
about as tedious as writing the instructions. It is difficult to modify the program.

Assembly Language
Assembly language is a symbolic representation (called mnemonics) of machine code.
They are close to machine code but the computer cannot understand them. The assembly-
language program must be translated into machine code by a separate program called an
assembler. The assembler program recognizes the character strings that make up the
symbolic names of the various machine operations, and substitutes the required machine
code for each instruction. The above program for addition two numbers in assembly
language may look like –
11 ADD 110  Suppose ADD is mnemonic for addition
Some of the examples of instructions for assembly language are as follows:
Code Meaning
ADD Addition
SUB Subtraction
INR Increase
DCR Decrease
CMP Compare
It is relatively easy for writing programs in assembly languages, but is slow in execution
as it has to be converted into machine language before execution.

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Advantages of Assembly Language

Writing a program in assembly language is more convenient than writing one in machine
language. Instead of binary sequence, as in machine language, a program in assembly
language is written in the form of symbolic instructions. This gives the assembly language
program improved readability. Again, it is useful writing program in embedded system
because it needs fewer codes than high level language. It is also used for device
programming.

Disadvantages of Assembly Language

Hard to remember mnemonics: There are large numbers of mnemonics for a machine. It
is difficult to remember all the mnemonics for writing assembly program
Machine dependent: Assembly language is specific to particular machine architecture.
Thus, assembly language programs written for one processor will not work on a different
processor if it is architecturally different.
Less efficient than machine language: The assembly language is to be translated into
machine language before execution. Thus, a program written in assembly language is
less efficient compared to an equivalent machine language program but more efficient
than equivalent high level language program.

High Level Language

A high-level programming language is a programming language that is more user-friendly,

to some extent platform-independent and abstracts from low-level computer processor
operations such as memory accesses. They are similar to natural languages (like English) and so
are easy to write and remember. They are easy to learn and work but while executing, they have
to be translated into assembly language and then to machine language. So it is slow in execution
but is efficient for developing programs. C, C++, Java, VB, & VB.net are known as high level
languages.

Advantages of High Level Language

Easy to use: The statements in high level language are much more like English language.
Thus, they are easier to understand than those written in assembly and machine
language.
Portability: High level programming languages can be run on different machines with
little or no change. It is, therefore, possible to exchange software, leading to creation of
program libraries.
Easy Debugging: Errors can be easily detected and removed.
Easy and Fast development of software: Since the commands of these languages are
closer to the English language, software can be developed with ease and speed.

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Disadvantages of machine language

More execution time: As the program written in high level language can not directly
generate executable code, it has to be translated into assembly language and then to
machine language. Thus, it takes more time for execution.
Needs own translator: Each language has its own translator to change high level language
program into machine language

Compiler & Interpreter

High level source program must be translated first into a form the machine can understand.
This is done by the software called compiler. The compiler takes the source code as input and
produces the machine language code (object code) for the machine on which it is to be executed
as output. During the process of translation, the compiler reads the source programs statement-
wise and checks for syntax errors. In case of any error, the computer generates message about
the error. Examples: C, C++, Java, FORTRAN, Pascal etc
An interpreter, like compiler, is also translator which translates high level language into a
machine level language. The difference between compiler and interpreter is their working
principle. The interpreter translates and executes the program line by line. Each time the
program is executed; every line is checked for syntax error and then converted to the equivalent
machine code. Examples: QBASIC, PERL, PHP, ASP

Compiler Vs Interpreter
Compiler Interpreter
1) Compiler scans the entire program 1) Interpreter translates and executes the
before translating it into machine code. program line by line.
2) Syntax errors are found only after the 2) Syntax errors can be trapped after
compilation of complete program. translation of every line.
3) It takes less execution time 3) It takes more execution time

Assembly Language Programming

Programs in assembly language are represented by instructions that use English Language
Type commands called mnemonics. It is more convenient to write the programs in assembly than
in machine language. However a translator (assembler) must be used to convert the assembly
language programs into binary machine language programs (object codes) so that the processor
can execute them.
An assembly language program written for one microprocessor is not transferable to a
computer with another microprocessor unless the tow microprocessors are compatible in their
machine codes.

Example: The binary code 0011 1100 of the 8085 microprocessor is represented by the
mnemonic INR A, which suggests the operation of incrementing the accumulator contents by
one.

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Tools for Developing Assembly Language Programs

The program development utilities enable the user to write, assemble and test assembly
language programs; they include programs such as Editor, Assembler, Linker (or Loader) and
Debugger. These utility programs enable the user to perform such functions as copying, printing,
deleting and renaming files. Therefore they are necessary to develop assembly language
programs.

Editor:
The editor is a program that allows the user to enter, modify and store a group of
instructions or text under a file name. The editor programs can be classified in two groups:
line editors and full-screen editors. Line editors, such as EDIT in MS-DOS, work with and
manage one line at a time. Full screen editors (also known as word processor), such as MS
Word and WordPerfect, manage the full screen or a paragraph at a time. To write text, the
use must call the Editor under control of the operating system. The exit command of the
Editor program will save the program on the disk under the file name and will transfer the
program control to the operation system.

Assembler:
The assembler is a program that translates source code or mnemonics into the binary
code, called object code, of the microprocessor and generates a file called the object file.
This function is similar to manual assembly, whereby the user looks up the code for each
mnemonic in the listing. The translation requires that the source program be written strictly
according to the specified syntax of the assembler. The assembly language source program
includes three types of statements, they are:

- The program statement in 8085 mnemonics that are to be translated into binary code.
- Comments that are reproduced as part of the program documentation.
- Directives to the assembler that specify items such as starting memory locations, label,
definitions and required memory spaces for data

Assembly Machine Executable

Language Language File
(Source Code) (Object Code) *.EXE or
.ASM .OBJ *.COM

Fig: Process of Compilation and Linking Assembly Language

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An assembler is a tool for developing assembly language program. In addition to

translating mnemonics, the assembler performs various functions as given below:

- Translates mnemonics into binary code with speed and accuracy, thus elimination
human errors in looking up the codes.
- Assigns appropriate values to the symbols used in program. This facilitates specifying
jump locations.
- Easy to insert or delete instructions in a program; the assembler can reassemble the
entire program quickly with new memory locations and modified addresses for jump
locations. This avoids rewriting the program manually.
- Checks syntax errors, such as wrong labels and expressions, and provides error
messages. However it cannot check logic errors in a program.
- Reserve memory locations for data or results.
- Provide files for documentation.
- A debugger program can be used in conjunction with the assembler to test and debug an
assembly language program.

Loader (Linker):
The loader is a program that takes the object file generated by the assembler program
and generates a file in binary code called the COM file or the EXE file. The COM or EXE
file is the only executable file i.e.; the only file that can be executed by the microcomputer.
To execute the program, the COM file is called under the control of the operating system
and executed. In different assemblers, the COM file may be labeled by other names.

Debugger:
The Debugger is a program that allows the user to test and debug the object file. The
user can employ this program to perform the following functions:
- Make changes in the object code.
- Examine and modify the contents of memory.
- Set breakpoints, execute a segment of the program and display register contents after the
execution.
- Trace the execution of the specified segment of the program and display the register and
memory contents after the execution of each instruction.
- Disassemble a section of the program i.e. convert the object code into the source code or
mnemonics.

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Assembler Instruction Format

Microprocessors recognize and operate in binary numbers. However, each microprocessor

has its own binary words, meanings and language. The words are formed by combining a
number of bits for a given machine. The basic terms related to computer language are explained
shortly below.
o Word (Word Length): The word (or word length) is defined as the number of bits the
microprocessor recognizes and processes at a time. The word length ranges from 4-bits
for a small microprocessor based systems to 64 bits for high speed large computers.
o Byte: A byte is defined as a group of 8-bits. For example a 16-bit microprocessor has
word length equal to 2 byte. One byte constitutes one character.
o Nibble: The term nibble is defined as a group of 4-bits. A byte has two nibbles
Each machine has its own set of instructions based on the design of its CPU or of its
microprocessor. To communicate with the computer, one must give instructions in binary sets of
0s and 1s.
o Op Code: An instruction is a command to the microprocessor to perform the given task.
It consists of task to be performed by the microprocessor called the operation code (Op-
code). Thus the Op-code field specifies how data is to be manipulated.
o Operand: Instruction also contains the data to be operated on which is called operand.
The operand (or data) may be 8-bit (or 16-bit) data, an internal register, a memory
location or an 8-bit (or 16-bit) address. In some instruction the operand is implicit.
o Mnemonics: Each microprocessor has a fixed set of instructions in the form of binary
patterns called a machine language. However it is difficult for human beings to
communicate in the language of 0’s and 1’s. Therefore, the binary instructions are given
abbreviated names, called mnemonics, which forms the assembly language for a given
microprocessor.

A typical assembly language programming statement is divided into four parts called fields:
Label, Operation Code (Op code), Operand and Comments. These fields are separated by
delimiters as shown in table below:

Delimiter Placement
1. Colon After label (Optional)
2. Space Between an op code and operand
3. Comma Between two operands
4. Semicolon Before the beginning of a comment

As an example, a typical assembly language statement is written as follows:

Label Opcode Operand Comments

START: LXI SP, 20FFH ;Initialize Stack Pointer

In above sample assembly language program delimiters include the colon following START,
the space following LXI, the comma following SP, and the semicolon preceding the comments.

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Types of Assembler

One Pass & Two Pass Assembler

One Pass Assembler goes through the assembly language program once and translates the
assembly language program. This assembler has the program of defining forward references.
This means that a JUMP instruction using an address that appears later in the program must
be defined by the programmer after the program is assembled.

Two Pass Assembler scans the assembly language program twice. In the first pass the
assembler generates the table of the symbols. A symbol table consists of labels with
addresses assigned to them. In this way labels can be used for JUMP statements and no
address calculation here to be done by the user. On the second pass, the assembler translates
the assembly language program into the machine code. The two pass assembler is hence
more efficient and easier to use.

One Pass Assembler Two Pass Assembler

1. An assembler which goes through an 1. An assembler which goes through an
assembly language program only once assembly language program twice to
and produces its object code is known as produce object code is known as two
one pass assembler. pass assembler.
2. In assembly language program, labels 2. In the first pass, the assembler
are used to point forward and backward generates the symbol table consisting of
references. Since the one pass assembler labels with address assigned to it.
goes through an assembly language In second pass, the assembler
program once, such an assembler must translates the assembly language
have some means to take forward program into object \ machine code
reference into consideration. using the symbol table.
3. Difficult to use hence undesirable. 3. Easier to use, hence desirable.

Cross Assembler

This type of assembler is typically resident on the processor and assembles programs for
another for which it is written. The cross assembler program is written in a high level
language so that it can run on different types of processor that understands the same high
level language.

For example, the 8085 cross-assembler from 2500AD Software Inc. has two programs:
one is as assembler named X8085 and the other is a linker with the file name LINK. After
assembling a program, the HEX file can be directly transferred to R/W memory of 8085
single-board microcomputer by using a Download Program. Thus programs and/or
hardware-related laboratory experiments can be easily performed. An assembly language
program using cross-assembler has following steps of operations:

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 Call an Editor (Such as EDIT in MS-DOS & WordPerfect or MS-Word in Windows) and
write an assembly language program in 8085 mnemonics. This is called source file.

 Call a Cross-Assembler (Such as X8085) and assemble the source file. The X8085
generates an intermediate binary file called an object file and provides a list of errors.
Reassembling the program would give a message of zero errors. The cross assembler
also generates a list file that includes memory address, machine codes in HEX, Labels
and Comments. This file is used primarily for documentation.

 Call a Link program and use the intermediate binary file (Object Code) to generate either
an Executable file or HEX file.

 Execute the program on the single-board machine.

After the end of the assembly process, we will have the following files on our PC disk.

 ASM File: This is the source file written by the user using an Editor. The filename can be
one to eight characters long with an extension of a maximum of three characters. The
filename and the extension are separated by a dot, e.g. Microprocessor.ASM, the
extension ASM suggests that this is an assembly language file.

 OBJ File: This is the intermediate binary file generated by the Cross-Assembler.

 LST File: This is the list file generated by the Assembler Program for documentation
purposes. It contains memory locations, hex code, mnemonics and comments.

 HEX File: This is generated by the Link Program and contains program code in
hexadecimal notations. This file can be used for debugging the program and to transfer
files from one system to another.

 COM File: This is the executable file generated by the Link Program, and it contains
binary code. However, this file cannot be executed on the PC. This type of a file can be
executed if it has to write an assembly language program for the microprocessor in the
PC. However, in such a situation cross-assembler will be not in use. We have to use the
assembler for the PC microprocessor.

Resident Assembler

This type of assembler assembles programs for a processor in which it is resident. The
resident assembler may slow down the operation of processor on which it runs.

Meta Assembler

This type of assembler can assemble programs for many different types of processors.
The programmer usually defines the particular processor being used.

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Macro Assembler

Macro assembler is a type of assembler that translates a program written in micro

language into the machine language. A macro language is the one in which all the
instruction sequence can be defined using macros. A macro is an instruction sequence that
appears repeatedly in program assigned with a specific name.

Macro assembler lets the programmer define all instruction sequence using macros. By
using macros, the programmer can assign a name to an instruction sequence that appears
repeatedly in a program. The programmer can thus avoid writing an instruction sequence
that is required many times in a program by using macros. The macro assembler replaces a
macro name with the appropriate instruction sequence each time it encounters a macro
name.

As in subroutine program, there is no need to use CALL and RET instruction to execute
and to resume program. A macro does not cause the program execution to branch out of the
main program. Each time a macro occurs, it is replaced with the appropriate instruction
sequence in the main program. Typical advantages of using macros are shorter source
program and better program documentation.

Conditional macro assembly is very useful in determining whether or not an instruction

sequence shall be included in the assembly depending on a condition that is true or false. If
two different programs are to be executed repeatedly based on a condition that can be either
true or false, it is convenient to use conditional macros. Based on each condition, a
particular program is assembled.

For example consider a sequence of instruction such as:

IN AX, PORT
ADD AX, BX
OUT PORT, AX

If above sequence of instructions are grouped and assigned a specific name ‘Addition’
(called macro name ‘Addition’), the whole macro becomes:

Addition {
IN AX, PORT
ADD AX, BX
OUT PORT, AX
}

When above instruction sequence is to be executed repeatedly macro assemblers allow

the macro name only to be typed instead of all instructions provided the macro is defined.

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Assembler Directives
Assembler directives are the instructions to the assembler concerning the program being
assembled. They are also called pseudo instructions or pseudo codes. They are neither translated
into machine code nor assigned any memory location. They just provide the direction to the
assembler.

It performs the operations such as:

 Telling the assembler to place the segment in standard order.

 Indicating starting and ending of procedures.
 Indicating ending of entire program.
 Selecting the size of segments.

Some of the important assembler directives are:

1. Data Definition Directives

Data definition directive creates storage for data. There are various types of data
definition directives summarized below.

 DB- Define Byte (1 Byte): The DB directive creates storage for a byte or group of bytes in
memory. It is used to declare a byte type variable.
Example: Count DB? (Initialization)
Data 1 DB 10H
List DB 10H, 20H, 30H

 DW-Define Word (2 byte): The DW directive creates storage for a word or list of words.
It is used to declare a word type variable.
Example: Data 1 DW 1234H
List DW 1234H, 6678H, 7981H

 DD- Define Double Word (4 byte): The DD directive creates storage for 32 bits double
word variable. It is used to declare double word type variable.
Example: Data 1 DD 12345678H

 DQ- Define Quad Word (8-byte): DQ directive creates storage for 8 byte or group of 8
bytes. It is use to declare quad word type variable.
Example: Data1 DQ 123456789123456H.

 DT-Define Ten Bytes: DT directive creates storage for ten bytes. It is used to declare ten
byte type variable.
Example: List DT 123456789A1234564455H

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2. DUP-Directive (Duplicate)
The DUP directive can be used to initialize several locations to zero. For example the
statement START DW 4DUP (0) reserves four words starting at the offset START in DS and
initializes them to zero. The DUP directive can also be used to reserve several locations that
need not be initialized. A question mark should used with DUP in this case. For example the
statement BEGIN DB100 DUP (?) reserves 100 bytes of uninitialized data space to an offset
BEGIN in DS.

3. EQU-Directive (Equate)
The EQU directive is used to give a name to some value or symbol. Each time the
assembler finds the given name in the program, it will replace the name with the value or
symbol equated with that name. Example count EQU 10H.

4. ORG-Directive (Origin)
The ORG directive allows setting location counter to desired value. For example ORG
200H tells assembler to set location counter to 2000H.

5. ASSUME-Directive
The ASSUME directive tells the assembler what names have been used for used for the
code, data, extra and stack segment. It identifies the segment name used for code, data and
stack segment. Example: ASSUME CS: CODE, DS: DATA, SS: STACK.

6. MODEL-Directive
The MODEL directive selects standard memory model for the program. It determines the
way segments are linked together as well as maximum size of each segment.
Model Description
Tiny Code and Data segment together may not be greater than 64K
Small Neither Code or data may be greater than 64K
Medium Only the code may be greater than 64K.
Compact Only the data may be greater than 64K.
Large Both code and data may be greater than 64K.
Huge All available memory may be used for code and data.

7. Program Segment-Directive
The program segment directives are:
 .STACK: The stack directive sets the size of the program stack which may be any size up
to 64K. The stack segment is addressed by SS and SP registers.
 .CODE: The code directive identifies the part of the program that contains the
declaration and initialization of all variables. This segment is addressed by DS and all
other register except IP, SP and BP.
 .DATA: The data directive identifies the start of the data segment.
 .DOSSEG: The DOSSEG segment tells the assembler to place the segments in order
basically code, data and stack.

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8. Procedure-Directive

A procedure is the group of related program instructions with common function or task.
 PROC Directive: It is used to identify the start of the procedure.
 ENDP Directive: It indicates the end of the procedure.
 ENDS Directive: It indicates the end of the segment.
 END Directive: The end directive terminates the assembly language program and is
placed at the end of the program. Any instruction after this is ignored.

Sample Assembly Language Program for 8086 Microprocessor

The sample program given below, when assembled and executed, exchanges the contents of
two variables. The following source program is created using a text editor.

TITLE: Exchange of Two Variables

DOSSEG
.MODEL SMALL
.STACK 100H
.CODE

Main PROC
MOV AX, @Data ; Initialize DS Register
MOV DS, AX

SWAP;
MOV AL, Value1 ; Load the AL Register
XCHG Value2, AL ; Exchange AL and Value2
MOV Value1, AL ; Move AL back into value1
INT 21h

Main ENDP
.Data
Value1 DB 0Ah
Value2 DB 14h
END Main

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Program Instruction

The first two instructions in the sample program initialize the data segment (DS) register.

MOV AX, @ Data

MOV DS, AX

The name @ Data is a standard MASM identifier that stands for the location of the data
segment. By setting DS equal to the start of the data segment, we make it possible for MASM to
locate variables correctly. The next three instructions exchange the contents of value1 and
value2.

MOV AL, Value1

XCHG Value2, AL
MOV Value1, AL

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Bus Structure & Memory Devices

Contents:

o Bus Structure
o Memory & Its Types
o Memory Interfacing
o Address Decoding

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Bus Structures

A microprocessor unit basically performs four operations; memory read, memory write, I\O
read and I\O write. These operations are part of communication between MPU and peripheral
devices.
A communication includes identifying peripheral or memory location, transfer of data and
control functions. These are carried out using address bus, data bus and control bus respectively.
All the buses together are called the system bus.

Data Bus
The data bus provides a path for data flow between system modules. It consists of a
number of a separate line generally 8, 16, 32 or 64. The number of lines is referred as width
of the data bus. A single line can only carry one bit at a time, thus the number of lines
determines how many bits can be transmitted at a time. The width of the data bus is a key
factor in determining the overall systems performance.

 Asynchronous Data Bus

In an Asynchronous data bus the timing is maintained in such that occurrence of one
event on the bus follows and depends on the occurrence of previous events.
Let us consider an example of simple memory read operation for an Asynchronous
bus where the events occur as follows.
o The CPU places the memory read and address signals on the bus.
o After allowing for these two signals to stabilize Master Synchronous Signal
(MSYNC) to indicate the presence of valid address and control signals on the bus.
o The addressed memory module responds with the data and the Slave Synchronous
(SSYNC) signal.
Thus at a certain time it cannot be identified when there is data or an address on the bus.

Read

Address

MSYNC

Data Bus

SSYNC

Fig: Asynchronous Bus

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 Synchronous Data Bus

A synchronous bus has its events tied by a clock. The clock transmits a regular
sequence of a 0’s and 1’s of equal duration. A single 1-0 transmission is called clock
cycle or bus cycle. All other devices work with the clock cycle. The events start at the
beginning of the clock cycle. A memory read in case of synchronous bus progresses as
follows:
o The CPU issues a start signal to indicate the presence of address and control
information on the bus.
o Then it issues the memory read signal and places the memory address on the
address bus.
o The addressed memory module recognizes the address and after a delay of one
clock cycle it places the data and acknowledgement signals on the buses.
In a synchronous bus all the devices are tied to a fixed rate.

Clock

Start

Read

Address

Data Bus

Acknowledge Signal

Fig: Synchronous Bus

Address Bus
The address bus is used to designate the source and destination of data in data bus. In a
computer system, each peripheral or memory location is identified by a binary number
called address.

The width of the address bus determines the maximum possible memory capacity of the
system. The address bus is used to address I\O ports. Usually higher order bits are used to
select particular modules and lower order bit is used to select a memory location or I\O port
within a module.

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Control Bus
The control bus is a group of lines used to control the data address bus. Since the bus is
shared by all the components of the microcomputer system there must be some control
mechanism to distinguish between data and address. The timing signals indicate the validity
of data and address information while command signal specify operations to be performed.
Some of the control signals are:
o Memory Write
o Memory Read
o I\O Read
o I\O Write
o ALE
o Interrupt Request
o Interrupt Acknowledge

Memory & Its Types

Memory is a collection of cells capable of storing binary information. In addition to these
cells, memory contains electronic circuits for storing and retrieving the information. Memory is
used in many different parts of a modern computer, providing temporary or permanent storage
for substantial amount of binary information. Memory locations are identified by an address.
The address bus of a microprocessor defines the maximum amount of memory a microprocessor
can address.
Microcomputer memory is categorized as:
o Processor Memory
o Primary or Main Memory
o Secondary Memory

Processor Memory
Processor memory is a group of register along with processor. They temporarily hold the
data during computation since processor and register are fabricated with same technology
and they have same speed.
Separate memory is kept alongside the processor to keep the most frequently needed
information. This memory is known as cache memory.

Primary Memory
This is the memory the microprocessor uses in executing and storing programs. Usually
the size of the primary memory is larger and speed is slower than the processor memory.
Primary memory can be categorized as:
o Random Access Memory (RAM)
o Read Only Memory (ROM)

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Random Access Memory

A random access memory (RAM) is a collection of binary storage cells together with
associated circuits needed to transfer information into and out of the cells configurations
used in such a way that memory cells can be accessed to transfer information to or from
any desired location with the access taking the same time regardless of location.
Thus RAM is read\write memory in which data can be written into and read from any
selected address in any sequence. A RAM is typically used for short term data storage
because it cannot retain stored data when power is turned off.

Properties of RAM
 Integrated circuit RAM may be either static or dynamic
 Stores binary information in the form of electric charges on capacitors.
 Data can be accessed randomly.
 Read and write operation can be performed.
 Volatile; lose stored information when power is turned off.

Types of RAM
There are two types of RAM
o Static Random Access Memory (SRAM)
o Dynamic Random Access Memory (DRAM)

Static Ram (SRAM)

SRAM consists of internal flip-flops and latches as a storage element that stores
binary information as long as dc power is applied. It stores bit as a voltage. Each
memory cell requires six transistor, they have low packaging density but high speed
and consume more power. SRAM is easier to use and has shorter read and write
cycles.
Dynamic Ram (DRAM)
DRAM consists of capacitors as a storage element and cannot retain data very
long without the capacitor being recharged by a process called refreshing. This is
done by cycling through words every few milliseconds, reading them and rewriting
them. DRAM offers reduced power consumption and large storage capacity. The
disadvantage is that the storage capacitor cannot hold its charge over an extended
period of time and will lose the stored data bit unless its charge is refreshed
periodically.

Read Only Memory

A read only memory (ROM) is a programmable logic device which contains
permanently or semi permanently stored data which can be read from memory but either
cannot be changed at all or cannot be changed without specialized equipment. The
information must be specified by the designer and is them embedded into the ROM to
form the required interconnection or electronic device pattern. A ROM stores data that
are used repeatedly in system application and operation. ROM’s retain stored data when
the power is off and therefore non volatile memories.

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Types of RAM
The different types of ROM are described below:
o The Masked ROM
o Programmable ROM (PROM)
o Erasable PROM (EPROM)
 Ultraviolet Erasable PROM
 Electrically Erasable PROM

The Masked ROM

The mask ROM is permanently programmed during the manufacturing process to
provide widely used standard functions, such as popular conversions or to provide user
defined functions. Once the memory is programmed it cannot be changed. Generally
manufacturers use this process to produce ROM in large numbers.

Programmable ROM
These are unprogrammed ROM. A PROM uses some type of fusing process to store
bits, in which a memory link is burn open or left intact to represent a 0 or a 1. The fusing
process is irreversible, once a PROM is programmed, it cannot be changed.

Erasable PROM
An EPROM is an erasable PROM. An EPROM can be reprogrammed if an existing
program in the memory array is erased first.
The basic types of erasable PROM are ultraviolet erasable PROM (UVEPROM) and
the electrically erasable PROM (EEPROM).

Ultraviolet Erasable PROM

In UVEPROM, the programming process causes electrons to be removed from
the floating gate. Erasure is done by exposure of the memory array chip to high
intensity ultra violet radiation through the quartz window on top of the package. The
positive charge stored on the gate is neutralized after several minutes to an hour of
exposure time. The UVEPROM is programmed by inserting the chip into a socket of
the PROM programmer and providing addresses. The programming time varies from
1-2 minutes.

Electrically Erasable PROM

EEPROM, an electrically erasable PROM can be both erased and programmed
with electrical pulses. Since it can be both electrically written into and electrically
erased, the EEPROM can be rapidly programmed and erased in circuits for
reprogramming.

Secondary Memory
Secondary memories are storage devices. These device have high data holding capacity
and can hold huge programs such as compilers and data based management system that are
not needed by the processor frequently. They are slow and have larger size. The secondary
memories are also referred to as auxiliary or back up storage.

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Differences

DRAM SRAM
1. DRAM stores a data bit in a small 1. SRAM uses flip-flops as a storage
capacitor. element.
2. DRAM cannot retain data very long
2. Data can be stored indefinitely as long
without the capacitors being refreshed by a
as dc power is applied.
process called refreshing.
3. Data can be read much faster from
3. Data access time is greater than SRAM.
SRAM’s.
4. DRAM can store much more data for a 4. SRAM can store less data than DRAM
given size and cost. for a give physical size and cost.
5. Data is kept as a charge. 5. Data is kept as a voltage.
6. It has high density. 6. It has low density.
RAM ROM
1. RAM is a type of memory in which all
1. ROM is a type of memory in which
addresses are accessible in an equal amount
data are stored permanently or semi
of time and can be selected in any order for
permanently.
read and write operation.
2. ROM stores data that are repeatedly in
2. A RAM stores currently used data.
used system applications.
3. A RAM has both read and writes 3. Data can be read from a ROM, but there
capability. is no write operation.
4. RAM, lose stored data when power is 4. Non volatile; data is not loosed even if
turned off so they are volatile. power is turned off.
Primary Storage Secondary Storage
1. This is the memory the microprocessor 1. This is the memory which stores all the
uses in executing and storing program. data and programs.
2. Smaller in size so holds the data and 2. Larger in size and hence holds larger
programs currently in use. data files and huge programs.
3. The microprocessor cannot directly
3. The microprocessor can directly
execute or process program stored in this
communicate with primary storage.
memory.
4. It has to communicate with
4. It has low speed and thus it is cheaper
microprocessor that has high speed and is
than primary memory.
expensive.
5. Generally volatile; data cannot be 5. Non volatile; data can be retained even
retained when power is turned off. after power is turned off.
Magnetic disk and tapes are secondary
6. RAM and ROM are primary storage.
storage.

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Memory Interfacing

Memory is an essential component of a microcomputer system; it stores binary instructions

and data for the microprocessor. To communicate with memory, the MPU should be able to
o Select the chip,
o Identify the register, and
o Read from or write into the register.
In a memory chip, all registers are arranged in a sequence and identified by binary
numbers called memory address. Each register has a group of flip-flops or field-effect
transistors that store bits of information; these flip-flops are called memory cells. The
number of bits stored in a register is called a memory word.
The MPU uses its address bus to send the address of a memory register and uses the data
bus and control lines to read from or write into that register.

Requirement of Memory Chip

o A memory chip requires address lines to identify a memory register. The number of
address lines required is determined by the number of registers in a chip. (2n = Number
of registers where n is the number of address lines.)
o A memory chip requires a Chip Select (CS) signal to enable a chip. The remaining
address lines of the microprocessor can be connected to the CS signal through an
interfacing logic.
o The address lines connected to CS select the chip, and the address lines connected to the
address lines of the memory chip select the register. Thus the memory address of a
register is determined by the logic levels (0/1) of all the address lines (including the
address lines used for CS)
o The control signal Read (RD) enables the output buffer and the data from the selected
register are made available on the output lines. Similarly the control signal Write (WR)
enables the input buffer and data on the input lines are written into memory cells.

A model of a typical memory chip representing the above requirements is shown below.

CS RD WR CS RD

An An
Address Address
R/W M ROM
Lines Lines
A0 A0

Data Data
Lines Lines
Fig: (a) R/W Memory Model (b) ROM Model

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Memory Map & Addresses

In an 8-bit microprocessor system like 8085, 16 address lines are available for memory. This
means it is a numbering system of 16 binary bits and is capable of identifying 216 = 65,536
memory registers, each register with a 16-bit address. The entire memory addresses can range
from 0000 to FFFF in HEX, A memory map is a pictorial representation in which memory
devices are located in the entire range of addresses. Memory addresses provide the locations of
various memory devices in the system and the interfacing logic defines the range of memory
addresses for each memory device.

Address range of a memory chip can be easily changed by modifying the hardware of the
chip select line, which is generated by keeping the higher order address lines of the
microprocessor at fixed logic levels. The hardware to generate the chip select address could be
inverters and NAND gates or decoder logic.

Memory & Instruction Fetch

The primary function of memory is to store instructions and data and to provide that
information to the MPU whenever the MPU request it. The MPU requests the information by
sending the address of a specific memory register on the address bus and enables the data flow
by sending the control signal as illustrated in the following example.

The instruction code 0100 1111 (4FH) is stored in memory location 2005H. Illustrate the data
flow and list the sequence of events when the instruction code is fetched by the MPU

4F 01001111
8085 Microprocessor Data Bus

Internal Data Bus Memory

2000

Instruction B C
Flag
Accumulator Flip Decoder D E
Flop H L
SP 01001111 2005
Arithmetic/Logic Unit Control
Unit PC

2005
Address Bus |
4F

Control Signal MEMR

Fig: Instruction Fetch Operation

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To fetch the instruction located in memory location 2005H, the following steps are performed:

Step 1: The Program Counter (PC) places the 16-bit address 2005H of the memory location
on the address bus.
Step 2: The control unit sends the Memory Read control signal (MEMR, active low) to
enable the output buffer of the memory chip.
Step 3: The instruction 4FH stored in the memory location is placed on the data bus and
transferred (copied) to the instruction decoder of the microprocessor.
Step 4: The instruction is decoded and executed according to the binary pattern of the
instruction.

While executing a program, the microprocessor needs to access memory quite frequently to
read instruction codes and data store in memory; the interfacing circuit enables that access.
Memory has certain signal requirements to write into and read from its registers. Similarly, the
microprocessor initiates a set of signals when it wants to read from and write into memory. The
interfacing process involves designing a circuit that will match the memory requirements with
the microprocessor signals.
Thus Memory Interfacing is the process of designing appropriate circuit arrangement for
enabling the microprocessor to access any register inside any of the many memory chips using
unconflicting appropriate address for fetching instruction codes and data from that memory
location into the microprocessor.
The primary function of memory interfacing is that the microprocessor should be able to
read from and writhe into a given register of a memory chip. To perform these operations, the
microprocessor should
o Be able to select the chip.
o Identify the register.
o Enable the appropriate buffer.

Example 1: Illustrate the memory address range of the chip with 1K (1024×8) bytes of memory,
shown in figure below and explain how the range can be changed by modifying the hardware of
the Chip Select line.
Explanation:
- Given Memory Size: 1 Kilobyte = 1024 Bytes
- Therefore the memory chip has 1024 registers.
- Number of address lines (n) = ln1024/ln2 = 10(i.e. A9-A0), which is required to identify the
registers.
- The remaining six address lines (i.e. A15-A10) of the microprocessor are used for the Chip -
Select (CS) signal. In the given figure below, the memory chip is enabled when the address
lines (i.e. A15-A10) are at logic 0. The address lines A9-A0 can assume any address of the 1024
registers, starting from all 0s to all 1s as shown next.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
Chip Select Logic Levels
1 1 1 1 1 1 1 1 1 1 03FFH

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- The memory addresses now range from 0000H to 03FFH.

- The address lines A15-A10, which are used to select the chip, must have fixed logic levels and
these lines are called high-order address lines. The address lines A9-A0, which are used to select
a register, are called low-order address lines and they can be assigned logic levels from all 0s to
all 1s and any in between combination.
- By combining the high order and the low order address lines, we can specify the complete
memory address range of a given chip.
- The memory addresses of the 1K chip in given figure can be changed to any other location by
changing the hardware of the CS line. For example, if A15 is connected to the NAND gate
without and inverter, the memory addresses will range from 8000H to 83FFH as shown below.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
Chip Select Logic Levels 83FFH
1 1 1 1 1 1 1 1 1 1

A15
MEMR
A14
A13 MEMW
A12
A11
A10
CS RD WR
A9
A8
A7
Internal Decoder

A6
A5 1024 Registers
A4
A3
A2
A1
A0
I/O Lines

Fig: Memory Address Range: 1024 Bytes of Memory

Example 2: Design an interfacing circuit so that ROM 1 of 8K and ROM 2 of 8K and R/W M 1 of
1K can be interfaced with 8085. The memory address specified by the memory devices are:

ROM 1: 0000H to 1FFFH

ROM 2: E000H to FFFFH
R/W M1: 8000H to 83FFH

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For ROM 1
- Given Memory Size: 8 Kilobyte = 1024x8 Bytes
- Therefore the memory chip has 8192 registers.
- Number of address lines (n) = ln8192/ln2 = 13(i.e. A12-A0), which is required to identify the
registers.
- The remaining three address lines (i.e. A15-A13) of the microprocessor are used for the Chip -
Select (CS) signal. The memory chip for ROM 1 is enabled when the address lines (i.e. A15-
A13) are at logic 0. The address lines A12-A0 can assume any address of the 8192 registers,
starting from all 0s to all 1s.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
Chip Select ↓ Register Select ↓
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFH

For ROM 1
Given Memory Size: 8 Kilobyte = 1024x8 Bytes
- Therefore the memory chip has 8192 registers.
- Number of address lines (n) = ln8192/ln2 = 13(i.e. A12-A0), which is required to identify the
registers.
- The remaining three address lines (i.e. A15-A13) of the microprocessor are used for the Chip -
Select (CS) signal. The memory chip for ROM 2 is enabled when the address lines (i.e. A15-
A13) are at logic 1. The address lines A12-A0 can assume any address of the 8192 registers,
starting from all 0s to all 1s.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 E000H
Chip Select ↓ Register Select ↓
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFH

For R/W M1
- Given Memory Size: 1 Kilobyte = 1024 Bytes
- Therefore the memory chip has 1024 registers.
- Number of address lines (n) = ln1024/ln2 = 10(i.e. A9-A0), which is required to identify the
registers.
- The remaining three address lines (i.e. A15-A10) of the microprocessor are used for the Chip -
Select (CS) signal. The memory chip for R/W M1 is enabled when the address lines i.e. A15 is
at logic 1 and A14-A10 are at logic 0. The address lines A9-A0 can assume any address of the
1024 registers, starting from all 0s to all 1s.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H
Chip Select ↓ Register Select ↓
1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 83FFH

The interfacing circuit is given below with all above designation:

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IO/M
+5V

E1 E2 E3
O7
MSB O6
A15 O5
3x8 O4
A14 Decoder O3
Logic O2
A13 O1
O0

RD WR RD RD

+5V
CE OE WE CE OE CE OE
E1 E2 E3
O7
MSB O6 A9 A12 A12
A12 O5 ROM 1 ROM 2
3x8 R/W M1
O4 8Kx8 8Kx8
A11 1Kx8
Decoder O3 A0 A0 A0
Logic O2
A10 O1
O0

Fig: Memory Design

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Control Signal Generation

o Generation of Read/Write Control Signal

Memory chip consists of different control signals; memory read (MEMR), Memory Write
(MEMW), Input/Output Read (IOR) and Input/Output Write (IOW). They are generated by
combining the signals RD, WR and IO/M.
- To generate the control signal MEMR we do have the combination of IO/M and RD signals
as shown in logic diagram below:
- The signal IO/M goes low for the memory operation. This signal is ANDed with RD and WR
signal to produce MEMR and MEMW control signal respectively when both input signals go
low.
- When the IO/M signal goes high, it indicates the peripheral I/O operation. This signal is
complemented using the inverter and ANDed with RD and WR signals to generated IOR and
IOW control signals respectively.

IO/M
MEMR

8085 RD
MEMW
Control
Signal
WR
IOR

IOW

Fig: Schematic to Generate Read/Write

Control Signal for Memory & I/O

o Generation of Chip Select Control Signal

 Using NAND Gate
 Using 3X8 Decoder Logic
 In 8-bit microprocessor like 8085, 16-bit address lines are used. The number of address lines
can be determined by the size of memory chip as given by 2n, where n is the number of
address lines; i.e. out of sixteen address lines ‘n’ number of address lines are used for
identify the memory register while remaining are used to enable CS control signal using
NAND gate as shown below:
A15
A14
A13 CS
A12
A11
A10

Fig: Chip Select Using

NAND Gate

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Now, by choosing any logic level either 1 or 0 the combination of input to the NAND
gate can be varied and the Chip Select line can be generated as per our requirement. By the
modification of input bits of NAND gate, memory address range can be defined as per our
need. For above example of 6 inputted NAND gate the memory address range can be varied
from 000H to 11FH.

 The decoder is used to decode the address lines. The output of the decoder is connected to
Chip Enable (Chip Select) control signal. The Chip Select line is asserted only when the
address on address lines is equivalent to 0. The control signal can be generated using 3x8
decoder logic as shown below:

A15 +5V

E1 E2 E3
O7
MSB O6
A14
O5
3x8
Decoder O4
A13
Logic O3
74LS138 O2
A12
O1
O0
CS

Fig: Chip Select Using 3x8 Decoder Logic

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Address Decoding

A microcomputer system consists of microprocessor, memory and I/O interfacing circuit.

The microprocessor communicates with all the components interconnected in system through a
common address and data bus. As a result, only one device can transmit data through the bus at
a time and other can only receive that data. If more than one device attempt to send data through
the bus at the same time, data collision may take place. So to avoid such situation and to ensure
that the proper device gets addressed in proper time, the technique used is called address
decoding.

In address decoding method, all the devices like memory, I/O units etc are assigned with
specific addresses. The address of device is determined from the way in which the address line
(from the processor) are used to enable a special device selection signal known as Chip Select
(CS).

Suppose, if the microprocessor need to communicate with the memory (either to write or
read from), the Chip Select (CS) pin of that particular memory should be enabled. At that time,
the address decoding circuit must ensure that the Chip Select (CS) pins of other devices are not
activated.

Let’s consider 2732 EPROM need to be interface with microprocessor. It is 4K× 8 bit
memory, so its address ranges from 0000H to 0FFFH.

CS CE

A12
Address
2732
Lines EPROM
A0 4096 x 8

O7 O0
Data
Lines

Fig: 2732 EPROM

To read the data from this memory, the microprocessor need to perform the following
operations:
o Select the Chip.
o Identify the Register. (Memory Location)
o Enable the OE (Output Enable) Pin.

Since, the memory range from 0000H to 0FFFH; only 12 address line (A0-A12) will be
sufficient to select all the memory location uniquely. Assume the rest address lines (A12-A15)
must be 0000H to enable the Chip Select (CS).

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A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chip Select/Chip Enable ↓ Register Select ↓
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Fig: Address Decoding
+5V
A15

E1 E2 E3
O7
MSB O6
A14
O5
3x8
O4
A13 Decoder O3
Logic O2
A12 74LS138 O1
O0 IO/M

RD

CS CE
Internal Decoder

A12
Address
2732
Lines EPROM
A0 4096 x 8

O/P Buffer
Data
Lines
O7 O0

Fig: EPROM Interfacing

This process of assigning address to a specific device depends on how many address lines
are assigned to access that device. Generally, there are two common methods; for mapping
address of these devices, they are:
o I/O Mapped I/O
o Memory Mapped I/O

I/O Mapped I/O (Peripheral-Mapped I/O)

In this method of address decoding, the I/O devices are addressed with 8-bit address, which
means that chip select signals for the devices are derived by using 8 address lines. In 8085
microprocessor, generally lower 8-bit address lines are used to derive the chip select signal. The
higher order address lines are unused and consider as don’t care condition. The instruction that
are used in I/O mapped I/O to communicate with the device are IN and OUT.

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The instruction IN (Code DP) inputs data from an input device into the accumulator and the
instruction OUT (Code D3) send the contents of the accumulator to an output device. These are
two byte instructions, with the second byte specifying the address or the port number of an I/O
device. Typically, to display the contents of the accumulator at an output device with the
address, for example, 01H, the instruction will be written and stored in memory as follows:

Memory Address Machine Code Mnemonics Memory Contents

2050H D3 OUT 01H 2050: 1101 0011H = D3H
2051H 01 - 2051: 0000 0001H = 01H

If the output port with the address 01H is designed as a LED display, the instruction OUT
will display the contents of the accumulator at the port. The second byte of this OUT instruction
can be any of the 256 combinations of eight bits, from 00H to FFH. Therefore, the 8085 can
communicate with 256 different output ports with device addresses ranging from 00H to FFH.
Similarly, the instruction IN can be used to accept data from 256 different input ports.

Memory Mapped I/O

In this method of address decoding, the I/O devices are address with 16-bit address. It means
that chip select signals for the devices are derived by using all 16 address lines from the
processor. So, all the I/O devices are treated as one of the memory location of the
microcomputer. All the instruction and signals that are used for memory access can be used for
accessing the I/O devices.

For example, LDA 5000H instruction will load the accumulator from the contents of address
5000H. If an input device, instead of memory location is connected at this address, the data from
that input device will load in accumulator. This is called memory mapped I/O technique.
On the previous example of EPROM interfacing, if A14 and A12 will be high as follow:

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Chip Select/Chip Enable Register Select
5H
↓ 000H
↓

Then, some other I/O device connected at output (O5) of 3-to-8 decoder will be selected. In
this case, EPROM will not activate, because EPROM will be selected only when A12-A15 will
0000H.
Usually in microcomputer based on 8085, memory mapping is used for memory devices like
RAM, ROM, EPROM etc and I/O mapping is used for I/O devices like 8255A (Programmable
Peripheral Interface), 8251A (Programmable Communication Interface), input/output latches etc.

In both I/O Mapped I/O and Memory Mapped I/O mode, depending on the number of
address line used to select the device, there are two types of address decoding, they are:
o Unique Address Decoding/Absolute Decoding
o Non-Unique Address Decoding/Partial Decoding

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Unique Address Decoding

If all of the address lines available on the mapping mode (i.e. available to select the chip) are
used for address decoding, then that decoding is called Unique Address Decoding. As the name
implies, in this mode, every devices will have single/unique address. This address decoding
technique is complicated but is best for all cases.

A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 1 = 01H

A7
A6
D7 D7
A5
I/O Address Data
A4 Pulse Latch Vcc
G1 Bus
A3
D0 D0
A2
Latch
A1 Enable
A0
G2
(I/O Control Signal) IOW Device Select
Pulse

Fig(1): Unique Address Decoding

Here, we have the illustration for Unique Address Decoding. As shown in the figure 1 the
output latch gets enabled for low level logic (0). This will happen if the outputs latch of gate G2
goes low, which is possible only if the signal IOW and the output of gate G1 both go low. When
the signal IOW goes low the processor starts to transfer (write) the data to the address location.

The address decoding circuit uses only the lower order 8-bit address lines A0-A7. Hence the
outputs latch is configured in I/O mapping mode. The output of gate G1 can only become low in
the above case. So if A0 is high and A1 to A7 are low the latch gets enabled if the I/O control
signal IOW from the processor becomes low. The data to the output device can be transferred in
only one case and hence the device has unique address of 01H. This process of assigning the
single address to a device is called Unique Address Decoding.

Non-Unique Address Decoding

If all of the address lines available for the mapping are not used in address decoding, then
that address decoding is called non-unique address decoding. The un-used address lines are
considered as don’t care condition. This technique of address decoding is simple to implement
but there may be a chance of address conflict. A single device may have more than one address.

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A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 1 0 = 02H

D7 D7
Data
Latch Vcc
Bus

D0 D0
Latch
Enable
A0
G2
(I/O Control IOW Device Select
Signal) Pulse

Fig: Non Unique Address Decoding

Here, we have the illustration for Non Unique Address Decoding. As shown in the figure 2
the output latch is again the low-level active device. Only one address line A0 is used to
generate the enable signal for the latch. The higher order address lines A1 to A7 are unused and
can be assumed as don’t care conditions.

The enable signal to the latch gets low if A0 goes low and the processor sends low level
output to its control pin IOW. When IOW goes low the latch gets enabled for every even
address because for even addresses A0 should be zeroes. For example if A1 = 1, A2 to A7 are
zeroes, the address of the latch is determined as enumerated in above figure i.e. 02H. The
multiple addresses for the device are 00, 02, 04 … FE etc. This type of address decoding is called
Non Unique Address Decoding.

Note: THE CONCEPT OF ADDRESS DECODING REGARDING PERIPHERAL MAPPED I/O & MEMORY
MAPPED I/O TECHNIQUES WILL BE FURTHER DISCUSSED IN NEXT CHAPTER “INTERFCING
I/O DEVICES”

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Input/Output Interfaces
Contents:

o Input/Output Devices
o Input/Output Interfaces
o Serial Interface
o 8251 Programmable Communication Interface
o RS 232-C Standard
o Parallel Interface
o 8279 Programmable Keyboard/Display Interface
o IEEE-488 Bus Interface
o 8255A Programmable Peripheral Interface

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Input/Output Devices

The input and output devices in a microcomputer system establish communication between
the microcomputer and external world. The MPU accepts data as input from devices and sends
data to output devices. There are two different methods by which I/O devices can be identified:
one uses an 8-bit address and the other uses a 16-bit address.

I/Os with 8-Bit Addresses (Peripheral-Mapped I/O)

In this type of I/O, the MPU uses eight address lines to identify an input or an output
device; this is known as peripheral-mapped I/O (also known as I/O-mapped I/O). This is an
8-bit numbering system for I/Os used in conjunction with Input and Output instructions. This
is also known as I/O space, separate from memory space, which is a 16-bit numbering
system. The eight address lines can have 256 (28 combinations) addresses; thus the MPU can
identify 256 input devices and 256 output devices with addresses ranging from 00H to FFH.
The input and output devices are differentiated by the control signals; the MPU uses the I/O
Read Control Signal for input devices and the I/O Write Control Signal for output devices.
The entire range of I/O addresses from 00H to FFH is known as an I/O Map and individual
addresses are referred to as I/O Devices Addresses or I/O Port Numbers.

If we use LEDs as output or switches as input, we need to resolve two issues: how to
assign addresses and how to connect these I/O devices to the data bus. In bus architecture,
these devices cannot be connected directly to the data bus or the address bus; all connections
must be made through tri-state interfacing devices so they will be enabled and connected to
the buses only when the MPU chooses to communicate with them. In the case of memory,
we did not have to be concerned with these problems because of the internal address
decoding, Read/Write Buffers and availability of CS and control signals of the memory chip.
In the case of I/O devices, we need to use external interfacing devices.

The steps in communicating with an I/O device are similar to those in communicating
with memory and can be summarized as follows:

o The MPU places an 8-bit address on the address bus, which is decoded by external
decode logic.
o The MPU sends a control signal (I/O Read or I/O Write) and enables the I/O device.
o Data are transferred using the data bus.

I/Os with 16-Bit Addresses (Memory-Mapped I/O)

In this type of I/O, the MPU uses 16 address lines to identify an I/O device; an I/O is
connected as if it is a memory register. This is known as Memory-Mapped I/O. The MPU
uses the same control signal (Memory Read or Memory Write) and instructions as those of
memory. In some microprocessors, such as the Motorola 6900, all I/Os have 16-bit addresses;
I/Os and memory share the same Memory Map (64K). In Memory-Mapped I/O, the MPU
follows the same steps as if it is accessing a memory register.

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Input/Output Interface

The link between the I/O devices and the microcomputer is maintained by a circuitry known
as I/O Interface. I/O Interface is a circuitry that connects I/O devices to the microcomputer. For
interfacing microprocessor to common peripherals (also called I/O devices); such as Keyboard,
CRT Terminal, Printer, Floppy Disk etc requires I/O Interface Circuit. In the 8085 based
systems, I/O devices can be interfaced using both techniques as we have discussed earlier i.e.
Peripheral Mapped I/O and Memory Mapped I/O Techniques. The process of data transfer in
both is identical. Each device is assigned a binary address, called device address or port number,
through it interfacing circuit. When the microprocessor executes a data transfer instruction for
an I/O device, it places the appropriate address on the address bus, sends the control signals,
enables the interfacing device, and transfer data. The interfacing device is like a gate for data
bus, which is opened by the MPU whenever it intends to transfer data. The two major types of
I/O interfaces are:
1. Serial Interface
2. Parallel Interface

Serial Interface

Serial communication involves the transmission of data from one place to another using
serial device. It means in serial transmission, only one line is used to transmit the complete
binary data bit by bit. Thus a serial interface exchanges data with the peripheral in serial mode
where the data are transmitted one bit at a time along a single communication link.
For example, to transmit the data 10010001, the data on the channel would be as shown
below:

D7 T
R R
B A E
U N C
F S E
M 1 0 0 1 0 0 0 1
F I
E I V
R T E
T R
D0 E
R

Fig: Serial Data Transmission

A parallel to serial converter is used to convert the incoming parallel data to a serial form
and then data is sent out with The Least Significant Bit (LSB) first and Most Significant Bit
(MSB) at last. Serial transmission is slow but inexpensive to implement as far as the number of
wire is concerned. Since only one wire is used for data transfer the amount of cross talk
(interference between different lines) decreases. Serial data transmission can be divided into
following two types.
 Synchronous Serial Data Transmission
 Asynchronous Serial Data Transmission

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Synchronous Data Transmission

The basic feature of synchronous data transmission is that the data is transmitted or received
based on a clock signal and both the transmitter and receiver are synchronized with the common
clock signal.

It is also called clock oriented transmission because all bytes of block are transmitted
constantly. In this transmission, a block of data byte is transmitted along with the
synchronization information. Usually, one or two SYNC characters are used to indicate the start
of each synchronous data stream as shown below:

Clock

D7 T
R R
B A E
U N C
F S Data Data E
SYNC SYNC
F M Byte Byte I
E I V
R T E
T Block of Data
R
D0 E
R

Fig: Synchronous Transmission

At the receiver side, as soon as it matches one or two SYNC characters based on the
number of SYNC character used, the receiver starts interpreting the data. In synchronous
transmission, the transmitting device needs to send data continuously to the receiving
device. However, if data is not ready to be transmitting, the transmitter will send SYNC
characters until the data is available.

Asynchronous Data Transmission

In asynchronous data transmission, the transmitter and receiver need not to be

synchronized with the common clock signals. It is also called character oriented
transmission, because only one character is transmitted at a time. Each character carries a
start bits and stop bits as synchronization information. Transmission begins with one start bit
that is at logic 0 (called space), followed by the required information byte, which is always
transmitted with LSB first and finally the stop bits that is at logic 1 (called Mark). This
formatting of data is known as “Framing”.

Asynchronous data transmission is shown below with the framing information.

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Clock Clock

D7 T
R R
B A E

Start Bit
U N C
F S E
M D7 D6 D5 D4 D3 D2 D1 D0

Stop Bit 1
Stop Bit 2
F I
E I V
R T E
T R
D0 E
R

Fig: Asynchronous Transmission

The asynchronous transmission is generally used in low speed transmission less than 20
Kbps, but synchronous transmission transmits data greater than 20Kbps.
Each asynchronous serial data unit can be divided into equal time intervals called bit
intervals. An 8-bit data will have 8-bit intervals. Thus each data bit will correspond to one of
the 8 intervals. The format for asynchronous serial data contains the following information:
 A low START bit that indicates beginning of the data to be transferred.
 8 data bits, denoting the actual data being transferred.
 An optional parity bit for either odd or even parity.

Baud Rate
The serial data transmission rate is also called the baud rate. The baud rate is defined
as the number of bits of data transmitted per second. Since each bit is transmitted over a
duration of one interval, Baud rate = 1/Bit Interval = Bits/Sec.
In parallel I/O, data bits are transferred when a control signal enables the interfacing
device; the transfer takes place in less than three T-states. However, in serial I/O, one bit
is sent out at a time; therefore, how long the bit stays on or off is determined by the
speed at which the bits are transmitted. Furthermore, the receiver should be set up to
receive the bits at the same rate as the transmission; otherwise, the receiver may not be
able to differentiate between two consecutive 0s and 1s.
0.83 ms

Bit TIme

Marking D0 D1 D 2 D 3 D 4 D 5 D 6 D 7
Start Bit

Stop Bit 1

Stop Bit 2
MSB
LSB

First Bit to be
Transmitted

Fig: Serial Bit Format

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Above figure shows how the ASCII character I (49H) will be transmitted with 1200
baud with the framing information of one Start and two Stop bits. The transmission
begins with an active low Start it, followed by the LSB-bit D0. The bit time-the delay
between any two successive bits is 0.83 ms; this is determined by the baud as follows:
1200 bits = 1 second
For 1 bit = 1/1200 = 0.83ms
Therefore, to transmit one character, a parallel byte (49H) should be converted into a
stream of 11 bits by adding framing bits and each bit must be transmitted at the interval
of 0.83 ms. To receive a character in the serial mode, the process is reversed-one bit at a
time is received and the bits are converted into a parallel word.
ASCII Character
The acronym ASCII stands for the “American Standard Code for Information
Interchange”. It is an 8-bit code commonly used with microprocessors for representing
alphanumeric codes. Out of the 8 bits first 7 bits are used to represent the character while
the 8th bit is used to test for errors and is referred to as parity bit. The parity bit can be set
to 1 or 0 so that the number of 1-bits in the byte either always odd or always even. The
standard ASCII Chart is given below:

STANDARD ASCII
CHART (0 – 127)

CHARACTER DECIMAL HEX CHARACTER DECIMAL HEX

NUL 0 00h SOH 1 01h

STX 2 02h ETX 3 03h
EOT 4 04h ENQ 5 05h
ACK 6 06h BEL 7 07h
BS 8 08h HT 9 09h
LF 10 0Ah VT 11 0Bh
FF 12 0Ch CR 13 0Dh
SO 14 0Eh SI 15 0Fh
DLE 16 10h DC1 17 11h
DC2 18 12h DC3 19 13h
DC4 20 14h NAK 21 15h
SYN 22 16h ETB 23 17h
CAN 24 18h EM 25 19h
SUB 26 1Ah ESC 27 1Bh
FS 28 1Ch GS 29 1Dh
RS 30 1Eh US 31 1Fh
SP 32 20h ! 33 21h
" 34 22h # 35 23h
$ 36 24h % 37 25h
& 38 26h ‘ 39 27h
( 40 28h ) 41 29h
* 42 2Ah + 43 2Bh
, 44 2Ch - 45 2Dh
. 46 2Eh / 47 2Fh
0 48 30h 1 49 31h
2 50 32h 3 51 33h
4 52 34h 5 53 35h
6 54 36h 7 55 37h

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8 56 38h 9 57 39h
: 58 3Ah ; 59 3Bh
< 60 3Ch = 61 3Dh
> 62 3Eh ? 63 3Fh
B 64 40h A 65 41h
66 42h C 67 43h
D 68 44h E 69 45h
F 70 46h G 71 47h
H 72 48h I 73 49h
J 74 4Ah K 75 4Bh
L 76 4Ch M 77 4Dh
N 78 4Eh O 79 4Fh
P 80 50h Q 81 51h
R 82 52h S 83 53h
T 84 54h U 85 55h
V 86 56h W 87 57h
X 88 58h Y 89 59h
Z 90 5Ah [ 91 5Bh
\ 92 5Ch ] 93 5Dh
^ 94 5Eh _ 95 5Fh
` 96 60h a 97 61h
b 98 62h c 99 63h
d 100 64h e 101 65h
f 102 66h g 103 67h
h 104 68h i 105 69h
j 106 6Ah k 107 6Bh
l 108 6Ch m 109 6Dh
n 110 6Eh o 111 6Fh
p 112 70h q 113 71h
r 114 72h s 115 73h
t 116 74h u 117 75h
v 118 76h w 119 77h
x 120 78h y 121 79h
z 122 7Ah { 123 7Bh
| 124 7Ch } 125 7Dh
~ 126 7Eh DEL 127 7Fh

Notes:
With synchronous transmission, a block of bits is transmitted in a steady stream
without start and stop bit code. The block may be many bits in length. So, to prevent
timing drift between the transmitter and receiver, these blocks must somehow be
synchronized, for which there are two possibilities.
One possibility is to provide a separate clock line between transmitter and
receiver. One side pulses the line regularly and the other side uses it as a clock. This
technique works well over short distance; but over long distances, the clock pulse are
subjected to some impairment as data signal and timing error can occur.
Another efficient possibility is to synchronize the transmitter and receiver and
then send large block of data one after another. To indicate the start of transmission
the transmitter sends out one or more unique character called ‘SYNC’ character or a
unique bit pattern called ‘FLAG’. Receiver uses the ‘SYNC’ character or ‘FLAG’ to
synchronize its internal clock with that of the transmitter, receiver then shifts in the
data following the ‘SYNC’ character and convert them to parallel form to be read by
microprocessor.

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Synchronous Vs Asynchronous Serial Data Transmission

Synchronous Transmission S.N Asynchronous Transmission

 Synchronous means at the same time. 1  Asynchronous means at irregular
So, both transmitter and receiver must intervals. So, transmitter and receiver
be synchronous with the common or need not to be synchronous with the
same clock. common clock.
 Serial data is transmitted along with the 2  Serial data is transmitted without
clock signal itself, which provides the transmitting the clock information.
timing information for the receiver.
 Also called clock oriented transmission 3  Also called character oriented
because a block of characters is transmission because only one character
transmitted along with the is transmitted at a time.
synchronization information.
 A complete block of characters (bytes) 4  Each character is treated individually.
treated individually and is transmitted at
a time in a steady stream.
 Transmission begins by sending one or 5  Transmission begins with one start bit
two unique characters called ‘SYNC which is always at logic low (0) called
character or unique bit pattern called ‘SPACE’ followed by the required
‘FLAG’ to the receiver that a new information byte (which is always
synchronous data stream is coming. transmitted with its LSB first) and
Receiver uses the ‘SYNC’ character or finally one or two stop bits that are
‘FLAG’ to synchronize its internal always at logic high (1) called ‘MARK’.
clock with that of the transmitter. This formatting of data is called
Framing.
 It is used for high speed transmission 6  It is used for low speed transmission
(greater than 20Kbps). (less that 20Kbps).
 It uses more sophisticated error 7  It uses less sophisticated error detection
detection and correction mechanism. mechanisms, e.g. parity bit.
 No pre-adjustment of data rate is 8  Manual pre-adjustment or presetting of
required as the receiver can respond to both transmitter and receiver is
various clock rates (as long as its necessary for operation at specific bit
maximum frequency isn’t exceeded) by period or data rate because separate
simply detecting the low high transition clocks are used by the transmitter and
of the clock signal. the receiver and because the receiver
can make no assumptions about the bit
period.
 In order to interpret the data correctly, 9 -----------
the receiving device must know the
start and end of each device data unit;
so in synchronous data transfer, the
transmitter must know the number of
data units to be transmitted.
 The synchronous receiver waits in a 10 -----------
“HUNT” mode while looking for data.

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As soon as it matches the one or two

‘SYNC’ characters, the receiver starts
interpreting the data.
 In synchronous transmission, the 11  In asynchronous transmission, the
transmitter must send data continuously transmitter need not send data
to the receiver. However, if the data continuously. It can start sending
isn’t ready to be transmitted, the character at any time. When no data re
transmitter will send ‘SYNC’ characters being transmitted a receiver stays high
until the data is available. at logic 1 called MARK.
 Basic Feature: The data is transmitted 12  Basic Feature: Synchronization is
or received based on a clock signal i.e. maintained within each character. The
a common clock signal is used to receiver has an opportunity to
synchronize both the transmitter and resynchronize itself at the beginning of
receiver on a block by block basis. At a each new character i.e. synchronization
specific rate of data transfer, the is maintained on a character by
transmitting device sends a data bit at character basis by the help of start bit
each clock pulse to the receiver and stop bit(s).
synchronized at the same clock rate
without sending start and stop bit(s).
 Example: High Speed Modems & 13  Example: Data transfer between the
Digital Communication Channel use microprocessor and the serial
synchronous data transfer. peripherals such as terminals, floppy
disks etc is primarily asynchronous.
 Clock lines are needed, hence more 14  No clock lines are needed, hence less
number of wires. number of wires.
 Somewhat sophisticated and expensive. 15  Simple and cheap, however requires and
overhead of 2 to 3 bits per character.
 Works for sufficiently long block of 16  Doesn’t work for long block of data
data bytes after some ‘SYNC’ between start and stop bit because it
character(s). increases the cumulative timing error.

Clock

Clock Clock

D7 T T
D7
R R R R
B A E A
B E
Start Bit

U N C N
U C
F S Data Data E S
SYNC SYNC F E
M Byte Byte M D7 D6 D5 D4 D3 D2 D1 D0
Stop Bit 1

I
Stop Bit 2

F F I
E I V I
E V
R T E T
Block of Data R E
T R T R
D0 E D0 E
R R

Fig: Synchronous Transmission Fig: Asynchronous Transmission

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8251A Programmable Communication Interface (PCI)

The 8251A is USART (Universal Synchronous/Asynchronous Receiver/Transmitter), designed

for synchronous and asynchronous serial data communication. It is a programmable 28-Pin
Chip. It includes five different sections, they are:

o Read/Write Control Logic & Registers

o Transmitter
o Receiver
o Data Bus Buffer
o Modem Control

TRANSMITTER

D7-D0 Data
Bus Output TxD
Buffer Register
Transmitter
C/D=0 Buffer
RD or WR Register
(P-S) TxC
RESET Transmitter
Control TxRDY
C/D=1 Control
Internal Data Bus

Register TxE
CLK WR=0 Logic
(16-Bit)

C/D Read/Write
Control RECEIVER
Logic
WR
C/D=1 Status
Register Input RxD
RD RD=0
(8-Bit) Register
Receiver
CS Buffer
Register
(S-P) RxC
DSR Receiver
DTR Modem Control
Logic RxRDY
CTS Control
RTS

Fig: Block Diagram of 8251A PCI

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Read/Write Control Logic & Registers

This section includes control logic, six input signals and three buffer registers: Data
Register, Control Register & Status Register.

Input Signals

CS (Chip Select): When this signal goes low, 8251A is selected.

RESET: A high signal on this pin reset 8251A.
C/D (Control/Data): When this signal is high, the control register or status register is
selected: The control and status register are differentiate by WR and RD signals.

 WR (Write): When this signal goes low, the MPU writes in the control register or
sends output data to the Data Buffer Register.
 RD (Read): When this signal goes low, the MPU either reads a status from Status
Register or accept data from the Data Buffer Register.
 CLK (Clock): This is the clock input for 8251A and is connected to the system clock.
The clock is necessary for communication with the microprocessor.
Control Register

The 16-bit control register split into two bytes. The first byte is called Mode Word
Instruction Register and second byte is Command Word Instruction Register.

Status Register

It checks the ready status of a peripheral, status of transmission, transmission error etc.

Data Buffer Register

This is 3-state bidirectional buffer register used to interface 8251A to the system bus.

Summary of Control Signal for 8251A PCI

CS C/D RD WR Function
0 1 1 0 MPU writes instruction in the control register.
0 1 0 1 MPU reads status from status register.
0 0 1 0 MPU outputs data to the data buffer register.
0 0 0 1 MPU accepts data from the data buffer register
1 x x x 8251A is not selected

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Transmitter Section
The transmitter accepts parallel data from the MPU and converts them into serial data for
the transmission. It has two register: A Buffer Register to hold eight bit data and an Output
Register to convert parallel data into serial data.
Transmitter control logic to controls all the operations related to the data transmission.
The transmission section has three output signals and one input signal.
 TxD (Transmit Data): Serial bits are transmitted in this line.
 TxC (Transmitter Clock): The transmitter clock controls the rate at which bits are
transmitted. This clock frequency can be 1 times the baud rate in synchronous
transmission mode and can be 1, 16 or 64 times in asynchronous transmission mode.
Suppose, Baud Rate = 110
In Synchronous Transmission Mode, TxC = 110 Hz
In Asynchronous Transmission Mode, TxC = 110 Hz in 1X Mode, TxC = 1.76 KHz in
16X Mode, TxC = 7.04 KHz in 64X Mode
 TxRDY (Transmitter Ready): This output signal when goes high, it indicates that the
Buffer Register is empty and is ready to accept a data byte. This signal is reset when
a data byte is loaded into the buffer.
 TxE (Transmitter Empty): This is also an output signal and when it goes high, it
indicates that output register is empty or 8251A has no character to send. This signal
is reset, when a data byte is transferred from Buffer Register to the output register.

Receiver Section
The receiver accepts serial data from the peripheral devices and converts them into the
parallel data and transfer to the microprocessor. It has two registers: A Buffer Register to
hold 8-bit data and an Input Register to accept the serial data from the peripheral & convert
them into the parallel data.
Receiver Control Logic controls all the operations related to the receiving data. The
receiver section has two input signals and one output signal.
 RxD (Receive Data): Bits are received serially on this line and converted into a
parallel byte in the receiver input register.
 RxC (Receiver Clock): The receiver clock controls the rate at which bits are received
by the 8251A. In synchronous mode, this clock can be 1 time the baud rate and in
asynchronous mode, it can be 1, 16, or 64 times the baud rate.
 RxRDY (Receiver Ready): This is an output signal and when it goes high, it indicates
that 8251A has character in the receiver buffer register and is ready to transfer it to
the microprocessor.

Modem Control
The Modem Control is used to establish data communication through modems over
telephone lines. However, telephone lines are designed to handle voice; the bandwidth of
telephone lines ranges from 300 Hz to 3300 Hz. The digital signal with rise time in nsec
requires a bandwidth of several MHz. Therefore, data bits should be converted into audio
tones; this is accomplished through modems. A modem is a circuit that translates digital data
into audio tone frequencies for transmission over the telephone lines and converts audio
frequencies into digital data for reception.

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RS 232-C Standard in Serial Input/Output

Serial transmission of data is used as an efficient means for transmitting digital information
across long distances. The obvious advantage is the savings in hardware. Also the existing
communication lines usually the telephone lines can be used to transfer information.
The RS 232-C is an interface convention developed standardizes the interface between Data
Terminal Equipment (DTE) and Data Communication Equipment (DCE) employing serial binary
data exchange. One of the most common uses for RS 232-C is the connection of computer
terminals to computers. This is done both directly and indirectly through modems.

RS 232-C
MC 1488 Cable MC 1489

TTL Transmit Receive TTL

2

+3.4 V-9 V -9 V +3.4 V

0.2 V  +9 V +9 V  0.2 V

Data Data
Terminal Receive Transmit Communication
3 3
Equipment Equipment
(DTE) (DCE)
MC 1489 MC 1488
Computer Modem
GND GND
7 7

Fig: RS 232-C Standard For Serial I/O

As we have known that modem and other devices used to send serial data are also called
Data Communication Equipment (DCE). The terminals or computers that are sending or
receiving the data are called Data Terminal Equipment (DTE). RS 232-C is the interface standard
developed by Electronic Industries Association (EIA) in response to the need for signal and
handshake standards between the DTE and DCE.
This standard describes the functions of 25 signal and handshake pins for serial data transfer.
It also describes the voltage levels, impedance levels, rise and fall times, maximum bit rate and
maximum capacitance for these signal lines. It also specifies that the DTE connector should be
male and the DCE connector should be female. Usually the 9-pin and 25-pin connectors are
available. The voltage levels for all RS 232-C are as follow:

Logic high or 1 is a voltage between -3V and -15V

Logic low or 0 is a voltage between +3V and +15V
The commonly used voltages are +12V and -12V

The signal levels of RS 232-C are not compatible with that of The DTE and DCE, which are
TTL signals. Hence TTL to RS 232-C and RS 232-C to TTL conversions are required for
establishing the link between DTE and DCE. The line driver such as MC1488 ca n be used
between DTE and RS 232-C cable and MC1489 can be used between the RS 232-C cable and
DCE.

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Signals Pins Signals

1 Protective Ground
Secondary Transmitted Data 14
2 Transmitted Data (TxD)  DCE
Transmission Signal Element Timing (DCE Source) 15
3 Received Data (RxD)  DTE
Secondary Received Data 16
4 Request to Send (RTS)  DCE
Receiver Signal Element Timing (DCE Source) 17
5 Clear to Send (CTS)  DTE
Unassigned 18
6 Data Set Ready (DSR)  DTE
Secondary Request to Send 19
7 Signal Ground
DCE  Data Terminal Ready (DTR) 20
8 Received Line Signal Detector
Signal Quality Detector 21
9 Reserved for Data Set Testing
Ring Indicator 22
10 Reserved for Data Set Testing
Data Signal Rate Selector (DTE/DCE Source) 23
11 Unassigned
Transmit Signal Element Timing (DTE Source) 24
12 Sec. Rec’d. Line Sig. Detector
Unassigned 25
13 Sec. Clear to Send

Fig: RS 232-C Pin Diagram

Among 25 pins of RS 232-C, the important pin numbers, the signal names and their descriptions
are listed in table below:

Pin No. Signals Functions

Transmit Data TxD Output, transmit data from DTE to DCE.
3 Receive Data RxD Input, DTE receives data from DCE.
4 Request to Send RTS General purpose output from DTE.
5 Clear to Send CTS Input to DTE, used as handshake.
6 Data Set Ready DSR Input to DTE, indicates that DCE is ready.
7 Signal Ground GND Common reference between DTE and DCE.
8 Data Carrier Detect DCD Used by DTE to disable data reception.
20 Data Terminal Ready DTR Output means DTE is ready.

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Parallel Interface

A Parallel Interface exchanges data with the peripheral in parallel mode, where all the n-bits
of data are transmitted simultaneously. Each bit in a word is transmitted on a separate line. So to
transmit a word of n-bits, there must be n-lines in parallel data transfer.
For example, to transmit the data 10010001, the data on the channel would be as shown
below:

T 1
R 0 R
A E
N 0 C
S 0 E
M I
I 1 V
T E
T 0
R
E 0
R
1

Fig: Parallel Data Transmission

Parallel interface provides a faster exchange of data but becomes expensive due to the needs
of multiple communication links. So, it is impractical for exchanging data over a long distance.

Method of Parallel Data Transfer

 Simple Input & Output

In the simple input and output parallel data transfer method, microprocessor assumes
that peripheral devices are always present and ready to communicate with the
microprocessor.

Data

Fig: Simple I/P and O/P

For example, consider the simple display device such as LED is always there and ready,
so microprocessor can send data to it at any time.
 Simple Strobe Input & Output
In many applications, valid data is present on an external device only at a certain time,
so it must be read in at that time.

Data

STB

Fig: Simple Strobe I/P & O/P

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For example, consider the keyboard. When a key is pressed, keyboard sends out the
ASCII Code for the pressed key on eight parallel data lines, and then sends out a strobe
signal (STB) on another line to indicate that valid data is present to transmit.

 Single Handshake with Input & Output

In this method, the peripheral sends some parallel data and then sends the STB signals to
the microprocessor. The microprocessor detects the STB signal on a polled or interrupt basis
and read in the byte of data. Then microprocessor sends an acknowledge signal (ACK) to the
peripheral device to indicate that the data has been read and that the peripheral can send the
next byte of data.

Data

STB

ACK

Fig: Single Handshake with I/P & O/P

 Double Handshake with Input & Output

For data transfer where even more coordination is required between the sending system
and receiving system, a double handshake is used.

STB

ACK

Data

Fig: Double Handshake with I/P & O/P

First of the entire data sending device asserts STB signal low to ask, “Are you ready?”
The receiving system raises its ACK line high to indicate that it is ready. The sending device
(Computer/Peripheral) then sends the bytes of data and raises its STB signal high to say,
“Here is some valid data for you”. After receiving the data, the receiving system low its
ACK signal to indicate that it has received the data and waiting for next byte of data.

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Synchronizing the Computer with Peripherals

The information exchanged between a microprocessor and peripheral devices consists of I/O
data, control information and status information.

The status information tells the microprocessor about the readiness or status of the
peripheral devices. It may also enable the microprocessor to monitor the devices, to ensure that
it is in good operation condition. As for example, a printer indicates whether it has run out of
paper or the paper is jammed. Another example is about READY signal, while communication
with the memory device.

Control information comprises the command send by microprocessor to peripheral devices

to take some specific action. If the peripheral device operates at different speeds,
microprocessor should have some means or technique to communicate with those devices.
Different technique used to transfer data between different speed device and microprocessor
is called “Synchronization”.

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8279 Programmable Keyboard/Display Interface

The data input and display are an integral part of many microprocessor based systems. The
system designer needs an interface that can control this operation. With this in mind, Intel
Corporation brought out 8279 Chip to interface with their 8-bit microprocessor. The 8279 is a
hardware approach to interfacing keyboard and display.

The 8279 is a 40-pin device, which functionally consists of four different sections:

 MPU Interface Section

 Keyboard Section
 Scan Section
 Display Section

DB0-DB7 IRQ
CLK RESET RD WR CS A0

Data Buffer I/O Control FIFO/Sensor

RAM Status

Internal Data Bus (8)

Keyboard
Display 16 x 8 Control and 8x8
Debounce
Address Display Timing FIFO/Sensor
&
Register RAM Registers RAM
Control

Timing
Display &
Registers Control Scan Counter Return

SHIFT
OUT A0-A3 OUT B0-B3 BD SL0-SL3 RL0-RL7 CNTL/STB

Fig: The 8279 Logic Block Diagram

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MPU Interface Section

This section includes eight bidirectional data lines (DB0-DB7), one interrupt request line
(IRQ) and six input signals. The six input signals are: RD (Read), WR (Write), CS (Chip
Select), A0 (Buffer Address Line), RESET & Clock.

The IRQ is an output line that becomes active when key data exists in an internal FIFO
(First-In-First-Out) RAM of 8279. This line is usually connected to one of the hardware
interrupt line of the MPU.

The RD and WR are the control signals used to perform read and write operation
respectively. The CS and RESET signal are used to select and reset the 8279 respectively.
The clock signals are used to generate internal timing. A high on the A0 pin indicates that the
signals are command or status signal and a low indicate that they are data.

Keyboard Section
This section includes eight return lines (RL0-RL7) that can be connected to eight columns
of a keyboard, SHIFT and CNTL/STB (Control/Strobe) lines. Basically there are three
modes of operations:
 Scanned Keyboard Mode
 Sensor Matrix Mode
 Strobed Input Mode

Scanned Keyboard Mode

In this mode, when a key is pressed, a unique 6-bit code is generated, along with the
CNTL and SHIFT states. So all together 8-bit code is formed and stored in FIFO RAM.
As soon as the 8-bit code is stored in FIFO RAM, the interrupt request (IRQ) pin of the
device goes high to indicate that the data is present in RAM. As the FIFO RAM is read,
the IRQ goes low, but becomes high again if the FIFO RAM contains further data. The
data format for the scanned keyboard mode is as follows:

MSB LSB

CNTL SHIFT

SCAN RETURN

Fig: Scanned Keyboard Mode

In the above figure, the three return bits D0, D1 and D2 comprise the column of
keyboard and the three scan line D3, D4 and D5 be the row of the keyboard.
In this scanned keyboard mode, there are two further alternative ways of operations:

 2-Key Lockout
 N-Key Rollover

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In 2-Key Lockout Mode, if two keys are pressed almost simultaneously (i.e.
without releasing the first pressed key, a second key is pressed); only the first key is
recognized. The recognized key code is then taken into FIFO RAM and IRQ is
activated. If the FIFO RAM is full, the key code is not entered, rather error flag is set.

In N-Key Rollover Mode, when a key is pressed, the debounce logic is set and the
debounce circuits waits for two keyboard scans and then clocks again whether the
key is till pressed. If it still is, the key code is stored in FIFO RAM. In this mode,
there is no limit to the number of keys that can be pressed for a simultaneous
depression, the key code are entered into FIFO RAM according to the order of the
key pressed. If during single debounce cycle, two keys are pressed, then error flag
will be set.

Debounce: When a mechanical switch/key is pressed, there is a transient during

which the contact is not firm a microscopic bouncing of a contact elements take
place. This may lead to ambiguous interpretation of the states of the switch. To avoid
this problem either hardware or software solutions are used, this is known as
debouncing.

Sensor Matrix Mode

In this mode, the keys are placed in the form of a matrix (scan lines comprising the
columns and the return lines comprising the rows). The data on each of the eight return
lines are directly entered into the sensor RAM. The SHIFT and CNTL status are not
taken as input in this mode. The data formats for the sensor matrix mode are as follows:

MSB LSB

RL7 RL6 RL5 RL4 RL3 RL2 RL1 RL0

Fig: Sensor Matrix Mode

In this mode, the debounce logic is inhibited. The IRQ line goes high, if a sensor
value is found to have changed at the end of a sensor matrix scan.

Strobed Input Mode

In this mode, the data is accepted from the return lines and stored in the FIFO RAM
during the rising edge of a STB (Strobe) signal. The data formats for the strobed input
mode are as follows:

MSB LSB

RL7 RL6 RL5 RL4 RL3 RL2 RL1 RL0

Fig: Strobed Input Mode

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Scan Section
The scan section consists of a scan counter and four scan lines (SL0-SL3). The scan
counter can be operated in either encoded or decoded mode.

In the encoded mode, generally out of four scan lines, 3 scan lines (SL0-SL2) are fed to
the 3-to-8 decoder (external to the 8279), that generates eight decoded scan lines. Combining
these with the eight return lines, one can form as microprocessor to 8x8 keyboard matrix,
which can be used for defining 64 different characters.

In the decoded mode, which uses an internal decoder (present inside the 8279), tow least
significant bits are decoded which is combined with eight return lines (RL0-RL7) and the
SHIFT and CNTL line to permits 4 x 8 x 4 = 128 different character definition.

Display Section
The display section consists of display address registers, 16x8 display RAM, Display
register and eight output lines divided into two groups A0-A3 and B0-B3. It also consist
the single BD (Blank Display) output line, which is used to blank the display during digit
switching.

The display address registers hold the address of the word currently being written or
read by the CPU. These addresses can be set to auto increment after each read or write.
The display RAM can be directly read by the CPU after the correct mode and address is
set.

The A and B nibble, out of 8 output lines can be entered independently or as one
word, according to the mode set. Data entry to the display can be set to either left or
right entry.

Left Entry (Type Writer) Mode: In the left entry mode, the first character typed
appears at the extreme left, then the carriage advances one step (auto-increment),
then second character appears on the right of the first character and so on.

Right Entry (Calculator) Mode: In right entry mode, the first character entered
appears at the right most display position. When a second character enters, the first
character shift one place to the left on the display and the second character appears to
its right. At the third entry, both the first and the second characters move one
position left and the third character appears again at the right most position.

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IEEE-488 Bus Interface

The IEEE - 488 standards defines a byte-serial, 8-bit parallel, asynchronous type instrument
interface. It is a document that describes the rules, specifications, timing relationships, physical
characteristics etc of an interfacing technique that allows digital instruments and devices to be
interconnected. It is a hardware (wires, connectors etc) that is used to implement the standard.
Sixteen signals line comprise the complete IEEE – 488 bus structure as shown below.

1 D 1
2 A 2
T
3 A 3
4 4
5 L 5
I
6 N 6
7 E 7
8 S 8

Hand-Shake Lines
1 DAV 1
2 NRFD 2
3 NDAC 3
Bus Management Lines
4 IFC 4
5 ATN 5
6 REN 6
7 SRQ 7
8 EOI 8
Fig: IEEE – 488 Interface

Legend:
Bus Management Lines
EOI – End or Identity
SRQ – Service Request
REN – Remote Enable
ATN – Attention
IFC – Interface Clear

Hand-Shake Lines
NDAC – Not Data Accepted
NRFD – Not Ready For Data
DAV – Data Valid

Since, it is not guaranteed by the standard that instruments will send information coded in
this suggested manner, two IEEE – 488 interconnected instruments may always be able to talk to
each other, but they may not always be able to understand each other.

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Serial Vs Parallel Communication

Serial Communication SN Parallel Communication

 Individual data bits and the eventual 1  Data word (a group of bits) is
parity bit are transmitted successively transmitted at a time parallelly over a
i.e. in a serial manner via a single data group of wires (entire data bus). Each
line one after the other. bit is transmitted over its own wire.
 The individual data word/unit is split 2  The individual data units (i.e. data
into single bits and transferred bit by bit. bytes) are transmitted as a whole.
 Simple due to reduced size of data path 3  Hardware required is complicated.
i.e. only a single communication link.
 Data transmission rate is slow. 4  Data transmission rate is high.
 Inexpensive. 5  Expensive.
 For long distance Transmission. 6  For short distance transmission.
 Universal in nature and more common. 7  May be impractical or impossible in
many situations.
 Sometimes they tend to be faster than 8  -----------
conventional parallel data transfer
(clocking frequency concerned).
 In some media (wireless) serial is the 9  Some devices such as a CRT
only form of communication e.g. RS Terminal or a Cassette Tape etc can’t
232 C. designed for parallel I/O. e.g. IEE 488

 To transmit a word of n-bits, serial data 10  -----------

transmission takes n times more time
than taken in parallel data transmission.
 The devices/peripherals commonly used 11  The devices commonly used for
for serial data transfer with the parallel data transfer with
microprocessor are CRT Terminals, microprocessor are Keyboards, 7
Printer/also used in parallel mode, Segment LEDs, Data Converters and
cassette tapes, modems for telephone memory.
lines etc.

D7 T T 1
R R
R 0 R
A A
B E E
N N 0
U C C
S
F S E 0 E
1 0 0 1 0 0 0 1 M
M I I
F I 1
I V
E V T
T E
R E T 0
T R
R E
0
D0 E R
R 1

Fig: Parallel Data Transmission

Fig: Serial Data Transmission

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8255A Programmable Peripheral Interface (PPI)

The 8255A is a widely use, programmable, parallel I/O device. It can be programmed to
transfer data under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile
and economical (when multiple I/O ports are required), but somewhat complex.
The 8255A has 24 I/O pins that can be grouped primarily in two 8-bit parallel ports: A
and B, with the remaining eight bits as port C. The eight bits of port C can be used as individual
bits or be grouped in two 4-bit ports: CUPPER (CU) and CLOWER (CL) as in figure given below. The
functions of these ports are defined by writing a control word in the control register.

Port A

CU
8255A Port C

CL

Port B

Fig: 8255A I/O Ports

The following figure shows all the functions of the 8255A, classified according to two
modes: The Bit Set/Reset (BSR) Mode and The I/O Mode. The BSR Mode is used to set or reset
the bits in Port C. The I/O Mode is further divided into three modes: Mode 0, Mode 1 and
Mode2. In Mode 0, all ports function as simple I/O ports. Mode 1 is a handshake mode whereby
ports A and/or B use bits from port C as handshake signals. In the handshake mode, two types of
I/O data transfer can be implemented: Status Check and Interrupt. In Mode 2, port A can be set
up for bidirectional data transfer using handshake signals from port C and port B can be set up
either in Mode 0 or Mode 1.

Control Word

D7 D6 D5 D4 D3 D2 D1 D0
0/1

BSR Mode I/O Mode

(Bit Set/Reset)

For Port C Mode 0 Mode 1 Mode 2

No Effect on I/O Simple I/O for Handshake I/O Bidirectional
Mode Ports A, B & C for Ports A and/ Data Bus for
or B Port A

Port C Bits are

Port B: Either in
Used for
Mode 0 or 1
Handshake
Port C Bits are
Fig: 8255A Operating Modes Used for
Handshake

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The block diagram of 8255A is shown below. It has two 8-bit ports (A and B), two 4-bit ports
(CU and CL), and the data bus buffer and control logic. The simplified but expanded version of
the internal structure, including a control register can be shown in the next figure.

Group A
Port I/O
A PA7-PA0
(8)
Group
A
Control

8-Bit Internal Data Bus

Group A
RD Port I/O
C Upper PC7-PC4
WR (4)
Read/Write Data
A1 Control D0-D7 Bus
Logic Buffer
A0 Group B
Port I/O
RESET C Lower PC3-PC0
(4)
Group
B
CS Control
Group B
Port I/O
B PB7-PB0
(8)

Fig: The 8255 A Block Diagram

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RD

WR

WR
Port
A
00

Control
Register RD

WR
EN

Port
CS C
10 EN

11
A1 10 RD
Internal C
01
A0 Decoding B WR
00
A

Port
B
Fig: Expanded Version of the 01 EN
Control Logic and I/O Ports

8255A Block Diagram Description

Control Logic

The control section has six lines. Their functions and connections are as follows:
 RD (Read): This control signal enables the read operation. When the signal is low, the
MPU reads data from a selected I/O port of 8255A.
 WR (Write): This control signal enables the write operation. When the signal goes low,
the MPU writes into a selected I/O port or the control register.
 RESET (Reset): This is an active high signal. It clears the control register and sets all
ports in the input mode.
 CS, A0 and A1: These are device select signals. CS is connected to a decoded address.
And A0 and A1 are generally connected to MPU address lines A0 and A1 respectively.

The CS signal is the Master Chip Select, and A0 and A1 specify one of the I/O ports or the
control register as given below:

CS A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Register
1 x x 8255A is not selected

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I/O Ports
It has two 8-bit ports (A and B), two 4-bit ports (CU and CL).
 Port A
- Can be used as an 8-bit input port.
- Can be used as an 8-bit output port.

 Port B
- Can be used as an 8-bit input port.
- Can be used as an 8-bit output port.

 Port C
- Can be used as an 8- input or output port.
- Can be used as 4-bit ports.
- Can be used to produce handshake signals for ports A and B.

Data Bus Buffer

- Bidirectional 8-bit buffer, used to interface the 8255A to the system data bus.
- Data is transmitted or received by the buffer upon execution of input or output
instruction by the microprocessor.
- Control words and status information are also transferred through the data bus buffer.

Group A & Group B Control

- Each of the control blocks (Group A & Group B) accepts “Commands” from the internal
data bus and issues the proper commands to its associated ports.
- Control Group A  Port A and Port CUPPER (C7-C4)
- Control Group B  Port B and Port CLOWER (C3-C0)

Data I/O Lines

 D0-D7
- These are the data input/output lines for the device.
- All information read from and written to the 8255 occurs via these 8 data lines.

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Control Word

The above figure of 8255A Expanded Version of Control Logic & I/O Ports shows a
register called the control register. The contents of this register, called the control word,
which specify an I/O function for each port. This register can be accessed to write a control
word when A0 and A1 are at logic 1, as mentioned in above table. The register is not
accessible for a Read Operation.

Bit D7 of the control register specifies either the I/O function or the Bit Set/Reset
function as classified in fig: 8255 A Operating Modes. If bit D7 = 1, bits D6-D0 determine I/O
functions in various mode as shown in figure below. If bit D7 = 0, port C operates in the Bit
Set/Reset (BSR) mode. The BSR control word does not affect the functions of ports A and B.

To communicate with peripherals through the 8255 A, three steps are necessary.

o Determine the addresses of ports A, B & C and of the control register according to
the Chip Select Logic and Address Lines A0 and A1.

o Write a control word in the control register.

o Write I/O instructions to communicate with peripherals through port A, B & C.

Control Word

D7 D6 D5 D4 D3 D2 D1 D0

Group B
Port C (Lower: PC3-PC0)
1 = Input
0 = Output
Port B
1 = Input
0 = Output
Mode Selection
0 = Mode 0
1 = Mode 1

Group A
Port C (Upper: PC7-PC4)
1 = Input
0 = Output
Port A
1 = Input
0 = Output
Mode Selection
00 = Mode 0
01 = Mode 1
1x = Mode 2

1 = I/O Mode
0 = BSR Mode

Fig: 8255 A Control Word Format for I/O Mode

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Operating Modes of 8255 A PPI

 BSR (Bit Set/Reset) Mode

The BSR mode is concerned only with the eight bits of port C, which can be set or reset by
writing an appropriate control word in the control register. A control word with bit D7 = 0 is
recognized as BSR control word and it does not alter nay previously transmitted control
word with bit D7 = 1; thus the I/O operations of ports A and B are not affected by a BSR
control word. In the BSR mode, individual bits of port C can be used for applications such as
an on/off switch.
BSR Control Word
This control word, when written in the control register, sets or resets one bit at a time, as
specified in following figure.

D7 D6 D5 D4 D3 D2 D1 D0

0 X X X Bit Select S/R

BSR Mode Set = 1

Reset = 0
Not Use, 000 = Bit 0
Generally
Set = 0 001 = Bit 1
010 = Bit 2
011 = Bit 3
100 = Bit 4
101 = Bit 5
Fig: 8255 A Control Word Format 110 = Bit 6
in BSR Mode
111 = Bit 7

 Input/Output Mode

Mode 0: Simple Input or Output

In this mode, ports A and B are used as two simple 8-bit I/O ports and port C as two 4-bit
ports. Each port (or half-port, in case of C) can be programmed to function as simply an
input port or an output port. The input/output features in mode 0 are as follows:
- Outputs are latched.
- Inputs are not latched.
- Ports do not have handshake or interrupt capability.

Mode 1: Input or Output with Handshake

In this mode, handshake signals are exchanged between the MPU and peripherals prior to
data transfer. The features of this mode include the following:
- Two ports (A and B) function as 8-bit I/O ports. They can be configured either as input
or output ports.
- Each port uses three lines from port C as handshake signals. The remaining two lines of
port C can be used for simple I/O functions.
- Input and Output data are latched.
- Interrupt logic is supported.

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Mode 2: Bidirectional Data Transfer

This mode is used primarily in applications such as data transfer between two computers or
floppy disk controller interface. In this mode, port A can be configured as the bidirectional
port and port B either in Mode 0 or Mode 1. Port A uses five signals from port C as
handshake signals for data transfer. The remaining three signals from port C can be used
either as simple I/O or as handshake for port B.

8255 A Chip Select Logic & I/O Port Addresses

A = 80 H
A7
CS
A6 8
A1 A1 2
A5
A0 A0 5 C = 82 H
A4 5
IOR RD
A3 A
IOW WR
A2
B = 81 H
Reset

Fig: 8255 A Chip Select

Hex
CS Port
Address

A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 = 80 H A
0 1 = 81 H B
1 0 = 82 H C
1 1 = 83 H Control
Register

Fig: 8255 A I/O Port Addresses

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Example 1: I/O Mode

Write a program to read the DIP switches and display the reading from port B at port A and from port
CL at port CU.

Solution
1. Port Addresses: This is a memory-mapped I/O; when the address line A15 is high, the Chip
Select line is enabled. Assumming all don’t care lines are at logic 0, the port addresses are as
follows:
Port A = 8000H (A1 = 0, A0 = 0)
Port B = 8001H (A1 = 0, A0 = 1)
Port C = 8002H (A1 = 1, A0 = 0)
Control Register = 8003H (A1 = 1, A0 = 1)

2. Control Word:

D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 1 1 = 83 H

I/O Port A in Port A = Port CU = Port B in Port B = Port CL =

Function Mode 0 Output Output Mode 0 Input Input

3. Program

MVI A, 83 H ; Load Accumulator with the control word

STA 8003 H ; Write word in the control register to initialize the ports
LDA 8001 H ; Read switches at port B
STA 8000 H ; Display the reading at port A
LDA 8002 H ; Read switches at port C
ANI 0F H ; Mask the upper four bits of port C; these bits are not input data.
RLC ; Rotate and place data in the upper half of the accumulator.
RLC
RLC
RLC
STA 8002 H ; Display data at port CU.
HLT

4. Program Description: The circuit shown below for this problem is designed for memory-
mapped I/O; therefore, the instructions are written as if all the 8255A ports are memory
location. The ports are initialized by the control word 83H in the control register. The
instructions STA and LDA are equivalent to the instructions OUT and IN respectively.
In this example, the low four bits of port C are configured as input and the high four bits
are configured as output; even though port C has one address for both halves CU and CL
(8002H). Reand and Write operations are differentiated by the control signals MEMR and
MEMW. When the MPU reads port C (e.g. LDA 8002H), it receives eight bits in the
accumulatro. However, the high-order its (D7-D4) must be ignored because the input data bits
are in PC3-PC0. To displaythese bits at the upper half of port C, bits (PC3-PC0) must be
shifted to PC7-PC4.

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LEDs

PA7

BUFFER
PA0
+5V
PC7

BUFFER
A15 CS
PC4
8255 A

PC3
DIP Switches
PC0
A1 A1
PB7
A0 A0
MEMR RD PB0
MEMW WR
RESET OUT
(8085)

+5V

Fig: Interfacing 8255A I/O Ports in Mode 0

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Example 2: BSR Mode

Write a BSR control word subroutine to set bits PC7 and PC3 and reset them after 10 ms. Use the
schematic in the figure: 8255A Chip Select Logic and I/O Port Address and assume that a delay
subroutine is available.

Solution

1. BSR Control Words

D7 D6 D5 D4 D3 D2 D1 D0
To Set Bit PC7 0 0 0 0 1 1 1 1 = 0FH
To Reset Bit PC7 0 0 0 0 1 1 1 0 = 0E H
To Set Bit PC3 0 0 0 0 0 1 1 1 = 07 H
To Reset Bit PC3 0 0 0 0 0 1 1 0 = 06 H

2. Port Address
Control Register Address = 83 H

3. Subroutine
BSR: MVI A, 0F H ; Load byte in accumulator to set PC7
OUT 83 H ; Set PC7 = 1
MVI A, 07 H ; Load byte in accumulator to set PC3
OUT 83H ; Set PC3 = 1
CALL DELAY ; This is a 10-ms delay
MVI A, 06H ; Load accumulator with the byte to reset PC3
OUT 83 H ; Reset PC7
MVI A, 0E H ; Load accumulator with the byte to reset PC7
OUT 83 H ; Reset PC7
RET

4. Analysis
 To set/reset bits in port C, a control word is written in the Control Register and not in port C.
 A BSR contrl word affects only one bit in port C.
 The BSR control word does not affect the I/O mode.

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Interrupts
Contents:

o Interrupt: Introduction
o 8085 Interrupts
o Interrupt Service Routine & Its Requirement
o Interrupt Structure
o 8086 Interrupt System
o 8259A Programmable Interrupt Controller

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An interrupt is process, getting attention of the microprocessor to perform some another task
while it is busy in doing something else.
When microprocessor is busy in executing one program, it can be stop for the execution of
the current program temporarily and can deviates its execution process to another one. After
performing the requested task, it returns to the previous program from where it has deviated.
This process is called interrupt. The interrupt process is asynchronous, that means it can be
initiated at any time without reference to the system clock. However, the response to an
interrupt request is directed or controlled by the microprocessor.

8085 Interrupts
Microcomputers can transfer data to or from an external device using the interrupt I/O. In
order to accomplish this, the microcomputer uses a pin on the microprocessor chip called the
Interrupt Pin (INTR). The external I/O device is connected to this pin.
When the device wants to communicate with the microcomputer, it makes the signal on the
interrupt line high or low, depending on the microcomputer. The microcomputer responds by
sending signal via its pin called Interrupt Acknowledgement (INTA).
Mainly, the interrupts are typically classified into two types, they are:

 External Interrupt
 Internal Interrupt

External Interrupt
An external interrupt is caused by a device that is external to the processor i.e. these are
usually initiated via the microprocessor’s interrupt pins by external devices such as A/D
converters. External Interrupt can be further divided into two types.

 MI (Maskable Interrupt)
 NMI (Non Maskable Interrupt)

An interrupt is called Maskable Interrupt, if it can be disabled or delayed or rejected i.e. a

Maskable Interrupt can be enabled or disabled by executing instructions such as EI (Enable
Interrupt) and DI (Disable Interrupt). If the microprocessor’s interrupt flag is disabled, it
ignores a Maskable interrupt. The 8085 provides two instructions to enable or disable interrupts.

o EI (Enable Interrupt): This is a one byte instruction. This instruction sets the interrupt
enable flip flop and enables all the interrupts. The interrupt request is disable by system
reset or by interrupt response process.
o DI (Disable Interrupt): This is also one byte instruction. This instruction resets the
interrupt enable flip flop and hence disable all the interrupt except TRAP.

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When the interrupt is disabled, the interrupt enable flip flop is reset to 0 and no Maskable
Interrupts are recognized by the processor. RST 7.5, RST 6.5, RST 5.5 and INTR are Maskable
Interrupts.
If the interrupt request cannot be disabled and microprocessor must response to it, such
interrupt is called Non Maskable Interrupt. The microprocessor can ignore or delay a Maskable
Interrupt request if it is performing some critical task; however, it has to respond to a Non
Maskable Interrupt request immediately. The 8085 has one Non Maskable Interrupt TRAP

The Non Maskable Interrupt has the higher priority over the Maskable Interrupt and cannot
be enabled or disabled by instructions. This means that if both the Maskable and Non Maskable
Interrupts are activated at the same time the then processor will service the Non Maskable
Interrupt first. This gives the concept of Interrupt Priority which will be discussed in later. So,
the priorities for servicing the interrupt requests among a number of devices depend on the type
of interrupt and the design of the specific microcomputer system (both hardware and software).

Internal Interrupt
Internal interrupts are activated internally by exceptional conditions such as overflow,
division by zero and execution of an illegal Opcode. They are handled in the same way as
external interrupt. Internal Interrupts can also be activated by execution of TRAP.
When TRAP instruction is executed, the processor is interrupted and serviced in the same as
External Interrupts. This interrupt is useful for operating the microprocessor in Single Step Mode
and hence important in Debugging.
The difference between internal and external interrupt is that the internal interrupt is initiated
by some exceptional conditions caused by the program itself rather than by an external events.
Internal interrupts are synchronous with the program, while external interrupts are
asynchronous. If the program is return, the internal interrupt will occur in the same place each
time. External interrupts depend on external conditions that are independent of the program
being executed at the time.

Hardware & Software Interrupts

An interrupt request on one of the interrupt lines of the 8085 by peripheral device is called
hardware interrupt. It is generated by peripheral devices. The hardware interrupt lines are TRAP,
RST 7.5, RST 6.5 & RST 5.5, which have fixed vectored address.
But in case of the INTR interrupt line, it has eight vectored addresses and the hardware in
the interrupting device decides where to deviate the execution. But it is possible to deviate the
execution of control to any one of the eight vectored address by using the RST (Restart)
instruction in the program. These instructions are: RST 0 to RST 7. This is termed as software
interrupt in 8085. Software interrupt is a special call instruction that behaves like an interrupt
rather than a subroutine call. It can be used by the programmer to initiate an interrupt procedure
at any desired point in the program. The most common used of software interrupt is associated
with a supervisor call instruction. This instruction provides means for switching from a CPU
user mode to the supervisor mode. Certain operations in the computer may be assigned to the
supervisor mode only, as for example, a complex input or output transfer procedure.

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Vectored & Non Vectored Interrupts

There are two ways of redirecting the execution to the ISR depending on whether the
interrupt is Vectored or Non-Vectored.
In Vectored Interrupt, the address of the subroutine is already known to the microprocessor
i.e. they are automatically transferred to the specific location on memory page 00H without any
external hardware. They don’t require INTA (Interrupt Acknowledge) signal or an input port.
The necessary hardware is already implemented inside the 8085. RST 5.5, RST 6.5, RST 7.5 and
TRAP all are automatically vectored. TRAP has the highest priority followed by RST 7.5, RST
6.5 and RST 5.5. The interrupts and their call locations are:

Interrupts Call Location

TRAP 0024 H
RST 7.5 0030 H
RST 6.5 0034 H
RST 5.5 0020 H

In Non-Vectored Interrupt, the device will have to supply the address of the subroutine to
the microprocessor i.e. they require external hardware to supply a call location to restart the
execution. The 8085 has only Non Vectored Interrupt i.e. INTR (Interrupt Request).

 INTR
The INTR is different from other four interrupts. This interrupt is not automatically vectored
as other interrupts do. When INTR is requested, an external hardware connected to the data bus
delivers one restart instruction out of eight restart instruction discussed below and according to
which the microprocessor is vectored or transferred to the particular memory location.
Binary Code Call Location in
Mnemonics HEX Code
D7 D6 D5 D4 D3 D2 D1 D0 HEX
RST 0 1 1 0 0 0 1 1 1 C7 0000 H
RST 1 1 1 0 0 1 1 1 1 CF 0008 H
RST 2 1 1 0 1 0 1 1 1 D7 0010 H
RST 3 1 1 0 1 1 1 1 1 DF 0018 H
RST 4 1 1 1 0 0 1 1 1 E7 0020 H
RST 5 1 1 1 0 1 1 1 1 EF 0028 H
RST 6 1 1 1 1 0 1 1 1 F7 0030 H
RST 7 1 1 1 1 1 1 1 1 FF 0038 H
These are 1-byte Call instructions that transfer the program execution to a specific memory
location on page 00H. The RST instructions are executed in a similar way to hat of Call
instructions. The address in the Program Counter (meaning the address of the next instruction to
an RST instruction) is stored on the stack before the program execution is transferred to the RST
call location. When a processor encounters a Return instruction in the subroutine associated
with the RST instruction, the program returns to the address that was stored on the stack.

For example to implement the instruction RST 5, a circuit can be used as shown in below;
where RST 5 is decoded, a 1-byte Call instruction to location 0028H.

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+5V

Tri-State Buffer

DI7 1

DI6 1

DI5 1

DI4 0
Data
EFH
Bus
DI3 1

DI2 1

DI1 1

DI0 1

INTA from
Enable Microprocessor

Fig: A Circuit to Implement the Instruction RST 5

 TRAP
TRAP, a Non Maskable Interrupt known as NMI. It has the highest priority among the
interrupt signals, it need not be enabled and it cannot be disabled. It is level and edge
sensitive, meaning that the input should go high and stay high to be acknowledged. It cannot
be acknowledged again until it makes a transition from high to low to high. When this
interrupt is triggered, the program control is transferred to location 0024H without any
external hardware or the interrupt enable instruction EI. TRAP is generally used for such
critical events as power failure and emergency shut-off.

 RST 7.5, 6.5 & 5.5

These Maskable Interrupts are enabled under program control with two instructions: EI
(Enable Interrupt) and SIM (Set Interrupt Mask).
RST 7.5: This is positive-edge sensitive and can be triggered with a short pulse. The
request is stored internally by the D flip-flop until the microprocessor responds to eh request
or until it is cleared by Reset or by bit D4 in SIM instruction.
RST 6.5 & RST 5.5: These interrupts are level sensitive, meaning that the triggering level
should be on until the microprocessor completes the execution of the current instruction. If
the microprocessor is unable to respond to these requests immediately, they should be stored
or held by external hardware.

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SIM Instruction

This is a multipurpose 1-byte instruction and used to implement the 8085 interrupts (RST 7.5,
6.5 & 5.5) and Serial Data Output (SOD). SIM Instruction can be used fro three different
functions:

 One function is to set mask for RST 7.5, 6.5 & 5.5 interrupts. This instruction reads the
content of the accumulator and enables or disables the interrupts according to the content of
the accumulator. Bit D3 is a control bit and should be equal to logic level 1 for bits D0, D1
and D2 to be effective. Logic 0 on D0, D1 and D2 will enable the corresponding interrupts and
logic 1 will disable the interrupts.

 The second function is to reset RST 7.5 flip flop. Bit D4 is additional control for RST 7.5. If
D4 = 1, RST 7.5 is reset. This is used to override or ignore RST 7.5 without servicing it.

 The third function is to implement serial I/O. Bits D7 and D6 of the accumulator are used for
serial I/O and do not affect the interrupts. Bit D6 = 1 enables the serial I/O and bit D7 is used
to transmit (output) bits.

The instruction interprets the accumulator contents as follows:

D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE XXX R 7.5 MSE M 7.5 M 6.5 M 5.5

Serial Serial Don’t Reset Mask Masks

Output Data Care RST 7.5 Set Interupts
Data Enable flip flop Enable If Bits = 1
1 = Enable if D4 = 1 If D3 = 1
2 = Disable

Fig: SIM Instruction

Because there are several interrupt lines, when one interrupt request is being served, other
interrupt requests may occur and remain pending. The 8085 has an additional instruction called
RIM (Read Interrupt Mask) to sense these pending interrupts.

The functions of RIM instruction is discussed below:

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RIM Instruction

This is also multipurpose 1 byte instruction used to read the status of interrupts RST 7.5, 6.5
& 5.5 and to read serial data input bit. RIM instruction can be used for the following functions:

 This instruction loads the accumulator with 8-bits indicating the current status of the
interrupt masks.

 Bit D4, D5 and D6 identify the pending interrupts.

 To receive serial data Bit D7 is used.

The RIM instruction loads eight bits in the accumulator with the following interpretations.

D7 D6 D5 D4 D3 D2 D1 D0
SID I7 I6 I5 IE 7.5 6.5 5.5

Serial Interrupt Interrupt Interrupt

Input Pending Enable masked
Data If bits = 1 Flip flop If bits = 1
is set
If bit = 1

Fig: RIM Instruction

Interrupt Priority

Since, the 8085 has five interrupt lines (TRAP, RST 7.5, RST 6.5, RST 5.5 & INTR). We
know all the interrupts can be masked except TRAP. Microprocessor responses to interrupt
instantly when interrupt request appears on one of interrupt line. If two or more than two
interrupts request appears at the same time, there will be confusion for the microprocessor that
which request to serve first. But this problem is solved by assigning priority to each interrupt
lines. The TRAP has highest priority followed by RST 7.5, RST 6.5, RST 5.5 & INTR
respectively.

Data transfer between the CPU and an I/O device is initiated by the CPU. However, the CPU
cannot start the transfer unless the device is ready to communicate with the CPU. The readiness
of the device can be determined from and interrupt signal. The CPU responds to the interrupt
request by storing the return address from PC into a memory stack and then the program
branches to a service routine that process the required transfer.

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In microcomputer a number of I/O device are attached to the processor, with each device
being able to originate an interrupt request. The first task of the interrupt system is to indemnify
the source of the interrupt. There is also the possibility that several sources will request service
simultaneously. In this case the system must also decide which device to service first.

An interrupt priority is a system that established a priority over the various sources to
determine which condition is to be serviced first when two or more request arrive
simultaneously. The system may also determine which conditions are permitted to interrupt the
computer while another interrupt is being serviced. Higher-priority interrupt levels are assigned
to request which, if delayed or interrupted, could have serious consequences. Device with higher
speed transfers such as magnetic disks are given high priority, and slow devices such as
keyboards receive low priority. When two devices interrupt the processor at the same time, the
processor services the device with the higher priority at first.
There are mainly two ways of servicing multiple interrupts, they are: Polled Interrupt and
Chained (Vectored) Interrupt. The details on these two categories are explained later.

Interrupts Response
An interrupt is considered to be an emergency signal that may be services. The
microprocessor may respond to it as soon as possible. Responding to an interrupt may be
immediate or delayed depending on whether the interrupt is Maskable or Non Maskable and
whether interrupts are being masked or not.

What happens when microprocessor is interrupted?

When the microprocessor receives an interrupt signal, it suspends the currently executing
program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt.
Each interrupt will most probably have its own ISR. When a device interrupts, it actually wants
the microprocessor to give a service which is equivalent to asking the microprocessor to call a
subroutine.

The 8085 interrupt process can be summarized as follows:

Step 1: The interrupt process should be enabled by writing the instruction EI in the main
program.
Step 2: MPU checks the INTR line during the execution of each instruction.
Step 3: If INTR line is high and interrupt is enabled, MPU completed the current instruction,
disable the interrupt and sent an acknowledge signal INTA.
Step 4: The signal INTA is used to insert a restart (RST) instruction through external hardware.
The RST instruction transfers the program control to specific memory location.
Step 5: When microprocessor receives RST instruction, it saves the memory address of next
instruction on the stack. The program control is transferred to call location.
Step 6: The ISR perform the specific task of the interrupt. The ISR must include EI instruction
to enable the interrupt.
Step 7: At the end of ISR, the RET instruction returns the memory address from where the
program was interrupted and continues the execution.

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Interrupt Service Routine (ISR) & Its Requirements

A special program caused to service an interrupt request is called Interrupt Service Routine
(ISR). When interrupt occurs, the CPU reads the ISR address from Interrupt Vector Table and
program ntrol transfers to ISR. The ISR then saves the processor registers on the stack and body
of ISR executes. When it finishes, the registers are restored and the instruction RET at the end of
ISR returns the program control from where it is interrupted.
Interrupt increases the efficiency of a computer system because the external devices require
the attention of the processor as needed. If the system had no interrupt, the processor would
have to poll every device in the system periodically to see if any of then required attention.
Many of the standard I/O devices generate interrupts, when they need the processor to process
data being received by or being sent by these interfaces.
As interrupt is a process of getting attention of microprocessor to perform some task while it
is busy in doing something else. The task or routine that the microprocessor executes in
response to interrupt is termed as Interrupt Service Routine (ISR).
Before executing the ISR, the microprocessor needs to save the required information to
resume the current program after executing the ISR. So the fundamental requirement of the ISR
is that it should begin by saving the contents of all registers and flags. After the completion of
the ISR, it needs to restore all the registers before returning to main program.

Call & Return Instructions

Call and Return instructions are associated with the subroutine technique. A ‘Subroutine’ is
a group of instructions that performs a subtask. The subroutine is written as a separate unit,
apart from the main program and the microprocessor transfer the program execution from the
main program to the subroutine, whenever it is called to perform the task. After the completion
of the subroutine task the microprocessor return to the main program. The subroutine technique
eliminates the need to write a subtask repeatedly; thus it uses memory more efficiently. Before
implementing the subroutine technique, the stack must be defined. This stack is used to store the
memory address of the instruction in the main program that follows the subroutine call.

The 8085 microprocessor has two instructions to implement subroutine: CALL (call a
subroutine) and RET (return to main program from subroutine). The CALL instruction is used in
the main program to call a subroutine and RET instruction is used at the end of the subroutine to
return to the main program. When a subroutine is called, the contents of program counter, which
is the address of the instruction following the CALL instruction is stored in the stack and the
program execution is transferred to the subroutine address. When the RET instruction is
executed at the end of the subroutine, the memory address stored in the stack is retrieved and the
sequence of execution is resumed in the main program.

Consider the following assembly language program, which illustrate what happens when the
CALL and RET instructions are used.

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4000 LXI SP, 4400H ; Main Program

4003 MVI A, 05H
4005 MVI B, 06H
4007 ADD B
4008 CALL 4050H
400B OUT PORT A
400D HLT

4050 MVI C, FFH ; Subroutine

4052 DCR C
4053 JNZ 4052
4056 RET

The main program is loaded within the address of 4000H to 400DH. The subroutine starts
from address 4050H and ends at 4056H. The first instruction LXI SP, 4400 in the main program
initializes the stack pointer register as shown in figure below:

43FC
43FD
43FE
43FF
4400 SP

The stack pointer points to memory location whose address is 4400H, after execution of
instruction LXI SP, 4400H. From address 4008H to 400AH, the 3-byte CALL instructions is
loaded, which specifies the address of the first instruction of the subroutine to be 4050H. The
address of the next instruction following the CALL instruction is 400BH, which is the content of
program counter at the instant when CALL instruction is executed.

At the instant of execution of CALL instruction PC = 400BH. After the execution of CALL
instruction, the contents of PC will be loaded to the top of stack. In this process, the stack
pointer decrements by one and pointes to 43FFH and the higher order address (higher byte) of
program counter which is 40 in this case will be loaded at this address. Then the stack pointer
further decrements by one and the lower order address (lower byte) of program counter which is
0B in this case will be loaded to the address 43FE. So the new address of stack pointer will be
43FE.

43FC
43FD
43FE 0B SP
43FF 40
4400

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The next thing that will happen after execution of CALL at address 4008 is that the program
counter will be loaded with the address 4050H and the sequence of program transfers to the
address 4050H where the microprocessor executes its first instruction. At the end of the
subroutine there is RET instruction. After execution of RET the following things will happen:
The microprocessor pops off the data, which is actually the address of the next instruction
following the CALL instruction in the main program and loads into the program counter. The
program counter first gets loaded with the data 0B of the memory location 43FE where the stack
pointer is currently pointing. The stack pointer then increments by on and points to memory
location 43FF, whose contents is 40. The program counter is then loaded with this higher order
address so that the 16-bit loaded address of PC will become 4000B and the stack pointer will be
again incremented by one. So execution of RET transfer the sequence of program control to the
main program from the subroutine. So this is the process how the program control switches
between the main program and subroutine when CALL and RET instruction is executed.

Interrupt Structure

The 8085 Interrupt Structure is shown in figure below. In order to enable the interrupt, we
use the instructions EI and SIM. The execution of EI instruction sets the RS flip flop and makes
one of the inputs to the AND gate 1 to 4 HIGH. Hence, in order for all the interrupts (except
TRAP) to work, the interrupt system must be enabled.

Priority Input Pin Mask Vector Location

1
D Q
2 RST 7.5 003C16
Q
CLR

Reset
003816
RST 7.5 Interrupt Recognized

3 RST 6.5
003416

003016

4 RST 5.5
002C16

002816

1 TRAP 002416

002016

EI S Q 001816
DI
Reset R Interrupt 001016
Any Interrupt Recognized Enable
Get RST
000816
Code from
External
5 INTR 000016
Hardware

Fig: The 8085 Interrupts and Vector Locations

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 Consider only the RST 7.5 Interrupt is to be enabled, the interrupt mask bit for RST 7.5 is set
to low, making the two inputs to AND gate 1 HIGH. Now, if there is the interrupt signal to
RST 7.5 pin, it sets the D flip flop, thus making the O/P of AND gate 1 HIGH and enables
RST 7.5.
 The 8085 branches to location 003CH to service routine.
 RST 6.5 and RST 5.5 can be similarly explained.
 Execution of the DI instruction clears RS flip flop and disables all the interrupts except
TRAP.

A microprocessor may be connected to more than one peripheral and most of the peripherals
can originate an interrupt request. But there are only five interrupt input lines in 8085
microprocessor. So, more than one device needs to be connected in the single interrupt line.
When the interrupt request generates in such line, first of all microprocessor needs to identify
the interrupting device, so to handle this problem microprocessor provides two approaches:
 Polling
 Chaining

Polling
Polling is the software approach used to identify the interrupting device on the priority basis.
In this method, when an interrupt generates, the execution control transfers to one common
branch address and execute one general initial service routine for all devices. All the devices
connected to the single interrupt request lines are polls in sequence. The order in which they are
polled or tested determines the priority of each device.
The highest priority device is polled first and if this device has generates the interrupt, the
execution control branches to the service routine for that device. Otherwise, the next or second
higher priority device is tested and so on.
Polled interrupt is very simple but for a large number of devices, the time required to poll
each device may exceed the time to service the device. In such case, the faster mechanism called
vectored or chained interrupt is used.

PBN
PAN

PB2
 PA2
P PB1
PA1

Device 1 Device 2 Device N

INTR

Fig: Polled Interrupt

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Chaining
Chaining is the hardware approach used to identify the interrupting device on the priority
basis. In this method, there is one common interrupt request line through which all the devices
connected to it request the interrupt. Two or more devices that can originate the interrupt are
connected in series as shown below:

INTR

Device 1 Device 2 Device N

 INTA

P

Hardware for Generating the

D0-D7
Interrupt Vector Address

Fig: Chained Interrupt

When a device requests an interrupt, the microprocessor issues the INTA (Interrupt
Acknowledge) signal in response. The INTA signal is first received by highest priority device,
which is device 1 in this case. If the device has generated the interrupt, it will accept the INTA
signal and place the vectored/transferred address on data bus. Otherwise, it will pass the INTA
signal to next device until the INTA signal is accepted by the interrupting device.
The word or address placed on data bus is referred to as vector, which the microprocessor
uses as a pointer to points the appropriate device service routine. This avoids the need to execute
a general initial service routine first as in the case of polling.

Summary

The 8085 interrupts and their requirements are listed in the table below in order of their
priority. TRAP has the highest priority and INTR has the lowest priority. It must be emphasized
that an interrupt can be recognized only if the HOLD signal is inactive.
Interrupts Type Instructions Hardware Trigger Vector
Non No External Level & Edge
TRAP Independent of EI & DI 0024H
Maskable Hardware Sensitive
Controlled by EI & DI No External
RST 7.5 Maskable Edge Sensitive 003CH
Unmasked by SIM Hardware
Controlled by EI & DI No External
RST 6.5 Maskable Level Sensitive 0034H
Unmasked by SIM Hardware
Controlled by EI & DI No External
RST 5.5 Maskable Level Sensitive 002CH
Unmasked by SIM Hardware
RST Code from 0038H
INTR Maskable Controlled by EI & DI Level Sensitive
External Hardware 0000H
Table: Summary of Interrupts in 8085A Microprocessor

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8086 Interrupt System

The 8086 assigns every interrupts a type code so that the 8086 can identify it. Interrupts can
be initiated by:
o External Devices
o Internally]
o By S/W Instructions
o Exceptional Condition such as Divide by 0, Overflow etc.

The 8086 interrupts can be classified into three types.

o Pre Defined Interrupts
o User Defined Software Interrupts
o User Defined Hardware Interrupts

Pre Defined Interrupt

The pre defined interrupts are called so because the interrupt vectors for these five interrupts
types (which are reserved fro specific functions) are predefined by INTEL. They are:
Type 0: INT 0 Divide by Zero
Type 1: INT 1 Single Step
Type 2: INT 2 Non Maskable Interrupt (NMI Pin)
Type 3: INT 3 Break Point
Type 4: INT 4 Interrupt on Overflow

The user must provide the desired IP and CS values in the interrupt pointer table. The user
may also initiate these interrupt through H/W or S/W.

Type 0: INT 0 (Divide by Zero)

This interrupt occur whenever the result of division overflow or whenever an attempt is
made to divide by zero. It is Non Maskable.

Type 1: INT 1 (Single Step)

This occurs after the execution of each instruction if the TRAP flag bit is set. This is used to
execute program one instruction at a time.

Type 2: INT 2 (Non Maskable Interrupt) (NMI Pin)

It is initiated via the 8086 NMI pin. It is normally used for power failure. The 8086 obtains
the interrupt vector address by automatically executing the INT 2 instruction internally.

Type 3: INT 3 (Break Point)

It is used to set break point in a program for debugging.

Type 4: INT 4 (Interrupt on Overflow)

This interrupt occurs if the overflow flag is set and the INT 0 instruction is executed.

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User Defined Software Interrupts

The user can generate an interrupt by execution a two byte interrupt instruction, INT N
(Where, N = 0 to FFH). The INT N is not Maskable by interrupt enable flag (IF). The INT N
instruction can be used to test an interrupt service routine for external interrupts.

User Defined Hardware Interrupts

The 8086 Maskable Interrupts are initiated via the INTR pin. These interrupts can be enabled
or disabled by STI: Set Interrupt Flag (IF = 1) or CLI: Clear Interrupt Flag (IF = 0) respectively.
If (IF) = 1 and INTR is active without the occurrence of any other interrupts, the 8086, after
completing the current instructions generates INTA low twice. INTA is only generated by 8086
in response to INTR.
First Pulse INTA, tells to Get Ready
Second Pulse INTA, Interrupt Type is sent.

Interrupt Vector & Interrupt Vector Table

An Interrupt Vector is a 4-byte number stored in the first 1024 bytes of memory 000000H –
0003FFH. These are 256 different d\interrupt vectors and each vector contains the address of an
interrupt service routine. Each vector contains the value for the IP and CS that form the address
of the interrupt service routine. The first two bytes contain IP and last two bytes contain CS.

The Interrupt Vector Table is a table which stores the interrupt vectors for 256 interrupts. It
is located in first 1024 bytes of memory at address 000000H-0003FFH. The lowest five types are
dedicated to specific interrupt (Pre-defined Interrupts). Interrupt type 5 to 31 are reserved by the
INTEL. Interrupt type 32 to 255 are available for user interrupt (Hardware & Software
Interrupts).

Interrupt Procedures in 8086

Once the 8086 has the interrupt-type code (via the bus for H/W Interrupts, from S/W
Interrupt Instructions INT N or from the Predefined Interrupts), the type code is multiplied by 4
to obtain the corresponding interrupt vector in the Interrupt Vector Table.
 The Interrupt Vector consists of IP and CS.
 During the transfer of control, 8086 pushes the Flags and current Code Segment Register and
Instruction Pointer onto stack.
 The new CS and IP values are loaded.
 The flags TF and IF are cleared to 0.
 No segment registers are used when accessing the Interrupt Pointer Table.

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The 8259A Programmable Interrupt Controller (PIC)

The 8259A is a Programmable Interrupt Controller designed to work with INTEL
Microprocessors: 8085, 8086 and 8088. The 8259 Interrupt Controller can:
 Manage eight interrupts according to the instructions written into its control registers. This is
equivalent to providing eight interrupt pins on the processor in place of one INTR (8085) pin.
 Vector an interrupt request anywhere in memory map. However, all eight interrupts are spaced at the
interval of either four or eight locations. This eliminates the major drawback of the 8085 interrupts in
which all interrupts are vectored to memory location on page 00H.
 Resolve eight levels of interrupt priorities in a variety of modes, such as fully nested mode,
automatic rotation mode, and specific rotation mode.
 Mask each interrupt request individually.
 Read the status of pending interrupts, in-service interrupts, and masked interrupts.
 Be set up to accept either the level-triggered or the edge-triggered interrupt request.
 Be expanded to 64 priority levels by cascading additional 8259As.
 Be set up to work with either the 8085 microprocessor mode or the 8086/8088 microprocessor mode.

Block Diagram of 8259A PCI

The following figure shows the Internal Block Diagram of the 8259A. It includes eight
blocks: Control Logic, Read/Write Logic, Data Bus Buffer, Three Registers (IRR, ISR and IMR),
Priority Resolver and Cascade Buffer. This diagram shows all the elements of a programmable
device plus additional blocks. The functions of some of these blocks are explained below:

Read/Write Logic
This is a typical Read/Write control logic. When the address line A0 is at logic 0, the
controller is selected to write a command or read a status. The Chip Select Logic and A0
determine the port address of the controller.

Control Logic
This block has two pins: INT (Interrupt) as an output and INTA (Interrupt Acknowledge) as
an input. The INT is connected to the interrupt pin of the MPU. Whenever a valid interrupt is
asserted, this signal goes high. The INTA is the Interrupt Acknowledge signal from the MPU.

Interrupt Registers & Priority Resolver

The Interrupt Request Register (IRR) has eight input lines (IR0-IR7) for interrupts. When
these lines go high, the requests are stored in the register. The In-Service Register (ISR) stores
all the levels that are currently being serviced, and the Interrupt Mask Register (IMR) stores the
masking bits of the interrupt lines to be masked. The Priority Resolver (PR) examines these
three registers and determines whether INT should be sent to the MPU.

Cascade Buffer/Comparator
This block is used to expand the number of interrupt levels by cascading two or more
8259As.

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INTA INT

D7-D0 Data
Bus Control Logic
Buffer

Internal Data Bus

RD IR0
IR1
Read/Write IR2
WR
Control Interrupt
In-Service IR3
Logic Priority Request
A0 Register
Resolver Register IR4
(ISR)
(IRR)
IR5
IR6
IR7
CS

CAS 0
Cascade Internal Mask Register
CAS 1 Buffer/ (IMR)
CAS 2 Comparator

SP/EN

Fig: Block Diagram of 8259A PCI

Interrupt Operation
To implement interrupts, the Interrupt Enable flip flop in the microprocessor should be enabled by
writing the EI instruction and the 8259A should be initialized by writing control words in the control
register. The 8259A requires two types of control words: Initialization Command Words (ICWs) and
Operational Command Words (OCWs). The ICWs are used to set up the proper conditions and specify
RST vector addresses. The OCWs are used to perform functions such as masking interrupt, setting up
status-read operations etc. After the 8259A is initialized, the following sequence of events occurs when
one or more interrupt request lines go high.
 The IRR stores the requests.
 The Priority Resolver checks three register: the IR for interrupt requests, the IMR for masking bits
and the ISR for the interrupt request being served. It resolves the priority and sets the INT high
when appropriate.
 The MPU acknowledges the interrupt by sending INTA.
 After the INTA is received, the appropriate priority bit in the ISR is set to indicate which interrupt
level is being served, and the corresponding bit in the IRR is reset to indicate that the request is
accepted. Then the Opcode for the CALL instruction is placed on the data bus.
 When the MPU decodes the CALL instruction, it places two more INTA signals on the data bus.
 When the 8259A receives the second INTA, it places the low order byte of the CALL address on the
data bus. At the third INTA, if places the high order byte on the data bus. The CALL address is the
vector memory location for the interrupt; this address is placed in the control register during the
initialization.
 During the third INTA pulse, the ISR bit is reset either automatically (Automatic-End-of-Interrupt-
AEOI) or by a command word that must be issued at the end of the service routine (End-of-
Interrupt-EOI). This option is determined by the initialization command word (ICW).
 The program sequence is transferred to the memory location specified by the CALL instruction.

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Programming Exercises
Contents:

o Programming with 8085: Examples

o Programming with 8086: Examples

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Programming with 8085

Example: The Most & Frequently Asked Problems & Their Solutions

Que. 1 Add two numbers stored at memory location 2040h and 2041h and store the result
at memory location 2042h.

Label Mnemonics Comments

LXI H, 2040h (H)(L) = 2040h
MOV A, M (A)  ((H)(L))
INX H Point to Next Data
ADD M (A) = (A) + ((H)(L))
INX H Store Data in Next Memory Location.
MOV M, A ((H)(L))  A
HLT

Que. 2 Clear the memory locations from 2040h to 204Fh.

Label Mnemonics Comments

LXI H, 203Fh (H)(L) = 203Fh (As a Pointer)
MOV C, M C as a Counter
XRA A A=0
Loop INX H Increment Pointer
MOV M, A ((H)(L))  A
DCR C Decrement Counter
JNZ Loop Continue if Counter ≠ 0

Que. 3 Sum the given series of numbers. The length is given in memory location 203Fh and
the series itself starts from 2040h. Store the result at 2060h.

Label Mnemonics Comments

LXI H, 203Fh (H)(L) = 203Fh (As a Pointer)
MOV C, M C as a Counter
XRA A Sum = 0
Loop INX H Increment Pointer
ADD M (A)  (A) + ((H0(L))
INX H Increment Pointer
DCR C Decrement Counter
JNZ Loop Continue if Counter ≠ 0
STA 2060h Store Result
HLT

Que. 4 Write a program to find the square of a given number.

Label Mnemonics Comments
LXI D, 2060h (D)(E) = 2060h (Base Address)
LDA 2040 Get Data
MOV L, A Prepare H & L to
MVI H, 00h Base Address
DAD D Get Effective Add. In H & L
MOV A, M Get Result in A
STA 2042h Store the Result
HLT

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Que. 5 Find the maximum in a given series of data. The length is given in memory location
203Fh and the series itself starts from 2040h. Store the result at 2060h.

Label Mnemonics Comments

LXI H, 203Fh (H)(L) = 203Fh (As a Pointer)
MOV C, M C as a Counter
DCR C Comparison is 1 Less
XRA A Maximum = 0
Loop INX H Increment Pointer
CMP M Compare Acr with Next Data
JNC Next Jump If No Change
MOV A, M Change If Acr Less
Next DCR C Decrement Counter
JNZ Loop Continue if Counter ≠ 0
STA 2060h Store Result
HLT

Que. 6 Write a program to copy 16 data from 2040h onwards to 2060 onwards.

Label Mnemonics Comments

LXI H, 203Fh (H)(L)=203Fh (As a Pointer 1)
MOV C, M C as a Counter
LXI D, 2060h (D)(E)=2060h (As a Pointer 2)
Loop MOV A, M (A)  ((H)(L))
STAX D (A)  ((D)(E))
INX H Increment Pointer 1
INX D Increment Pointer 2
DCR C Decrement Counter
JNZ Loop Continue if Counter ≠ 0
HLT

Que. 7 Write a program to Ex-or two data without using Ex-or instruction.

Label Mnemonics Comments

LXI H, 2040h (H)(L)=2040h
MOV A, M (A)  ((H)(L))
MOV B, A Keep a Copy in Register B
CMA Complement contents of Acr
INX H Point to Next Mem. Location
ANA M AND the Acr with 2nd Data
MOV C,A Put ANDed Result in Reg: C
MOV A,M 2nd Number in Acr
CMA Complement contents of Acr
ANA B AND Acr with 1st Data
ORA C OR the contents of Acr with the Contents of Reg: C
INX H Point to Next Mem. Location
MOV M, A Store the Result
HLT

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Que. 8 Write a program to generate the Fibonacci Series.

Label Mnemonics Comments

LXI H, 203Fh (H)(L)=203Fh
MOV C, M (C)  ((H)(L)) (As a Counter)
INX H Point to First Data
MOV A, M (A)  (303Fh)
INX H Point to Next Data
Loop ADD M (A) = (A) + (203Fh)
INX H Point to Next Mem. Loc. For
MOV M, A Storing Next Fibonacci No
DCX H Get Previous Fibonacci No
MOV A, M (A)  ((H)(L))
INX H Point to Latest Fibonacci No
DCR C Decrement Counter
JNZ Loop Continue if Counter ≠ 0
HLT

Que. 9 Find the number of negative, positive and zero elements in a given series of data.
The length is given in memory location 203Fh and the series itself starts from 2040h. Store the
result at 2060 onwards.

Label Mnemonics Comments

LXI H, 203Fh (H)(L)=203Fh (As a Pointer 1)
MOV C, M C as a Counter
XRA A Clear Acr
MOV B, A No of Positive Element = 0
MOV D, A No of Negative Element = 0
MOV E, A No of Zero Element = 0
Loop INX H Increment Pointer
CMP M Compare Acr with Next Data
JNZ Neg Jump If No is Negative
INR E Increment Zero Counter
JMP Ahead Check Next Number
Neg MVI A, 7Fh Max, +Ve No for Comparison
CMP M Compare Acr with Next Data
JNC Pos If No Carry, Increment +Ve Counter
INR D Else Increment -Ve Counter
Pos INR B Increment +Ve Counter
Ahead XRA A Initialize Acr for Next Comparison
DCR C Decrement Counter
JNZ Loop Continue if Counter ≠ 0
LXI H, 2060h Pointer to Store Data
MOV M, B Store +Ve Counter
INX H Increment Pointer
MOV M, D Store –Ve Counter
INX H Increment Pointer
MOV M, E Store Zero Counter
HLT

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Que. 10 Write a program to multiply 05h and 08h.

Label Mnemonics Comments

MVI A, 00h Clear the Acr Contents.
MVI B, 08h (B)  08h
MVI C, 05h (C)  05h (As a Counter)
Loop ADD B (B) + (A)
DCR C Decrement Counter
JNZ Loop Continue if Counter ≠ 0
STA C000h Store the Result

Que. 11 Sort the given list in ascending order. The length of the series is given memory
location 203Fh and the series itself starts from 2040 onwards.

Label Mnemonics Comments

LXI H, 203Fh (H)(L)=203Fh (As a Pointer 1)
MOV C, M C as a Counter
DCR C Comparison is 1 Less
MOV B, C Keep a Copy in Reg: B
INX H Get Starting Address of Data
Loop MOV A, M Assume First Data is Lowest
INX H Increment Pointer
CMP M Compare A with M
JC Next If (A)<((H((L)), Interchange
MOV D, M Contents of Two Memory
MOV M, A Location
DCX H Decrement Pointer
MOV M, D ((H)(L))  D
INX H Increment Pointer
Next DCR B Decrement Counter
JNZ Loop Continue if Counter ≠ 0
MOV C, B Repeat It for One Less
JNZ Again Jump to Again if Counter ≠ 0
HLT
Again LXI H, 2040h ((H)(L))  2040h
JMP Loop Continue if Counter ≠ 0

Que. 12 Write a program to display the absolute value.

Label Mnemonics Comments

MVI A, Any Get Any Data Byte.
ORA A Flag Set
JM Loop Jump on Minus to Loop
OUT 01h Display at Port 1
HLT
Loop CMA Find 2’s Complement
ADI 01h
OUT 01h
HLT

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Que. 13 Convert binary number stored at 2040h to 4 digit BCD number. Store the BCD result
at 2041h and 2042h.

Label Mnemonics Comments

LDA 2040h (A) = 2040h
MOV B, A Keep a Copy in Reg: B
LXI D, 0000h BCD Number = 0
MVI C, FFh C  FFH
ANA C If Number = 0 then
JZ Done Conversion Not Needed
Loop DCR B Decrement Binary Counter
MOV A, E Increment BCD Counter in
INRA BCD Mode
DAA Decimal Adjust Acr
MOV E, A (D)  (A)
JNC Next If No Carry Jump to Next
INR D Increment MSD (BCD)
Next MOV A, C Repeat the Loop until No = 0
ANA B AND B with Acr Contents
JNZ Loop Continue if Counter ≠ 0
XCHG Exchange DE & HL Reg:Pair
Done SHLD 2041h (L) (2041h), (H) (2042h)
RST 1

Que. 14 Writer a program to load the data byte A8H in register C. Mask the high order bit and
display the low order bits at a output port.

Label Mnemonics Comments

MVI C, A8h C  A8h
MOV A, C AC
ANI 0Fh Mask (D7 – D4)
OUT Port 1 Display at Port 1
HLT

Que. 15 Write instructions to read the input port and continue to read it until both switches
are closed. When both switches are closed, turn on LEDS.

Label Mnemonics Comments

IN 2FH Read Input Port
ANI 00000011B Mask all bits except D1 & D0.
JNZ Start If a switch is open, reads again
OUT 8FH Turn on all LEDS
HLT

Que. 16 When all of 8 switches are off, the microprocessor reads data FFh and when a switch
is turned on, it goes to logic 0 (for all switches on, the data will be 00h). Write instruction to
read input port and if all switches are open, set zero flag.

Label Mnemonics Comments

IN 07h Port Address
CMA Complement data from port 07h
ORA A Set zero flag, if all switches are open.
HLT

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Programming with 8086

Example: The Most & Frequently Asked Problems & Their Solutions

Que. 1 Find the largest number from a Que. 2 Find the smallest number from
table of 10 bytes. a table of 10 bytes.

TITLE: Obtaining Smallest Number in a Table TITLE: Obtaining Smallest Number in a Table
Using Bubble Sorting Algorithm Using Bubble Sorting Algorithm
.MODEL SMALL .MODEL SMALL
.STACK 32 .STACK 32
.DATA .DATA
TABLE DB 01, 21, 32, 26, 57, 64, 79, 50, 33, 42 TABLE DB 01, 21, 32, 26, 57, 64, 79, 50, 33, 42
LARGE DB? SMALL DB?
COUNT DW 0010 COUNT DW 0010
.CODE .CODE
MAIN PROC FAR MAIN PROC FAR
MOV AX, @Data MOV AX, @Data
MOV DS, AX MOV DS, AX
MOV SI, 00 MOV SI, 00
MOV CX, COUNT MOV CX, COUNT
MOV DL, 0FFH MOV DL, 0FFH
L1: L1:
MOV AL, TABLE [SI] MOV AL, TABLE [SI]
INC SI INC SI
CMP DL, AL CMP DL, AL
JAE Next JB Next
MOV DL, AL MOV DL, AL
Next: Next:
LOOP L1 LOOP L1
MOV LARGE, DL MOV SMALL, DL
MOV AX, 4C00H MOV AX, 4C00H
INT 21 H INT 21 H
MAIN ENDP MAIN ENDP
END MAIN END MAIN

Prepared By: SriKisna Khadka 145

2006 Batch
 HWHIC

…
BLEX
Microprocessor

Que. 3 Suppose you have two tables of Que. 4 Arrange the numbers of a table
10 unsigned integers (mad allowed being in ascending order.
255), find the sum of all ten numbers in
each table and store the greatest of the two TITLE: Arranging the Numbers of a Table in
sums in memory. Ascending Order Using Bubble Sorting.
.MODEL SMALL
TITLE: Add Corresponding Bytes of Two Tables .STACK 32
of 10 Bytes And Store the Result in The Third .DATA
Table. TABLE DB 34, 31, 32, 36, 33, 38, 39, 30, 37, 35
.MODEL SMALL COUNT DW 0010
.STACK 32
.DATA .CODE
TABLE1 DB 1,2,3,2,5,6,7,5,3,4 MAIN PROC FAR
TABLE2 DB 3,4,5,2,6,7,8,6,4,2 MOV AX, @Data
SUM1 DB? MOV DS, AX
SUM2 DB? MOV SI, 00 ; SI => int i = 0
LARGE DB? MOV DI, 00 ; DI => int j = 0
COUNT DW 10 ; for(i=o; i<10;i++) // Outer Loop
.CODE ; for(j=i+1; j<10;j++) // Ineer Loop
MAIN PROC FAR ; if(TABLE[j] < TABLE [i])
MOV AX, @DATA swap (TABLE[j],TABLE[i]);
MOV DA, AX ; // End of Inner Loop
MOV BX, 00 ; // End of Outer Loop
MOV CX, COUNT ; Outer Loop Initialization
MOV AH, 00 MOV CX, COUNT
MOV DL, 00 DEC CX
L1: ; Outer Loop Begin
MOV DL, TABLE1 [BX] Outer Loop:
ADD AH, DL ; Inner Loop Initialization
INC BX MOV BX, SI
LOOP L1 INC BX
MOV SUM1, AH MOV DI, BX
MOV BX, 00 ; Inner Loop Begin
MOV CX, COUNT Inner Loop:
MOV AH, 00 MOV DL, TABLE[DI]
MOV DL, 00 MOV DH, TABLE[SI]
L2: CMP DL, DH
MOV DL, TABLE2 [BX] JAE Skip_swap
ADD AH, DL CALL SWAP
INC BX MOV TABLE[DI],DL
LOOP L2 MOV TABLE[SI},DH
MOV SUM2, AH Skip_swap
MOV DL, SUM1 INC DI
MOV DH, SUM2 CMP DI, 1
MOV LARGE, DL JB Inner Loop
CMP DL, DH ; Inner Loop Ends
JAE EXIT INC SI
MOV LARGE, DH Loop Outer Loop
EXIT: ; Outer Loop Ends
MOV AX, 4C00H MOV AX, 4C00H
INT 21H INT 21H
MAIN ENDP
MAIN ENDP
SWAP PROC NEAR
END MAIN
MOV AL, DL
MOV DL, DH
MOV DH, AL
RET
SWAP ENDP
END MAIN

Prepared By: SriKisna Khadka 146

2006 Batch

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