Scribd
Upload
55 views

FPGA Final FA20

The document provides instructions for a take-home final exam on FPGA system design. It includes 4 questions related to Verilog coding of basic digital circuits and finite state machines. Students are asked to write code, draw diagrams, and explain concepts. Submissions are due by a specified date and time through an online system.

Uploaded by

Maryam Qazi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
55 views

FPGA Final FA20

The document provides instructions for a take-home final exam on FPGA system design. It includes 4 questions related to Verilog coding of basic digital circuits and finite state machines. Students are asked to write code, draw diagrams, and explain concepts. Submissions are due by a specified date and time through an online system.

Uploaded by

Maryam Qazi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

Final-Term Exam (Take-Home) Fall – 2020

Faculty of Engineering Sciences and Technology

Subject: FPGA Based System Design Submission Day: Saturday


Instructor: Muhammad Amin Qureshi/ Syed Rizwan
Submission Date: 30th January 2021, 10AM
Program: BE (EE), BS (CS/SE) Max. Marks: 40 (Scaled up to 50 for BE)

Please follow the instructions carefully:

1. Write your answers in a Word file and upload the file before the due date on Blackboard.
2. Write your name and registration ID on the first page of your Word file.
3. Answer scripts can only be uploaded on Blackboard any time before its deadline.
4. To avoid any unforeseen problems, you are advised NOT to wait for the last hour to
upload your answer script.
5. Submission of answer copy(ies) will be considered acceptable through Blackboard only.
Therefore, do not submit your document through email or any other medium.
6. Use 12 pt. font size and Times New Roman font style along with 1-inch page margins.
7. Follow the requirements of the word limit and the marking criteria while writing your
answers.
8. Provide relevant, original and conceptual answers, as this exam aims to test your ability to
examine, explain, modify or develop concepts discussed in class.
9. Do not copy answers from the internet or other sources. The plagiarism of your answers
may be checked through Turnitin.
10. Recheck your answers before the submission on BlackBoard to correct any content or
language related errors.
11. Double check your word file before uploading it on BlackBoard to ensure that you have
uploaded the correct file with your answers.

Page 1 of 4
RUBRIC (Scoring guide)
Correct diagram of the problem 20%

Correct theoretical understanding represented by the answer 30%

Correct Code 50%

Question 1: [5 Marks]
a) Draw the routing structure or networks inferred by the following statements:

if (m==n) wire [1:0] sel;


r=a+b+c; case (sel)
2’b00: r= a+b+c;
else if (m>n) 2’b10: r=a-b;
r=a-b; default: r=c+1;
else endcase
r=c+1;

b) Explain the two types of routing networks inferred by conditional control structures of if
else and case in Verilog HDL.

Question 2: [5 Marks]

Find the errors in the following codes:

a) A modified version of the code for a 2-to-4 decoder is shown below. This code is almost
correct but contains one error. What is the error?

module dec2to4 (W, En, Y);


input [1:0]W;
input En;
output reg [0:3] Y;
integer k;
always @(W, k)
for (k = 0; k < = 3; k = k+1)
if (W == k)
Y[k] = En;
endmodule

b) Following is the code of a 4-bit parallel register. What are the errors?

module Reg4(I, Q, Clk, Rst);

input [3:0] I;

Page 2 of 4
output [3:0] Q;
wire [3:0] Q;
input Clk, Rst;

always @(Clk) begin


if (Rst == 1 )
Q <= 4'b0000;
else
Q <= I;
end
endmodule

c) Using a casex statement (behavioral modeling), write Verilog code for an 8-to-3 priority encoder.
The output “d” is only used to indicate the condition when all inputs are 0. If “d” output is 0, it
means that all inputs are low.

Question 3: [10 Marks]

a) Write the Verilog code and testbench for a 16-bit Serial adder using Moore FSM design
technique.
b) Why are 4 and 5-input LUTs are preferred in FPGAs and why not higher input LUTs like
10 or 12 or much higher not used?
c) What is a tristate buffer and how is it synthesized using Verilog HDL? Explain with the
help of diagram and Verilog code.

Question 4: [10 Marks]

a) Write Verilog code that represents a Toggle flip-flop with an asynchronous clear input.
Use behavioral code, rather than structural code.
b) Write Verilog code that represents a JK flip-flop with synchronous reset. Use behavioral
code, rather than structural code.

Page 3 of 4
c) Draw the block diagram of a 16-bit sign magnitude adder/subtractor using parameter
keyword and write the complete Verilog code.

Question 5: [10 Marks]

Design a system that can be used to control a vending machine with the following specifications.
The circuit has five inputs: Q (quarter or 15 cents), D (dime or 10 cents), N (nickel or 5 cents),
Coin, and Resetn. When a coin is deposited in the machine, a coin-sensing mechanism generates
a pulse on the appropriate input (Q, D, or N). To signify the occurrence of the event, the
mechanism also generates a pulse on the line Coin. The circuit is reset by using the Resetn signal
(active low). When at least 25 cents have been deposited, the circuit activates its output, Z
(which gives out the desired item, coffee for example).

 The machine should not return the change and keep the excess amount deposited if the
amount exceeds the price, i.e. 25 cents and keep this amount for the next user.
 Draw the State Diagram, Block Diagram and write the Verilog code directly. Do not
make the next state table or k-maps.

Page 4 of 4

You might also like