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Parameters Extraction of Semiconductor Devices

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Numerical Simulation of Semiconductors & NanoDevices Chapter 7

Parameters Extraction of
Semiconductor Devices

Contents
7-1. Introduction
7-2. Circuit Models
7-2.1. Large & Small Signal Circuit Models
7-2.2. Y-Parameters of a Device Model
7-2.3. S-Parameters of a Device Model
7-2.4. Minimum Conductance in a Device Model (Gmin)
7-3. Measurement of Device Model Parameters
7-3.1. Measurement of I-V Characteristics
7-3.2. Measurement of C-V Characteristics
7-3.3. Measurement of S-Parameters
7-4. Parameters Extraction & Optimization
7-5. Number of Model Parameters
7-6. Non-Quasi-Static (NQS) Modeling
7-7. Noise Modeling
7-8. Model Characterization
7-8.1. Typical Fitting Procedures
7-8.2. Typical DC Procedures
7-8.3. Typical AC Procedures
7-8.4. Probing on IC
7-8.5. IC Jig De-embedding
7-8.6. Parameter Extraction versus Optimization
7-8.7. Model Accuracy & Benchmark Criteria
7-9. Macromodels
7-10. Compact Modeling
7-11. Examples of Semiconductor Models
7-11.1. Diode Models
7-11.2. Bipolar Transistor Models
i. Ebers-Moll Model
ii. Gummel-Poon (G-P) Model
iii. VBIC Model

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7-11.3. MOS Transistor Models

i. MOS Level-1 Model
ii. BSIM3 Model Parameter Extraction & Optimization
iii. Limitations of BSIM3
iv. BSIM4 Model
v. BSIM5 Model
vi. BSIM-6 Model
vii. BSIMSOI Model
viii. BSIM-MG Model
ix. Comparison between MOSFET Models
7-12. Case Study: Compact Modeling of a CNTFET
7-13. Summary
7-14. Problems
7-15. Bibliography

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CHAPTER 7:

Parameters Extraction of Semiconductor

Devices

7-1. Introduction
The design of semiconductor devices is a complex task that involves many
trade-offs between many objectives (speed, power, etc.), which are often in
conflict. However, the ultimate goal of device simulation is to provide the
device model parameters for circuit simulation. In fact, the analysis of
integrated circuits (IC‘s) by circuit simulators, such as SABER and SPICE1,
demands the specification of the device model parameters. For active devices,
such as transistors or diodes, the circuit models are highly nonlinear. Hence
their parameters cannot be completely determined by direct measurements.

Fig. 7-1. Device modeling and parameters extraction and their associated tasks

1
SPICE (Simulation Program with Integrated Circuit Emphasis) and SABER are general-
purpose circuit simulators. SABER is a proven platform for designing, modeling and
simulating physical systems, which combines VHDL-AMS, Verilog-AMS, SPICE, and the
Saber-MAST language into a single environment. Both are used in IC design to predict and
verify the electronic circuit behavior.
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The goal of parameter extraction (PEX) is to determine the device model

parameters that minimize the differences between a set of measured
characteristics and the device model. This minimization process is often called
fitting of model characteristics to the measurement data. Generally speaking,
there are two methods of extracting model parameters:
1- Direct PEX methods
2- Iterative PEX methods
The direct extraction methods are based on the approximation of model
equations by linear functions and determine the values of parameters
graphically or by solving the linearized equations by the least-square method
(LSM).
The iterative extraction methods fit the model responses to a set of measured
characteristics by minimizing an objective function that characterizes the fit.
Sometimes a mixed approach is used in which some parameters are extracted
using the direct methods and the remaining ones by an iterative procedure, or
the direct solution is used as the starting point to an iterative refinement
As devices are scaled down, the linear regions on the device characteristics
become difficult to observe and special efforts are required to isolate groups of
parameters describing the model under different operating conditions. The
problem is overcome by fitting the model equations to a set of measured device
characteristics iteratively in the full range of operating conditions. Therefore,
the linear or nonlinear LSM can be used. LSM approach has been extensively
developed over the years, and numerous optimization programs (like IC-CAP)
are available today. These programs utilize different optimization methods.
Usually the gradient methods are used, although in some programs direct
search optimization are available. A serious drawback of the LSM optimization
method is its sensitivity to poor initial values. The Levenberg-Marquardt
(LM) algorithm is used for optimization of nanodevices. LM is a
combination of gradient decent and Gauss Newton method which
requires good initial guess. .
In order to perform the parameter extraction job, one can use standard
parameter extraction tools like IC-CAP,(from Agilent) UTMOST (from
Silvaco) or AURORA (from TMA). Therefore, we treat the results of device
simulation as a substitute for a real experiment. The figure 7-2 shows one of

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the most famous modeling packages, namely IC-CAP, which offers a complete
DC-to-RF modeling of device parameters.

NOTE 7-1. What’s IC-CAP ?

The Integrated Circuit Characterization & Analysis Program (IC-CAP), which
is available from Agilent, is the industry standard for DC-to-RF semiconductor
device modeling. IC-CAP extracts compact models used in high speed/digital,
analog and power RF applications. Most semiconductor foundries rely on IC-
CAP for modeling CMOS, Bipolar, and other device technologies. It can
extract parameters of several device models, such as Gummel-Poon (G-P) and
VBIC for bipolar transistors and BSIM for CMOS devices. IC-CAP is
customizable modeling software and includes measurement, simulation,
optimization and statistical analysis tools.

Fig. 7-2. Photograph of one of the parameter extraction tool kits (IC-CAP), from Agilent

7-2. Circuit Models

For circuit design purposes, an equivalent circuit model of the device is
necessary. A small-signal model is a linear model, in which each component

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value is obtained under a certain bias (operating point). On the other hand, the
large-signal model is a non-linear model, which describes the transistor
characteristics in a wide range of bias values. The small-signal model
parameters can be obtained by linearizing (differentiating) the large-signal
model around a certain operating point. In this section, show how to extract the
large-signal model parameters of different devices, on the basis of DC and AC
measurements.

7-2.1. Large-Signal and Small-Signal Models

Passive components are usually linear, but active (semiconductor) devices are
typically nonlinear and need to be described by nonlinear equations. The I-V
or C-V characteristics of a device describe its linear or nonlinear behavior. The
small signal AC analysis makes use of linear or linearized characteristics,
which is performed by taking the first partial derivative with respect to
different terminal voltages. Circuit functions that are used in parameter
extraction are driving-point immittances and various matrices (Y, Z, A, S, etc.)
for a two-port circuit representation. The linearized C-V characteristics can be
also replaced with s-parameters, for high frequency devices. Figure 7-3(a) and
7-3(b) show the small-signal and large-signal models of a MOSFET. Note that
the capacitances are neglected in figure 7-3(b) for simplicity.

Fig. 7-3. Small signal and large -signal MOSFET models.

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7-2.2. Y-Parameters of a Device Model

The small-signal model of a transistor can be put in the form of a linear 2-port
network and represented in a matrix form as shown in figures 7-4 and 7-5. For
instance, the y-matrix of a MOSFET small-signal model can be approximated
and put in the following form for sinusoidal input waveforms:

(7-1)

MOSFET model BJT Model

Fig. 7-4. Simplified model and y-parameters of MOSFET and BJT

Fig. 7-5. Simplified model and y-parameters of a general 2-port network

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7-2.3. S-Parameters of a Transistor Model

The s-matrix is another important 2-port network representation method for
linear models. It is particularly important for recent RF CMOS devices, which
are working from DC to microwave region. The figure 7-6 depicts the s-matrix
and s-parameters and their relation to the transfer T-matrix. Note each S matrix
element is in general complex. Note that S11, S22 are reflection coefficients
and one can plot these on a Smith Chart. Also, S12, S21 are not reflection
coefficients and are usually plotted on a Polar diagram. The reflected and
incident waves are related to terminal currents and voltages using the following
equations (for port 1):

(7-1)

From this, the terminal currents can be presented with a and b, as follows:

(7-2)

From this, one can solve the conversion from s-parameters to y-parameters, as

(7-3)

(7-4)

where

(7-5)

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Fig. 7-6. S-parameters of a 2-port network

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Table 7-1. Conversion between different forms of two-port linear models.

7-2.4. Minimum Conductance of a Device Model (Gmin)

There exists an important parameter in almost all circuit simulators, called the
minimum conductance (usually termed as GMIN). In fact, the iteration of DC
operating point of a semiconductor device relies on the utilization of nonzero
small-signal conductance. In the off-state of most semiconductor devices the
current (i) and conductance (di/dv) both go to zero, leading the Jacobean
matrix elements to diverge. In order to avoid divergence, all semiconductor
models include additional leakage conductance GMIN (typically 10 -12 S) that
maintains a non-zero di/dv in any operating mode. However, this causes
additional and non-physical leakage currents in the range of pA‘s, and there
often is need reduce GMIN in low-current or voltage sampling applications.
Many convergence aids increase GMIN temporarily during iteration to speed up
convergence. One of the most important goals of compact models is to predict
statistical variation of circuit performances without statistical investigations.

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Fig. 7-7. Role of.GMIN in a device model

7-3. Measurement of Device Model Parameters

Any set of N-port I-V parameters can be solved by obtaining N2 independent
measurements. Most precisely these are measured by forcing all but one input
to zero and measuring all the N outputs. By repeating this for all N-inputs, all
N2 parameters can be measured. The setup of a MOS-parameter measurement,
is shown in figure 7-8. First, i1 is forced to zero by opening port 1, and v1 and
v2 are measured as a function of test current in port 2. Then, the roles of the
ports are interchanged.

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Fig. 7-8. Schematic of a measurement setup of a MOS transistor.

7-3.1. Measurements of C-V Characteristics

Capacitance-voltage (C-V) testing is widely used to determine semiconductor
parameters, particularly in MOSCAP and MOSFET structures. However, other
types of semiconductor devices and technologies can also be characterized
with C-V measurements. The procedure for taking C-V measurements involves
the application of DC bias voltages across the capacitor while making the
measurements with an AC signal. Commonly, AC frequencies from about 10
kHz to 10MHz are used for these measurements. The bias is applied as a DC
voltage sweep that drives the MOSCAP structure from its accumulation region
into the depletion region, and then into inversion

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Fig. 7-9. Schematic of the C-V measurement setup of a MOS structure.

7-3.2. Measurements of S-Parameter

For RF devices, it is more convenient to replace the C-V measurements with S-
parameter measurements, to make junction capacitance extraction easier and
accurate. However, the S-parameter measurements require some experience.
With the aid of modeling toolkit, you can perform this process successfully.
The basic steps to get accurate s-parameter measurement include:

1. Calibrate the system very well to remove all DC and RF losses up to the tip
of the probes
2. De-embed the parasitic due to pads and interconnects that surround the
device to get the true measurement of the device-under test such as MOSFET.
(1) Measurement of S11 & S12
Apply input to Port1, terminate at Port2 with a Matched Load ∴a2 = 0.
S11 =(b1/a1)a2=0 = Reflection coefficient at Port 1 (matched load at Port 2).
S21 =(b2/a1)a2=0 = Voltage transfer ratio Port1 to Port2 (matched load at Port2)
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(2) Measurement of S22 & S21

Apply input to Port2, terminate at Port1 with a matched load ∴a1 = 0.
S22 = (b2/a2)a1=0 = Reflection coefficient at Port 2 (matched load at Port1).
S12 = (b1/a2)a1=0 = Voltage transfer ratio Port 2 to Port 1 (matched load at Port
1). The figure 7-10 depicts the measurement setup of the pulsed I-V
characteristics and the s-parameters, of a 2-port network.

Fig. 7-10. Measurement of s-parameters by vector network analyzer (VNA).

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7-4. Parameter Extraction & Optimization

Parameter extraction (PEX) is an important part of model development. PEX
may be equation-based or simulation-based. In the simulation-based approach,
a circuit simulator (or its part that evaluates devices and their models) is used
to provide circuit responses. The simulation-based approach eliminates
potential inconsistencies between model equations used by the extractor and
the equations implemented in simulation tools.
After the development of a model and the detailed experimental data is
measured, the parameter extraction is carried out to find the appropriate values
of the model parameters. The model parameters should be optimized to fit the
measured data as closely as possible to the simulated data. This is usually done
by the aid of the nonlinear least-squares method. This method aims at finding
the values of parameters which minimize an objective function. For such
parameter values the best fit of the model to the measured data is obtained. A
simplified flow chart of the optimization method is shown in figure 7-11.

Fig. 7-11. Flowchart of parameter extraction and optimization. Illustration for a single
parameter (p) extraction and optimization process.

As shown in figure 7-11, parameter extraction can be formulated as an

optimization problem in which a nonlinear objective function f is minimized
with respect to a set of model parameters p, subject to a set of constraints. The
objective function f(p) describes the (total) differences between the measured
data and the results of model evaluation. The quantity to be minimized is the
norm of the error vector, which is given by:

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(7-6)

Here p is the vector of parameters to be optimized; the vector f(p) consists of

the error evaluated at each data point. For instance, in a MOSFET model, Ik
may be the calculated drain current and Ik*: is the measured value at the kth
data point. Imin is a quantity provided by the user. At currents above Imin the
relative error is used, while for Ik* < Imin the absolute error (scaled by Imin) is
used. Any measure of the error may be used. This definition minimizes the
RMS error in the fit of the model to the data. Other definitions might be used
to minimize the maximum error.

Note 7-2. Curve Fitting (Regression) & Optimization

When we have a set of measurements of a phenomenon and try to find an
analytic function, which models such phenomenon, we solve a problem about
finding some parameters that minimizes a computable error function. In this
way, parameter estimation may be studied as an optimization problem, in
which the fitting function we are trying to minimize is the error one. This can
be done using many dterminstic and stochastic methods.
Let's assume we made 'N' measurements yi at the stimulating points xi. I.e. we
obtained the array {xi , yi}. Subsequently, these measured values were plotted.
A curve Y(x) shall be fitted to this array of measured data points using least
square curve-fitting technique. Referring to an individual measurement point,
the fitting error is:
(7-7a)
and for all data points:

(7-7b)
This error shall be minimized. The fitting is done by varying the coefficients of
the fitting curve of equation. The minimum of the total error E depends on the
values of these coefficients. This means, we have to differentiate E partially
versus the curve coefficients and to set the results to zero. We obtain a system
of equations, solve it, and get the values of the coefficients for a best curve fit.
This is known as regression analysis. The regression analysis is simple for a
straight line fit. But in general, measured data is non-linear. Unfortunately, a
non-linear regression analysis can be quite complicated. This problem can be

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solved if we use a suitable transformation on the measured data. This means

that the measured data is transformed to a linear context between the yi- and
the xi-values. This is a pretty smart way to get the curve fitting parameters
easily without so many calculations.

7-5. Number of Model Parameters

In device model development, the number of parameters sets up the degree of
freedom in fitting the model. All relevant physical phenomena should be
possible to the device model. However, the larger the number of parameters,
the more complicated is the fitting process. The plot left shows how the
number of parameters used in the DC I-V function of a MOSFET has increased
during the years - current BSIM models may have 300-400 parameters, when
all the dimensional scaling parameters are included.

Fig. 7-12. Evolution of MOSFET models and their number of parameters.

7-6. Non-quasi-static (NQS) Modeling

Most device equations are calculated by assuming a quasi-static situation, i.e.
given set of terminal voltages immediately results in a corresponding current or
charge. To obtain parameters of large-signal models, both static and dynamic
characterization must be performed. In fact, all physical devices have some
transport delays, and if the signal is fast compared to these delays, we need

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non-quasi static (NQS) modeling. In AC analysis the delay τ in the trans-

conductance is easily modeled by substituting

gm → gm.exp(–jωτ) (7-8)

For time-domain analysis, it is usually implemented by building a passive

delay Bessel filter inside the model.

Fig. 7-13. Illustration of quasistatic and non-quasistatic models

The structure of the LDMOS model (by Motorola Corp.) is shown below in
figure 7-14. Here, the delay in capacitors is modeled simply by series resistors,
while the vgs driving the transconductor is delayed by a (buffered) 3 rd order
Bessel filter. It should be noted that BJT models have had an excess delay
parameter TT already some tens of years.

Fig. 7-14. Example of a non-quasistatic model of a MOSFET device (by Motorola Corp.).

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7-7. Noise Models

Noise is any electrical signal present in a system other than the desired signal.
The significance of the noise analysis of a circuit is the limitation it places on
the smallest input signal that can be distinguished and treated. This doesn‘t
apply to internal distortion, which is a by-product due to nonlinearities of
electronic devices. There exist so many noise sources, among which one can
cite: Thermal noise, Shot noise and Flicker noise.

Thermal noise (Johnson noise or Nyquist noise) is the electronic noise

generated by the thermal agitation of the charge carriers (electrons) inside an
electrical conductor at equilibrium, which happens regardless of any applied
voltage. Thermal noise is approximately white, meaning that the power
spectral density is equal throughout the frequency spectrum. Additionally, the
amplitude of the signal has very nearly a Gaussian probability density
function

Shot noise, arising from the discreteness of charge quanta, is also a sort of
white noise.

Flicker noise is a type of electronic noise with a 1/f dependence. It is therefore

often referred to as 1/f noise. It occurs in almost all electronic devices, and
results from a variety of effects, such as impurities in a conductive channel,
generation and recombination noise in semiconductor devices. It is always
related to a direct current. In electronic devices, it is a low-frequency
phenomenon, as the higher frequencies are overshadowed by white noise from
other sources.

7-7.1. Noise Models

In electronic circuits, the white thermal noise source may be represented, using
an equivalent input noise voltage vn and source resistance R, as shown in figure
7-15. As shown in figure, the mean square voltage of the Johnson noise,
produced by a resistor R, is given by:

vn2  4 k T .R.B (7-9a)

where k is Boltzmann's constant (1.38 × 10-23 J/K), T is the resistor temperature

in Kelvin, R is its resistance in Ohms and B is the bandwidth (in Hz) over
which the noise voltage is observed. Note that the mean square noise voltage is
sometimes referred to as the noise power PN. For a given resistor, R, we can

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maximize this by matching (equalizing) the noise source resistance and the
subsequent system input resistance to get the maximum available noise power,

vn2
PN   4 k T .B (7-9b)
4R
The Noise Power Spectral Density (NPSD) at any frequency is defined as the
noise power in a 1 Hz bandwidth at that frequency. Putting B =1 into the above
equation, we can see that Johnson (thermal) noise has a maximum available
NPSD of just kBT.

Sv (Thermal Noise) = PN/ B = k T [V2/Hz] (7-9c)

This means that Johnson noise has an NPSD which is white and doesn't depend
upon the fluctuation frequency. However the NPSD does fall at extremely high
frequencies because the total noise power is always finite.

Fig. 7-15. Noise source model

Shot noise is due to discreteness of the electronic charge arriving at any anode
giving rise to impulses of current. The current noise power spectrum density is
given by:
SI (Shot Noise) = 2 e I [A2/Hz] (7-9d)

where I is the average flowing current and e is the electronic charge. This
means the shot noise is white, with constant spectral density, over the whole
bandwidth of the system. It worth noting that electronic noise levels are often
quoted in units of Volts per root Hertz [V/√Hz] or Amps per root Hertz.
[A/√Hz]. In practice, because noise levels are low, the actual units may be
considered as [nV/√Hz].

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Unlike Johnson or shot noise, which depend upon simple physical parameters
(the temperature and current level respectively), the flicker noise (or 1/f noise)
is strongly dependent upon the details of the particular system. In fact the term
‗1/f noise‘ covers a number of noise generating processes, some of which are
poorly understood. For this form of noise the NPSD, Sn, decreases with
frequency approximately as follows:
Sn = 1/ f n (7-10a)

where the value of the index, n, is typically around 1 but varies from case to
case over the range, ½<n<2. The mean squared current fluctuation, due to
flicker noise in a device over a frequency range B, is modeled as follows:

 I DC
a

i  k I  b .B
2
n
(7-10b)
 f 
where K1 , a and b are constants and IDC is the DC current flowing across the
device Flicker noise is often characterized by the corner frequency fc between
the regions dominated by each type. MOSFETs have a higher fc than JFETs or
bipolar transistors which is usually below 2kHz for the latter. Flicker noise is
found in carbon resistors, where it is referred to as excess noise, since it
increases the overall noise level above the thermal noise level, which is present
in all resistors. In contrast, wire-wound resistors have the least amount of
flicker noise. Since flicker noise is related to the level of DC, if the current is
kept low, thermal noise will be the predominant effect in the resistor.The
figure 7-16 depicts the power spectral density of the thermal (Johnson) noise,
the shot noise and the flicker noise. Note that the first two types are white, and
have a constant spectral density over the whole bandwidth of any system.

Fig. 7-16. Spectral density of thermal, shot (white) and flicker noise.

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7-7.2. Equivalent Input Noise of a Device or a Circuit

The noise performance of a device or circuit is usually expressed in terms of an
equivalent input noise signal, which gives the same output noise as the circuit
under consideration. Such representation allows us to calculate the noise figure
of a system and hence the minimum incoming signals, that can be detected by
this system. The figure 7-17 illustrates the input and output equivalent noise of
a system. The system is assumed to have two internal noise sources at its input
(vn and in).

Fig. 7-17. Input and output equivalent noise of a system.

7-7-3. Noise Figure and Noise Temperature

In communication systems, the noisiness of a signal is specified by the signal-
to-noise ratio (S/N). The noise factor (F) of a given system (device or circuit)
is defined as the numerical ratio of signal-to-noise ratios (S/N) in output and
input of this system:
F = (S/N)in / (S/N)out (7-11a)

The noise figure (NF) of a system is defined as follows:

NF = 10 log F = (S/N)in − (S/N)out (7-11b)

where (S/N) ratios are in dB here. The noise factor of a system is related to its
noise temperature (Tn) via the following relation:
F = 1 + Tn/To (7-11c)

where To is the physical temperature of the system. Systems without gain (e.g.,
attenuators) have a noise figure equal to their attenuation L (in dB) when their
physical temperature is equal to T0. When we know the internal structure of a

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sub-system (like a transistor or an amplifier), and its internal noise sources, we

can calculate its noise figure from the input equivalent noise.

veq2 veq2
F 2  (7-12a)
vs 4k.T .Rs
For instance, the system shown in figure 7-18, will have a noise figure, which
is given by:

vn2  Rs2 .in2

F 1 (7-12b)
4k.T .Rs
where vn and in are the internal noise sources of the system

Fig. 7-18. Noise factor of devices

7-7.4. BJT Noise
Consider the noise performance of the simple bipolar transistor stage as shown
in the figure 7-19 below. The total output noise can be calculated by
considering each noise source in turn and performing the calculation as if each
noise source were a sinusoid with RMS value equal to that of the noise source

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being considered. Consider the noise generator vs due to Rs. A part of this
source will be fed to the base and amplified:

Z
vl  vs . (7-13a)
Z  rbb '  Rs
where Z is the parallel combination of rbé and Cbé. The output noise voltage due
to vs is then given by:

Z
vo1   gm .RL .vl  gm .RL .vs .
Z  rbb '  Rs (7-13b)
| Z |2
v  g .R .v .
2 2 2 2

| Z  rbb '  Rs |2
o1 m L s
(7-13c)

Similarly it can shown that the output noise voltages by vb and ib are

| Z |2
vo22  gm2 .RL2 .vb2 .
| Z  rbb '  Rs |2 (7-14a)

| Z |2 .( Rs  rbb ')2
vo23  gm2 .RL2 .vb2 . (7-14b)
| Z  rbb '  Rs |2

Also, the noise at the output due to il2 and ic2 is given by:

vo24  RL2 .il2 , vo25  RL2 .ic2 (7-15a)

The total output noise is then:

5
v   voj2
2
no (7-15b)
j 1

Such that the output noise power spectral density becomes:

(7-16a)

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Substituting for Z we get:

 4kT  1
+ RL2   2e I c  where f1 
 RL  2  rbé //( Rs  rbb ' ).Cbé
(7-16b)

The output noise power spectral density has a frequency-dependent part, which
arises because the gain stage begins to fall above frequency f1, and noise due
to vo2 , vb2 and ib2 which appears amplified in the output, also begins to fall. The
constant term is due to noise generators il2 and ic2 . Note that this noise
contribution would also be frequency dependent if the effect of Cbe had not
been neglected.

Fig. 7-19. Noise model of a BJT.

The noise performance is usually expressed in terms of an equivalent input

noise signal, which gives the same output noise as the circuit under
consideration. Such representation allows us to calculate the noise figure of the
device and hence the minimum detectable incoming signals. Therefore, the
shown equivalent circuit is recalled, where viN2 is an input noise voltage
generator that produces the same output noise as all of the original noise
generators. All other sources of noise are considered removed. Thus

vav2 1 | Z  rbb '  Rs |2  4kT 

 2. .  2eIc   4kT ( Rs  rbb ' )  2eI B .( Rs  rbb ' )2
f gm |Z| 2
 RL  (7-17)

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The above equation rises at high frequencies due to variation of |Z| with
frequencies. This is due to the fact that as the gain of the device falls with
frequency, output noise generators il2 and ic2 have larger effects when referred
back to the input. From the input equivalent noise, one can calculate the noise
figure of the BJT. The minimum noise figure of a BJT is hence given by:

Fmin ≈ 1 + 2 gm rb (f / fT)2 (7-18)

where rb is the base resistance and gm is the transistor transconductance.

7-7.5. MOSFET Noise

In MOSFETs (and JFET‘s), there are two intrinsic sources of noise: 1/f noise
and thermal noise in the channel region. MOSFET‘s show also full shot noise
for the leakage current at the gate.

Since the MOSFET channel material is resistive, it exhibits thermal noise. The
thermal noise spectral density of a MOSFET device in any region of operation
is given by the following formula (due to Klassen and Prins):

SId(f) =( 4 k T./L2Id) ∫ g2(V)dV (7-19a)

where g(V) is the local channel conductance at a given point along the channel
and V is the corresponding voltage. The most basic equation from which g(V)
can be derived is

Id = g(V).dV/dy (7-19b)

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Fig. 7-20. MOSFET noise sources, from drain and gate sides.

In analog circuits, most devices are operating in the saturation region, and
according to long-channel theory, the drain current noise spectral density in
saturation is classically expressed by the following formula (due to Jordan):

SId(f) = 4 k T.(2/3).gdo (7-20

where gdo ≈ gm + gmb is the drain conductance, gm is the MOSFET trans-

conductance and gmb is the substrate transconductance. This classic model
underestimates the actual noise present in short-channel devices by a factor
ranging from three to ten times, as shown in figure 7-20. A more accurate
noise model must account for high-field effects. Therefore, the above model is
sometimes written as follows:

SId(f) = 4k T gm (7-21)

where  is a correction factor, depending on the MOS technology. The above

model assumes that the device is operating at frequencies well above the
flicker noise corner frequency so that flicker noise may be neglected. However,
very often in JFETs the dominant type of noise is shot noise instead and in

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MOSFETs the dominant type of noise is flicker noise, due to carrier velocity
dispersion. Therefore, the total drain current noise power is given by:

I Dsat
i  4 kT .gm .f  K
2
d f (7-22a)
f

After calculating the input equivalent noise of a MOSFET, from its internal
noise sources an intrinsic gain, one can calculate its noise figure. The
minimum noise figure of a MOSFET is approximately given by:

(7-23)

The parameter F3 is equal to one if induced gate noise is included and zero if it
is ignored (i.e., ig =0).

7-7.6. CMOS (Excess) Thermal Noise

By the aggressive scaling of CMOS technology, there was always the concern
that the high field transport in the channel could produce large carrier velocity
dispersion, and therefore more noise, significantly above thermal noise.
Therefore, recent short devices were expected to produce higher noise figure,
at certain points. Fortunately, the opposite has happened so far. Even though
the product gm.rds decreases with nanometer scaling, the device trans-
conductance gm,, still provides higher gain with CMOS scaling to compensate
for the additional noise in the channel at high field. Moreover, carrier transport
in the channel of very short CMOS may experience a change in properties that
leads to less carrier velocity dispersion due to the lower probability of carrier
scattering events (semi-ballistic transport). If this becomes a new trend it will
progressively benefit CMOS technology and will offer unprecedented lower
noise figures with scaling at frequencies above 10 GHz. Currently, minimum
noise figure (NFmin) for CMOS transistors in 90 nm is 0.5dB at 5.5 GHz.
Figure 7-21(a) shows the noise measurement system. As shown in figure, the
standard noise measurement set-up included an E5263A 2-channel high speed
source monitor unit, an SR570 low-noise amplifier (LNA) and a 3570A signal
analyzer. The output of the amplifier is fed to 35670A dynamic signal analyzer
that performs the fast Fourier transform on the time domain signal to yield the
voltage noise power spectral density. Figure 7-21(b) shows the noise gamma
factor according to several authors.
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Fig. 7-21(a). MOSFET drain noise versus drain bias

Fig. 7-21(b). MOSFET noise corfficient

7-8. Model Characterization

The model characterization consists of several stages, among which:
 De-embedding the device parameters, from other parasitic parameters,
 Solving circuit parameters from measurements
 Verification of the reliability of fitted results.

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7-8.1. Typical Fitting Procedures

A good DC fit is a necessary prerequisite for AC modeling – if the simulation
suggests an erroneous DC bias to the device, also the AC parameters will be
calculated in a wrong operating point, and their value will be wrong. Hence, a
good DC fit is necessary for good AC performance.

7-8.2. Typical DC Procedure

The first main problem in DC measurements is to get an estimate for the series
resistances so that their effects can be removed and not absorbed into the I-V
function. Here, AC measurements may help. If the device has a self-heating
model, you need to estimate the thermal resistance - if not, the self-heating
effects will be absorbed into the I-V function. Then, measurements at different
temperatures are used to fit the temperature dependence. If you need the model
at elevated or cryogenic temperatures, fit the model there.

Fig. 7-22(a). Flowchart of the DC procedures.

7-8.3. Typical AC Procedure

Measuring AC parameters is more complicated, as very careful calibration and
de-embedding of the jig parasitics is needed to obtain accurate and frequency
independent values of the capacitors, for example. After the voltage
dependency at TNOM is obtained, measurements at other temperatures are
used to fit the thermal dependence.

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Fig. 7-22(b). Flowchart of the AC measurement procedures

Fig. 7-23. AC measurements

7-8.4. Probing on IC
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When measuring devices directly on IC, co-planar probes are commonly used,
as they provide good 50 ohm up to tens of GHz. To correct the measurements,
the following calibration/de-embedding procedures are usually performed:
• Calibration to the probe tips using on-substrate known and precise impedance
standards
• Measuring the effects of bonding pads and wiring outside the actual DUT
• Measuring the device characteristics
• De-embedding the effects of the pads and wiring

7-8.5. IC Jig De-embedding

The device and test jig always include some series and parallel parasitics that
need to be de-embedded from the measurements. A very typical de-embedding
procedure is to measure an open and short layout and using these, remove the
parallel pi-network P, and then the series parasitics in network.

Fig. 7-24. Structure of the IC de-embedding jig

7-8.6. Parameter Extraction versus Optimization

As we mentioned in the previous sections, measurements are used to fit a given
set of parameters that are recognized from some corner points or values of
DC/AC parameters. This method is applicable for relatively simple models,
only. For more complex models like BSIM3 and so on, one has to use
numerical optimization methods. In this case, the procedure is as follows:
• optimize DC parameters to match the measured I-V curves. Here the
optimization goal needs to include both I-V curves and dI/dV values
• optimize AC parameters to match the measured s-Parameters

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7-8.7. Accuracy and Benchmark Criteria

As we said before, a network analyzer is most prone to measurement errors
when the reflection coefficient is either very small or close to one. However,
the manufacturers guarantee just certain phase and magnitude accuracy. In
order to benchmark the accuracy of compact device models for digital
applications it is sufficient to compare the simulated and measured data for the
linear current (Vgs = Vsupply; Vds = 0:1V) and the saturation current (Vgs = Vds =
Vsupply). In 1993 Tsividis and Suyama published a number of qualitative
benchmark tests for analog compact models, while in the same year a new
method for the evaluation of the accuracy of such compact models was
introduced. In the last years, within the IC industry the need for standardization
of compact models, being the interface between the design community and the
IC foundries, has been recognized. This has resulted in a series of workshops
on compact modeling, which was started by SEMATECH in 1995. From
discussions during workshops, a list of qualitative and quantitative benchmark
tests for DC and AC behavior was compiled. The results are summarized in
Tables below, where the original data are reproduced together with data for
BSIM3 on the same process. Results for BSIM4 are expected to be better.
From the first comparisons of high-frequency measurements and compact
model calculations (using MOS model 9) it turns out that it is crucial to include
a number of parasitics in the model calculations. Not only junction and overlap
capacitances should be taken into account, but also the bulk resistance and
especially the gate resistance. Taking these parasitics into account, both the
bias and frequency dependence of a number of important quantities, such as
impedance, transconductance, current and voltage gain, can be modeled with
good accuracy.
Table 7-2. Deviation between measured and simulated MOS characteristics (by BSIM3v3
and MOS model 9) for different temperatures and 3 operating regions: linear region (Id-Vgs),
saturation region (Id-Vds) and output conductance (gds-Vds).

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7-9. Macromodels
Macro modeling is the abstraction of information from a detailed-description at
a low level to a less-detailed description at a higher level. Macromodels are
particularly suitable for a multitude of components which don‘t have proper
simulation models. In addition, several devices (such as thyristors) have no
internal accessible points for the measurement of their internal parameters. In
all these cases, the macromodels must be built using other known components
of lower complexity. Typical examples include:

• Lateral PNP with unintentional collector to substrate.

• Parallel PNP in a vertical NPN that conducts while the PNP is in saturation
• Dual-gate and tri-gate FET

Few simulators, like SABER from Synopsys, have models for the following
components:

• PIN-diode and other microwave and power devices

• Optoelectronic components
• Snap-back protection devices

For instance, the intrinsic SPICE diode model uses the integral charge-control
approach that is not effective in modeling power PIN diodes, as it do not
consider the forward and reverse recoveries and neglects the conductivity
modulation of the base region resistance and the emitter recombination.
Similarly, the other power devices, such as SCR, GTO, IGBT, and MCT have
no intrinsic SPICE models.

Actually there exist four methods to build new models for such devices:

 Structural macromodeling (using lower complexity components),

 C-code (or SystemC) modeling,
 Analog hardware-description languages, such as VHDL-AMS, Verilog-A
and MAST (SABER), and
 The analog behavioral macromodels (ABM), which can be edited in SPICE
programs.

The structural macromodeling consists in producing an electrical equivalent

circuit, built with standard SPICE devices, that describe the device internal
structure. The behavioral approaches utilize the black-box approach, where the
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dependencies between the terminal voltages and currents are considered.

These models use linear or piece-wise-linear elements give low analysis time,
but with poor simulation accuracy, as the model neglects many static and
dynamic nonlinear effects. A higher accuracy can be brought by considering
the physical internal equations. Actually, the analog hardware description
languages (such as VHDL-AMS) can use a more physical approach, when the
internal differential equations are extracted from the device physics.

Fig. 7-25 Schematic of thyristor, GTO and Triac macromodels.

* SCR Model (Example for 600 Volt 16 Amp SCR)

* TERMINALS: A G K
. SUBCKT BTW38 1 2 3
Qp 6 4 1 POUT OFF
Qn 4 6 3 NOUT OFF
R3 6 4 400K
R2 1 4 266K
R1 6 3 24
RGS 2 6 .2
DF 6 4 ZF
DR 1 4 ZR
DG 6 3 ZG
.MODEL ZF D (IS=6.4F IBV=300U BV=600 RS=60K)
.MODEL ZR D (IS=6.4F IBV=300U BV=800)
.MODEL ZG D (IS=6.4F IBV=300U BV=5)
.MODEL POUT PNP (IS=6.4P BF=1 CJE=19.4N TF=228N TR=59.5U)
.MODEL NOUT NPN (IS=6.4P BF=100 RE=10M RC=10M
+ CJE=19.4N CJC=3.89N TF=228N TR=59.5U)

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.ENDS
Fig. 7-26 Netlist of thyristor macromodel.

Fig. 7-27. Macromodel of a diode, with VHDL-AMS.

7-10. Compact Modeling

Recently, the idea of compact models has gained a great momentum in the
electronic industry such that they are employed in almost all known circuit
simulators. In computer-aided design of ICs, the compact model describes the
device behavior, analytically (by mathematical equations), as a function of bias
conditions and device geometry. The compact models have no fitting
parameter and reflect the dependence of device physical parameter. Compact
modeling based on surface-potential description provides accurate and fast
statistical simulation. Compact models are asymptotically correct. In fact, the
compact models are actually a critical link in the translation of CMOS process
properties into IC performance.

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For instance, the DC diode current (Id) is given by the following functions of
diode voltage (Vd) and other diode parameters:
Id = Is·[exp (Vd/(n·Vt) –1] + Vd·GMIN, for (-5n·Vt ≤Vd) ≥
Id = -Is + Vd·GMIN, for (-BV = Vd) and (Vd < -5n·Vt ≤ Vd)
Id = -IBV, for (Vd = -BV )
Id = -Is·[exp (-(BV + Vd)/Vt) -1+ BV/Vt] for (Vd ≤ -BV ). (7-24)
where n is the ideality factor (n=1 by default), Vt=kT/q is the thermal voltage,
Is is the reverse saturation current, BV is the diode breakdown voltage, IBV is
the breakdown current and GMIN is the simulator minimum conductance, This
equation reflects the experimental diode characteristics of commercial diodes.
One of the most famous compact models of MOSFET devices is called
HiSIM. This compact model is based on the surface-potential description and
provides accurate and fast simulation. Actually, the surface potential of a
MOSFET is an internal device parameter that cannot be directly measured like
terminal voltages. However, fast iteration formulas were derived from the
semiconductor equations to calculate this parameter, by Sah et al. A formula
was obtained for each of the three surface potentials (in depletion, inversion
and accumulation modes). They were soon extended and later reported in
nonequilibrium These formulas can provide the rigorous derivations of the
approximate models (threshold voltage model and inversion charge model)
because the first term of these formulas gives the linear relationship which
relate the gate voltage to the surface potential. Thus, the nonlinear terms of
these formulas lead to the corrections for more accuracy to the threshold
voltage and the inversion charge models. The Compact Model Council (CMC)
is a working group in the Electronic Design Automation (EDA), which is
formed to choose, maintain and promote the use of standard models.
Commercial and industrial analog simulators (such as SPICE and SABER)
need to add device models as technology advances. New models are usually
submitted to the CMS, where their technical merits are discussed, and then
potentially voted on. Some of the models supported by the CMC include:
 BSIM3, BSIM4, BSIM5 and BSIM6 for MOSFETs from UC Berkeley
 PSP (Penn State-Philips), which is another MOSFET model.
 BSIMSOI, a model for silicon on insulator MOSFETs.
 HICUM, which is a HIgh CUrrent Model for BJTs,

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Fig. 7-28. Compact modeling lifecycle

The so-called process aware compact models (PCMs) are analogous to

compact models for semiconductor devices and circuits. PCM may be used to
capture the nonlinear behavior and multi-parameter interactions of
manufacturing processes. SPICE process compact models (SPCMs) can be
considered as an extension of PCMs applied to SPICE parameters. By
combining calibrated TCAD simulations with global SPICE extraction
strategy, it is possible to create self consistent process-dependent compact
SPICE models, with process parameter variations as explicit variables. There
exist some modelling tools to generate and compile compact device models for
SPICE-like simulators. For instance, the Paragon tool (Chaudhary, et al, 2002)
can generate compact device models in a high-level abstract representation
(e.g., in XML, or Verilog-A or VHDL-AMS). The generated model can be
optimized and coded into C/C++ by ADMS (Lemaitre et al, 2002) or MCAS.
(Wan et al, 2003).

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Fig. 7-29. Flowchart of process compact modeling (PCM)

7-11. Examples of Device Models

The device models are important in circuit simulation programs, like SPICE
and its variants. SPICE includes many semiconductor device compact models.
In this section we demonstrate some models of the well-known semiconductor
devices and illustrate how their parameter can be extracted and optimized. In
particular we demonstrate the P-N junction diode models, the BJT models
(Gummel-Poon, VBIC) and the MOSFET models (BSIMx / MOSx).

7-11.1. Diode Model

Diode current is controlled by a barrier height, according to the Shockley
equation. The simple DC model used in SPICE is very similar to the Shockley
equation, with the addition of an ideality factor (emission coefficient)
parameter n, and a convergence aid of the GMIN parallel conductance. SPICE
model includes breakdown via a breakdown voltage, specified as BV, with
current at breakdown of IBV. Finally, a series resistance RS is added to the
diode model to simulate the resistances of the connecting wires and the ohmic
contact.

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(7-25)

where IS is the diode‘s reverse saturation current, Vd is the applied voltage bias,
kT/q is the thermal voltage and ID is the current through the device.

Fig. 7-30. Model and I-V characteristics of a diode.

i. Diode Capacitance
The next stage in the development of the diode model is to add the dynamic
effects to the diode model via the diode capacitance. In forward mode the
charge stays within the junction area for time TT, causing diffusion
capacitance Cdiff. In reverse mode the depletion capacitance Cd of the reverse
junction dominates the overall capacitance.

(7-26a)

(7-26b)

ii, Diode Temp Behavior

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The temperature characteristics of the diode are strongly physics based,

including the change in bandgap energy, saturation current and built-in
junction potential. The most important parameters related to this are.

(7-27a)

(7-27b)

(7-27c)

Note that the temperature drift of knee current IKF and breakdown voltage
need some (polynomial) fixes that are not included in the original SPICE
model. Typical 1st and 2nd order polynomial corrections are:

(7-28a)
(7-28b)

The SPICE model of a diode is specified by the .model statement a follows:

.model DName D(Par1=value Par2=value… Parn=value)

where Par1..Parn are the diode model parameters. As shown in the Table 7-3,
the DC characteristics of the diode are determined by the parameters IS, N, and
the ohmic resistance RS. Charge storage effects are modeled by a transit time,
TT, and a nonlinear depletion layer capacitance which is determined by the
parameters CJO, VJ, and M. The temperature dependence of the saturation
current is defined by the parameters EG, the band gap energy and XTI, the
saturation current temperature exponent. The nominal temperature at which
these parameters were measured is TNOM, which defaults to the circuit-wide
value specified on the .OPTIONS control line. Reverse breakdown is modeled
by an exponential increase in the reverse diode current and is determined by
the parameters BV and IBV (both of which are positive numbers).

Table 7-3. Diode model parameters

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Name Parameter Units Default

IS Saturation current A 1.0e-14
RS Ohmic resistanc Ohm 0
N Emission coefficient - 1
TT Transit-time sec 0
CJO Zero-bias junction capacitance F 0
VJ Junction potential V 1
M Grading coefficient - 0.5
EG Band-gap energy eV 1.11
XTI Saturation-current temp.exp - 3.0
KF Flicker noise coefficient - 0
AF Flicker noise exponent - 1
Coefficient for forward-bias
FC - 0.5
depletion capacitance formula
BV Reverse breakdown voltage V infinite
IBV Current at breakdown voltage V 1.0e-3
TNOM Temperature C 27
AREA Area multiplier - 1

7-11.2. Bipolar Transistor Models

The figure 7-31 depicts the structure of a modern BJT. This structure is called
double-poly self-aligned BJT. There exist so many circuit models of the
bipolar junction transistor (BJT), such as the Ebers-Moll and Gummel-Poon
(G-P) model. The SPICE model of a BJT is specified by the .model statement:

.model ModelNameNPN (par1=a par2=b………parn=x)

.model ModelNamePNP (par1=a par2=b………parn=x)
where par1…….parn are the parameters that allow to BJT model equations
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Fig. 7-31. Structure of self-aligned poly emitter bipolar transistors.

i. Ebers –Moll Model

The BJT current equations can be translated into the so-called Ebers-Moll
model, as shown in figure below. The indicated BJT currents are given by:

 v    v  
I E  I ES exp BE   1   R I CS exp BC   1 (7-29a)
  VT     VT  

 v    v  
I C   F I ES exp BE   1  I CS exp BC   1 (7-29b)
  VT     VT  

 F I ES   vBE    R I CS   vBC  
IB  exp  1  exp  1 (7-29c)
F   T  
V R   T  
V

where F and R are the forward and reverse C-B current gains and, F and R
are the forward and reverse C-E current gains of the BJT. Also IES and ICS are
the reverse saturation currents of the E-B and C-B junctions and FIES = RICS

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Fig. 7-32. Ebers-Moll model of a discrete BJT

ii. Gummel-Poon Model

The Gummel-Poon (G-P) model has been the industry standard model for BJT
devices for decades (Gummel & Poon, 1970). It is simple, and well-built BJT
model. The following figure shows the structure of the G-P model. In order to
support operation with collector and emitter swapped, it calculates the B-E and
B-C junctions separately and has all necessary parameters for both the forward
and reverse modes (e.g. VAF/VAR, TF/TR,.. etc).

The G-P model takes several phenomena into account, such as the gain
reduction due to high injection. This is specified by forward knee current IKF.
Also, a simple model for output impedance is given by Early voltage VAF. In
saturation regime the current in B-C junction is not negligible, and a different
equation for IC rises.

(7-30)

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Table 7-6 depicts the meaning of the different parameters in the G-P model.
The G-P is widely used in the popular circuit simulators such as SPICE and its
variants.

Fig. 7-33. Gummel-Poon (G-P) model of a discrete NPN BJT

Fig. 7-34. The G-P model of an advanced BJT, indicating the lateral PNP BJT

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Table 7-4. Parameters in the G-P model.

Parameter Meaning Default Value Units

AF flicker-noise exponent 1 -
BF ideal max forward beta 100 -
BR ideal max reverse beta 1 -
CJC B-C zero-bias depletion capacitance 0 F
CJE B-E zero-bias depletion capacitance 0 F
CJS zero-bias collector-substrate capacitance 0 F
EG energy gap for temperature effect of IS 1.1 eV
FC coefficient for forward-bias depletion capacitance 0.5 -
IS transport saturation current 1.00E-016 A
IKF corner for forward beta high current roll-off inf A
ISE B-E leakage saturation current 0 A
current where base resistance falls half-way to its
IRB inf A
minimum
IKR corner for reverse beta high current roll-off inf A
ITF high-current parameter for effect on TF 0 A
ISC B-C leakage saturation current 0 A
KF flicker-noise coefficient 0 -
MJC B-C junction exponential factor 0.33 -
MJE B-E junction exponential factor 0.33 -
MJS substrate junction exponential factor 0 -
NF forward current emission coefficient 1 -
NE B-E leakage emission coefficient 1.5 -
NR reverse current emission coefficient 1 -
NC B-C leakage emission coefficient 2 -
PTF excess phase at freq=1.0/(TF*2PI) Hz 0 deg
RB zero-bias base resistance 0 ohms
RBM minimum base resistance at high currents RB ohms
RE emitter resistance 0 ohms
RC collector resistance 0 ohms
TR ideal reverse transit time 0 s
TNOM parameter measurement temperature 27 deg.C
TF ideal forward transit time 0 s
VTF voltage describing VBC dependence of TF inf V

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Parameter Meaning Default Value Units

VAF forward Early voltage inf V
VAR reverse Early voltage inf V
VJC B-C built-in potential 0.75 V
VJS substrate junction built-in potential 0.75 V
VJE B-E built-in potential 0.75 V
XCJC fraction of B-C depletion capacitance to the base node 1 -
XTI temperature exponent for effect of IS 3 -
XTB forward and reverse beta temperature exponent 0 -
XTF coefficient for bias dependence of TF 0 -

Disadvantages of the G-P Model

The G-P model ignores several phenomena. These phenomena include:
• Modeling of the parasitic PNP transistor
• Quasi-saturation at low VCE-voltages. This is due to the collector resistance,
that is not modeled in G-P model
• Standard GP model does not have any parameter for breakdown voltage
• Input capacitance has discontinuous high order derivatives (C depl model)
• Effects appearing of heterojunction bipolar transistors (HBT‘s)
Doping concentrations in a vertical BJT usually increase towards the surface,
and this is ok for operation: strong doping in emitter gives good beta, and low
doping in collector results in high breakdown voltage. However, the base
region is difficult to design, as low base doping also means high resistivity in
the already thin base region. A typical trick to achieve both low base resistance
and high emitter efficiency is to make use of heterojunction BJTs (HBT). In
HBT‘s, the base region is fabricated of a material with smaller forbidden
energy gap.

iii. VBIC Model

The Vertical Bipolar Inter-Company (VBIC) is a public domain model
developed by the Bipolar Circuits and Technology Meeting (BCTM)
consortium. It models quasi saturation, avalanche, and substrate effects. The
latest release includes self-heating effects. Figure 7-35 shows the subcircuit of
the VBIC model. Compared to the standard G-P model, we note that QBE is
distributed on both sides of RB. This results in better RF matching of scattering
parameters. The parallel lateral PNP is included in the model and breakdown
effects are also included.

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Fig. 7-35. Structure of. the VBIC model

7-11.3. MOS Transistor Models

MOSFET operation and modeling has been a subject of extensive study for
many years. In fact, the modern MOSFET devices have many features, which
were not known when first models were constructed. For instance, the halo and
pocket areas are used to obtain lightly-doped drain/source regions, silicide is
used to lower Drain/Source resistance, hot electrons escape to substrate
causing substrate currents and modulation of threshold voltage. In addition, the
device may operate in the moderate inversion regions between weak and strong
inversion due to the low supply voltages. The cross section of a single finger
NMOS transistor is shown in figure 7-36. Also, figure 7-37 depicts the circuit
model of such a MOSFET. There are finite resistances in the drain, source, and
gate terminals as well as in the substrate. At low frequency, the substrate
coupling effects are neglected. However, as the operation frequency increases,
the impedance of the junction capacitances reduces. The signal coupling
through the substrate resistances from the drain to the source and from the
drain/source to the substrate contact has to be carefully considered. This non-
ideal coupling effect especially affects the output admittance, which is an
important variable for RF design.

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The first basic model was based on the MOSFET 1-dimensional analysis (long
channel). Another approximate model, which may be used for short-channel
MOS, is called the charge-sheet model (CSM). The CSM assumes that the
depletion region is free of mobile charges. All electrons are considered inside
the inversion layer which is a sheet of zero thickness, just below the gate
oxide. Since the inversion layer is infinitesimal, the potential drop across it is
negligible, and we can assume that all of the surface potential is dropped
across the depletion region in the substrate.

In order to obtain accurate expressions for the MOSFET drain current and
parasitic capacitances, several authors tried to find out expressions for the
semiconductor surface potential. The first accurate and complete quantitative
MOSFET model was the Pao-Sah model. Perhaps the Pao-Sah model is the
most complete, in the sense that it accounts for a two dimensional charge
distribution, starting from the Poisson equation and other semiconductor
equations. However, this model needs to a series of approximations in order to
reach an analytical equation for surface potential and the MOSFET drain
current.
The so-called PSP (Pennsylvania State University-Phillips) model is an
advanced compact MOSFET model developed by merging the best features of
the two surface potential-based models: SP (developed at The Pennsylvania
State University) and MM11 (developed by Philips). In fact, there exist so
many compact MOSFET models, among which one can cite:
 aMOS - Texas Instruments,
 ASIM - AT&T Bell Labs, USA
 BSIM3/BSIM4/BSIMSOI/BSIMCMG - Univ. of California at Berkeley,
 CSIM - AT&T Bell Labs,
 EKV - Swiss Federal Institute of Technology (EPFL), Switzerland
 HiCUM - University of Technology Dresden, Germany
 HiSIM- Hiroshima University, Japan
 MISNAN - Carleton University, Canada
 MOS9/MOS11/MOS31/MOS40/ - NXP, The Netherlands
 PSP - The Netherlands (SP-Penn State Univ/MM11-Philips)
 SPP - University of California at Berkeley, USA
 UMOS - Intel, USA
 USIM - Agere Systems (IBM),

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The figure 7-38 depicts the development of MOSFET models from Pao-Sah
and MM models. The table 7-5 depicts how the MOSFET model statement is
called in different SPICE programs. The SPICE model of a MOSFET includes
a variety of device and process related parameters.

Fig. 7-36. MOSFET structure and parameters

Fig. 7-37. Basic MOSFET model

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Fig. 7-38. Development of MOSFET models from Pao-Sah and Phillips (PSP) models

Table 7-5. SPICE Dialects and Netlist Syntax

Spice2/3: .model mname NMOS|PMOS LEVEL=1 [par= value]*

PSpice: .model mname NMOS|PMOS LEVEL=1 [par= value]*
HSpice: .model mname NMOS|PMOS LEVEL=1 [par= value]*
Spectre: model mname mos1 type= [n|p] [par= value]*
ADS model mname MOSFET NMOS=[0|1] PMOS=[0|1] Idsmod=1
[par= value]*

i. MOS Level-1 Model

We start by introducing the most classical MOSFET models and their DC and
AC parameters. The following figure shows the MOSFET ideal characteristics
A. DC Parameters
For amplifier design, the transistor is biased in the saturation (or active) region.
In this region, the drain current of NMOS is given by the approximate relation:

(7-31)

where kn = nCox(W/L) is the transconductance parameter, Vt is the threshold

voltage (the vGS value when MOSFET starts conducting), λn is the channel-

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length modulation parameter, μn is the electron mobility, Cox is the gate

capacitance per unit area. As the gate bias voltage exceeds Vt, the channel
starts to conduct with a square law iD with the gate voltage. The parameter λ
describes the fact that the drain current increases with the drain-source voltage.
B. AC parameters
The main parameters affecting the transistor AC characteristics are the gate-
source capacitance (C gs) and gate-drain capacitance (Cgd). In addition, the
source-body (Csb) and drain-body (Cdb) depletion capacitances are due to the
parasitic PN junction. If the source and body are connected, then C sb can be
neglected. These parameters can be obtained from the following equations and
verified by measurements.

(7-32a)
,

(7-32b)

where Cox is the gate oxide capacitance per unit area , Cgso and Cgdo are the
overlap capacitances between gate-source and gate-drain, respectively. Also,
Vo is known as the junction built-in voltage, Csb0 and Cdb0 are the zero-bias
body capacitance to source and drain.

Table 7-6. MOSFET Level 1 SPICE parameters

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ii. BSIM3 Model

BSIM3 is a compact MOSFET model, which is based upon finding solutions to
Poisson's equation by Gradual Channel Approximation (GCA) and Quasi-Two
Dimensional Approximation (QTDA) approaches. BSIM3v3 has become an
industry standard for modeling deep-submicron MOS technologies. The model
is suitable for both digital and analogue applications, in part because of
improved modeling of the output conductance, when compared to previous
MOS device models. It also offers binning parameters for improving the model
for smaller devices. BSIM3v3 includes compact, analytical expressions for the
following physical phenomenon observed in present day MOS devices:
• Short and narrow channel effects on threshold voltage.
• Non-uniform doping effect (in both lateral and vertical directions).
• Mobility reduction due to vertical field.
• Carrier velocity saturation.
• Drain-induced barrier lowering (DIBL).
• Channel length modulation (CLM).
• Substrate current induced body effect (SCBE).
• Subthreshold conduction.
• Source/drain parasitic resistances.
The following figure depicts the effect of several phenomena (such as drain-
induced barrier lowering DIBL and short-channel binning effect SCBE) on the
short MOS I-V characteristics and output resistance. One must keep in mind
that a binned BSIM3v3 model is only partly physical. Its physical foundation is
compromised by the very large number of non-physical correction parameters
that are necessary for the model to work over a large range of channel
dimensions in a deep submicron process. Most of the simulation problems
encountered with BSIM3v3 are created by these correction parameters. The
parameter extraction and optimization method minimizes these problems. We
initially focus upon the basic equations used in the model, and then proceed to
the measurement and parameter extraction and optimization strategies.

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Fig. 7-39. MOSFET Effects.

A. Drain Current Model

The overall current equation for both linear and saturation current is given by:

(7-33a)

(7-33b)

(7-33c)

(7-33d)

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The device parameters Leff, Weff, Cox, Vgs, Vds, Vbs, X j, Xdep, s, vsat are channel
effective length and width; oxide capacitance, gate voltage, drain-source
voltage, substrate bias voltage, junction depth, depletion width, surface
potential, and carriers saturated velocity are given respectively. The threshold
voltage Vth is given by:
(7-34a)

(7-34b)
,

The parameter Tox is the oxide thickness and Vbi is the built-in voltage.
For large device sizes the above expression can be reduced to Vtho. The
parameter Vtho is the ideal threshold voltage of a large channel device at zero
substrate bias, and Vbeff is substrate bias with upper limit 1-3.

(7-35)

The effective mobility μeff is given by:

(7-36a)

(7-36b)

Such that
(7-36c)

Here μ0 is the parameter which represents the ideal low field mobility of a
large device. The coefficients Ua, Ub and Uc are parameters that represent the
reduction of the channel mobility by the vertical field. From this equation, it is
possible to show that for large V gs values the parameter Vgst =(Vgs- Vth) for Vgs
< Vth, Vgst will be proportional to exp(Vgs-Vth).

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The drain current equation in the sub-threshold region is given by:

(7-37a)

where
(7-37b)

(7-37c)

(7-37d)

The parameter Nch is the channel doping density, εox is the permittivity of the
oxide, and εsi is the permittivity of the silicon. The effective channel length in
BSIM3 is given by:
Leff = Ldrawn – 2dL (7-38a)

(7-38b)

The parameters LL, LLN, LW, LWL and LWN are the length parameters that
represent the short channel effect. The XL parameter represents the difference
between the drawn channel length on the layout and the printed length on the
wafer. The effective channel width model in BSIM3v3.1 is given by:
Weff = Wdrawn – 2dW (7-38c)

WL, WLN, WW, WWN, WWL, DWG and DWB are the width parameters
that represent the narrow channel effect. The parameter XW is the difference
between the drawn channel width on the layout and the printed width on the
wafer. Lint and Wint represent the reduction of the channel length and width of
the device due to source-drain diffusion. Usually it is sufficient to extract Lint
and Wint for a long channel device,
B. Junction Capacitance Model

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The source and drain capacitance is divided into two components, namely the
area junction capacitance per unit area and the perimeter junction capacitance
per unit length. The total junction capacitance CJcap is found from

CJcap = CJA . A CJP . P (7-39a)

where A is the total junction area and P is the total perimeter. The area
junction capacitance
CJA = CJ (1 MJ Vbs /Pb) if Vbs > 0 (7-39b)
The perimeter junction capacitance is
C JP = CJSW (1 MJSW Vbs / Pbsw) if Vbs > 0 (7-39c)

C. Parameter Binning
BSIM3v3 uses the following implementation for all those parameters that can
be binned. As an example the parameter 'P' is written in terms of the binning
parameters LP, WP and PP. The parameter P0 is a parameter for the large
device size, LP is a binning parameter for the length variation, WP is a binning
parameter for the width variation, and the parameter PP is a binning parameter
for the length multiplied by width variation.

D. Parameter Extraction and Optimization Strategies

Based on the properties of the BSIM3v3, a combination of a local optimization
and the group device extraction strategy can be adopted for parameter
extraction. We can use the following data measurement procedures for
parameter extraction and optimization on a large number of test transistors.
Ids versus Vgs at low Vds with varying Vbs.
Ids versus Vgs at high Vds with varying Vbs.
Ids versus Vds at low Vbs with varying Vgs.
Ids versus Vds at high Vbs with varying Vgs.
Cj versus V (junction capacitance versus voltage).

Additional measurements determine the values of the following parameters:

Tox (gate oxide thickness).
CGDO (gate-drain overlap capacitance).
CGSO (gate-source overlap capacitance).
rce (drain sheet resistance).

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Parameter extractions for each process technology start with an initial set of
parameters that come from,
a) Vendor or Silicon Foundry (Hit kit) models;
b) Previous models;
c) Extracted models from physical fundamentals.

Using these initial parameters with the above extracted 4 parameters from the
process monitor (Tox, CGDO, CGSO, Rsh), several optimization strategies can
be implemented for CMOS technologies (down to 0.18um for BSIM3v3).
These strategies are derived by modifying the standard extraction and
optimization procedures from commercial tools. The interaction between
parameters that are optimized in a given strategy is controlled by the maximum
and minimum limit for each parameter. For the matter of illustration, we
summarizer these strategies.
Strategy 1: Parameters in threshold and sub-threshold regions
This local strategy is applied for wide and long device only.
Target parameters: Vth0, μ0, Ua, Ub, Uc, K1, K2, N factor and V off.
Requires Ids versus Vgs data with low Vds and varying Vbs.
Strategy 2: Threshold shift effect parameters
This local strategy is applied for narrow and long device only.
Target parameters: Wint, K3, W0, K3b, DWG, DWB, WL, WLN, WW, WWN.
Requires Ids versus Vgs data with low Vds and varying Vbs.
Strategy 3: Threshold shift and channel resistance effects parameters
This local strategy is applied for wide and short device only.
Target parameters: Lint, Rdsw, Dvt0, Dvt1, Dvt2, Prwg, Prwb, LL, LLN, LW, LWN and
NLX. Requires Ids versus Vgs data with low Vds and varying Vbs
Strategy 4: Threshold shift, mobility and channel resistance effects binning
parameters. A good model result can be obtained for carefully chosen target
device sizes, but the simulation characteristics vary widely from the actual
device characteristics when the channel length and width are varied from large
to very small device sizes. By carefully choosing appropriate model binning
parameters, the effects of small channel width and length can be better fit to
measured data. This local optimization strategy is applied for the small device
size only (short and narrow channel).
Target binning parameters: PVth0, PRdsw, PU0, PUA, PUB, and PK2.
Requires Ids versus Vgs data with low Vds and varying Vbs.

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Strategy 5: Low bias drain saturated current parameters

This local optimization strategy uses specific geometric combinations.
Target parameters: A0, vsat, B1, Pvsat, B0, and Ags. Requires Ids versus Vds
data with low Vbs and varying Vgs. For A0 and Ags use wide and long channel
devices. For vsat use wide and short channel devices. For B0 and B1 use
narrow long channel devices. For the binning parameter P vsat use small devices.
Strategy 6: Low bias output resistance parameters
Local optimization of output resistance is more challenging. Device sizes that
are included or excluded must be chosen carefully. This strategy is usually
applied for wide and short channel devices, but you can also include short
channel devices together with the long channel. If the wide and long channel
device becomes the dominant factor in the optimization, this device can be
excluded. This strategy and strategy 5 should be executed one after another
several times to get a good result.
Target parameters: Pvag,PCLM,PDIBL1,PDIBL2,DROUT,DELTA,PSCBE1, PSCBE2,
ETA0, DSUB. Requires Ids versus Vds data with low Vbs and varying Vgs.
Strategy 7: High bias drain saturated current parameters
This local optimization strategy uses a combination of geometries.
Target parameters: KETA, WKETA, LKETA and PKETA.
Requires Ids versus Vds data with high Vbs and varying Vgs.
For KETA use wide and long channel device only.
For binning parameter WKETA use narrow and long channel devices only.
For binning Parameter LKETA use wide and short channel devices only.
For binning parameter PKETA use small devices only.
Strategy 8: High bias output resistance parameters
This local optimization strategy uses short channel devices together with long
channel devices. The parameters optimized in this strategy are those in
equations.
Target parameters: ETAB and PDIBLCB.
Requires Ids versus Vds data with high Vbs and varying Vgs.
Strategy 9: Junction capacitance parameters
This global optimization strategy uses junction capacitance C-V data to
optimize the parameters listed in equations. Junction capacitance versus
voltage measurements are taken on two junction capacitors: one with an area-
dominated structure and the other with a perimeter-dominated structure.
Target parameters: CJ, MJ Pb, Cjsw and Pbsw.

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iii. Limitations of BSIM3v3

One undesirable characteristic of using a quadratic expression in the
denominator of the effective mobility equation is that its nonlinear property
can lead to simulation instability if parameters are not carefully optimised. If a
transient simulation has an internal time step that can cause a calculated gate
voltage to become large during the convergence computation, then it is
possible for the mobility vertical field parameters to dominate. This creates
non-physical mobility and transconductance results that may lead to unstable
convergence. In order to minimize this problem, we should optimize those
parameters that represent the reduction of channel mobility by the vertical field
(Ua, Ub, and Uc). These parameters should be very small. The parameter
binning feature is useful when it is desirable to fit a wide range of length and
width devices within a technology. Without this binning it will be necessary to
have separate sets of model parameters for limited ranges of device sizes to get
the best result. However, binning parameters must be used carefully because
they can produce undesirable non-physical behavior in the model. In nano-
device technology it is possible to have the PP parameter equation become
dominant when transistor width and length are implemented at their minimum
design rule values. An example of the above problem occurs if one allows the
series resistance binning parameter PRdsw to be less than zero. The simulation
result then may give a negative resistance that is not physical for smaller
devices. The BSIM3v3.1 model does not include quantum effects, which
become significant for devices with oxide thickness below 4nm and this
omission may contribute to non-physical model parameter extraction results.
Other areas for improvement of the BSIM3 model are addressed in BSIM4.
iv. BSIM4 Model
The BSIM4 model has been an industry-standard model for MOSFET devices,
since 2000. The BSIM4 model addresses many important modeling issues for
sub-0.13um CMOS technology and RF high-speed applications. In fact,
BSIM4 has been successfully used for the 0.13um, 90nm, 65nm, 45/40nm,
23/28nm, and 22/20nm technology nodes. The major effects covered in the
BSIM4 model is the process-induced strain effect, and the shallow-trench
isolation (STI) effect, which models the device performance based on the
active area geometry. BSIM4 still considers the operating regions described in
MOS level 3 (linear for low Vds, saturated for high Vds, sub-threshold for
Vgs<Vt), but provides a perfect continuity between these regions. BSIM4
introduces a new region where the impact ionization effect is dominant. In that

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region, Vds is very high, over the nominal supply voltage V DD. One of the key
features of BSIM4 is the use of one singly equation to build the current, valid
for all operating modes. Smoothing functions ensure a nice continuity between
operating domains. The improvements over the BSIM3v3 include:
• Non-Quasi-Static (NQS) model;
• Scalable strain effect model for process induced strains;
• Unified current-saturation model that includes all mechanisms of current
saturation – velocity saturation, and velocity overshoot;
• Temperature model that allows prediction of temperature effects on
saturation velocity, mobility, and S/D resistances;
• Gate direct tunneling current model for multiple-layer gate dielectrics;
• Quantum mechanical charge layer- thickness model;
• Gate Induced Drain Leakage (GIDL) current model;
• Induced gate noise model;
• Enhanced accuracy and flexibility of holistic thermal noise model;
• Improved accuracy of forward body bias model;
• Model of the intrinsic input resistance for RF, analog and digital applications;
• Layout dependent parasitic model for multi-finger devices;
The BSIM4.4 model was specifically developed to addresses trap-assisted
tunneling (TAT) and recombination current that occurs at reverse biased P-N
junction where the doping on both sides of the junction is relatively high due to
the halo-doping technology. Also, a new parameter VFBSDOFF, is added to
improve the gate overlap tunneling current. More details about BSIM3 and
BSIM4 can be found in William Liu book: MOSFET Models for SPICE
simulation (2011).
v. BSIM5 Model
BSIM5 is a charge-based model. Compared with the previous charge-based
models with an assumption of the linearization of the bulk and inversion
charges with respect to the surface potential at a fixed gate bias, the BSIM5
model is directly derived from the solution of the Poisson equation coupled to
the current density equation. The comparisons of the inversion charge and the
channel current between the BSIM5 and the Pao-Sah model indicate that the
BSIM5 model maintains the device physics and the accuracy of the Pao-Sah
model. Various new physical effects are timely addressed in the new physical
core including accurate physics that is easily extended to non-charge-sheet,
continuous current and derivatives, and extendibility to non-traditional CMOS
based devices including SOI and double-gate MOSFETs.

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vi. BSIM6 Model

BSIM6 model is the next generation bulk RF MOSFET model which uses
charge based kernel with physical models derived from BSIM4 model.
vii, BSIMSOI Model
The figure 7-40 shows the topology of BSIMSOI model, that is generated from
documentation parameters by Paragon (Chaudhary et al, 2006). The internal
and external body nodes (B and P, respectively) are shown in the model
topology. The only node that is neglected in this model topology is the thermal
junction node, which is required for a self-heating version of the BSIMSOI
model.

Fig. 7-40. BSIMSOI v2.2 large signals model, After Chaudhary et al (2005).

viii. BSIM-MG Model

BSIM-MG is a compact multiple-gate MOSFET model. Multiple-gate
MOSFETs (e.g., FinFETs), which have superior short channel control, are
expected to replace planar CMOS in the near future. Note that the independent
gate MOSFET (shown in figure 7-34) allows the tuning of threshold voltage by
changing the back-gate voltage. BSIM-MG includes two sub- models, namely:
the independent multi-gate compact model BSIM-IMG and the common
multi-gate compact model BSIM-CMG.

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The kernel of the model has an enhanced surface potential nalytic description
of the channel charge and channel current. The model takes into account the
quantum confinement in the multi-gate structures, in a compact model
framework.

Fig. 7-41. Several shapes of multigate MOSFET. (a) Bulk FinFET with 2 independent gates;
(b) SOI FinFET with independent gates; (c) All-gate–around MOS

ix. Which MOS Model Should You Use?

Level 1: For quick estimates of long devices, with low accuracy. Very poor
for small devices. Considered obsolete nowadays.
Level 2: Suitable for convergence problems and small computer resources.
Level 3: Good for MOSFET down to about 2 microns.
BSIM – Level 4 (HSPICE Level 13): good for small geometry MOSFETS
with L down to 1 micron and tox down to 150 Angstroms. Problems near
Vsat; negative output conductance; discontinuity in current at VT. For
submicron dimensions, replaced by BSIM2 and HSPICE Level 28.
BSIM2 (HSPICE Level 39): Good for small geometry MOSFETs with L
down to 0.2 micron and tox down to 36 Angstroms.
HSPICE Level 28: BSIM with its problems solved; good choice for
HSPICE users.
BSIM3 Version 3 (HSPICE Level 49): Most accurate, but complex.
BSIM4 is the industry standard compact MOSFET model since 2000
BSIM6 was development in late 2010 to address RF MOSFET devices.
BSIM-CMG and BSIM-IMG are the surface potential based models for
multi-gate MOSFETs.

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Fig. 7-42. Evolution of the BSIM models of different MOSFET structures

7-12. Case Study: Compact Modeling of a CNTFET

The carbon nanotube field-effect transistor (CNTFET) is one of the most
intriguing applications of carbon nanotubes. Like other FETs, the drain current
increases with an increasing drain bias unless the applied gate voltage is below
the threshold voltage. For planar CNTFETs the FET with a shorter channel
length produces a higher saturation current, and the drain saturation current
becomes higher for the CNT of smaller diameter.

Fig. 7-43. Schematic of the gate-all-around GAA, CNTFET. After Lee et (2015).

The modeling of CNTFETs has been the subject of extensive research.

Recently, Lee et al (2015), developed an interesting compact model of the
CNTFET, which has been implemented in Verilog-A. This model is based on
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Numerical Simulation of Semiconductors & NanoDevices Chapter 7

the virtual source (VS) model and captures dimensional scaling effects (Lee &
Wong, 2015). The VS model is a semi-empirical model with only a few
physical parameters, originally developed for short-channel Si MOSFETs. The
model runs in SPICE environments with analytical current equations
throughout all regions of operation, with no numerical iterations. According to
this model, the drain current in the ballistic limit can be calculated by the 1D
Landauer formula, as follows:

(7-40)

The velocity in the ballistic limit (vnB) can be calculated from this ballistic
current (IdB = e n vnB). Therefore, the CNTFET drain current (Id = e n vno) can
be calculated from the virtual source velocity vno, which is given by
(Khakifirooz, Nayfeh & Antoniadis, 2009):

(7-41)

where v is the carrier mean free path, and l is proportional to Lg and may be
defined as the distance over which the electric potential drops by kBT/e from
the top of the energy barrier in the channel.

As illustrated in figure 7-44, the on-state current Ion ≡ Id(Vgs=Vds=Vdd) per CNT
and the intrinsic delay int = LgCinvVdd/Ion are plotted against CNT diameter at a
fixed off-state current Ioff ≡ Id(Vgs=0, Vds=Vdd) =1nA per CNT. As shown in
figure 7-45, a 2-nm diameter CNT can deliver 27% higher Ion and 21% lower
int than a 1-nm diameter CNT. Also, μ ~ d2 is observed in CNFETs with
relatively long channels (Lg> 4μm). By calibrating the VS-CNFET model to
experimental data and rigorous numerical simulations, it becomes possible to
make predictive estimates of device behavior as the dimension scales down.

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Numerical Simulation of Semiconductors & NanoDevices Chapter 7

Fig. 7-44. CNTFET capacitance, charge and mobility. After Lee et al (2015).

Fig. 7-45. CNTFET quantum capacitance and charge. After Lee et al (2015).

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Numerical Simulation of Semiconductors & NanoDevices Chapter 7

7-13. Summary
The parameter extraction of circuit models of semiconductor devices is an
important step in the cycle of electronic design, as shown in the following
figure. Although most device models are based on physical theory, there are
always some parameters which do not have physically-defined values, and
others for which the physical values do not give the best fit to real device
characteristics. Thus it is generally necessary to extract model parameters from
measured transistor data.

Fig. 7-46. IC design lifecycle, showing the device parameter extraction stage

A typical modeling procedure involves selecting a model based on the device

technology and its final circuit application (e.g., DC, RF, power, etc), making
the necessary measurements to characterize a device or a set of devices, and
then applying an extraction algorithm to calculate the model parameters to
minimize discrepancies between measured and simulated data. This step is
achieved by either calculating the parameters using built-in or custom model
equations from measured data, or by using tuning or optimization techniques.
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Numerical Simulation of Semiconductors & NanoDevices Chapter 7

Fig. 7-47. Optimization in parameter extraction

The optimization is very important for extracting the parameters of any

semiconductor device (e.g., BJT and MOSFETs). Advanced optimization
techniques are also necessary for identifying the model parameters of
semiconductor devices because their models are very sophisticated. The
equations of such models contain about 100 parameters. Therefore, the
measurement and particularly identification of the full set of the model
parameters is very difficult. Optimization methods may be deterministic (like
Least-squares, Levenberg-Marquardt, and Gauss-Newton) or stochastic, like
Particle Swarm Optimization (PSO) or even genetic algorithms (GA).

In a typical extraction procedure, parameters are extracted sequentially, one at

a time or in small groups.. A small portion of the model and data from a
limited part of a device's operating range are used in extracting each parameter.
A linear least-squares model (LSM) fit is often used over each region. As an
example, a typical MOSFET extraction procedure might find values for the
threshold- and mobility related parameters in the linear region of operation,

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Numerical Simulation of Semiconductors & NanoDevices Chapter 7

and then makes use these values in finding the velocity saturation and channel
length modulation parameters.
There exist turn-key solutions for the device characterization and parameter
extraction process. For instance, the UTMOST from Silvaco (SimuCAD) and
IC-CAP, from Agilent, provide the platform to develop the parameter
extraction methodologies.

The aim of macro-modeling is to obtain a circuit model of an IC or a portion

of an IC with reduced complexity and accelerate simulation time. There several
methods to build SPICE-like models for complicated components, such as
power device. The structural (subcircuit) macro-modeling consists in
developing an equivalent circuit, built with standard SPICE devices, or analog
hardware description language (AHDL) modeling or analog behavioral models
(ABM). The Berkeley Short-channel IGFET Model (BSIM) is one of the most
successful compact models for MOSFET devices. BSIM exist in several
version (BSIM1, BSIM2, BSIM3, BSIM4, BSIM5, BSIM6, BSIMSOI, and
BSIM-MG).

Fig. 7-48. Snapshots of main windows in IC-CAP

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Prof. Dr. Muhammad EL-SAB3 Ain-shams University
Numerical Simulation of Semiconductors & NanoDevices Chapter 7

7-14. Problems

(1) Show how to perform the parameters extraction of a GaAs MOSFET

device, from real measurement data for the device y-parameters. Assume very
small RS and RD, to simplify the extraction procedure.

Hint:

Similarly, you can find simple relations for y22, y12 and y21, Comparing these
relations with measured values, you can evaluate the transistor parameters (gm,
Cgs, cgd, Csd and gd), in the above model.

(2) Show how to perform the parameters extraction of an IGBT device, from
real measurement data for the device h-parameters. Assume very small RS and
RD, to simplify the extraction procedure.

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Numerical Simulation of Semiconductors & NanoDevices Chapter 7

7-15. References
[1] Ebers, J.J. & Moll, J.L. (1954). Large Signal Behavior of Junction Transistors, Proc.
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[40] Wang, X.H., Gu, X., Gildenblat, G. & Bendix, P, (2003). Application of the Genetic
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[57] Lee, C.-S. & Wong, H.-S. P. (2015), Stanford Virtual-Source Carbon Nanotube Field-
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