PART-B

1)
a) Reduce the following Boolean expression (x’y’ + z)’ + z + xy + wz to a minimum number
of literals using Boolean Algebra Laws. (CO1, COMPREHENSION) (5 marks)

Answer:    
            = (x'y')'z' + z + xy + wz                    Demorgan Theorem (1 mark) 
            = [ (x + y) z' + z] + xy + wz                                 (1 mark) 
            = (z + z') (z + x + y) + xy + wz                            (1 mark) 
             = z + wz + x + xy + y                                          (1 mark) 
            =  z(1 + w) + x(1 + y) + y         =  x + y + z         (1 mark) 

b) Write HDL (Hardware Description Language) code for the following circuit (5marks)

module Circuit_Gates (output F1, F2, input A, B, C, D);          (5marks) 

      wire A_bar = !A; 
      wire B_bar = !B; 
     and (T1, B_bar, C); 
    and (T2, A_bar, B); 
    or (T3, A, T1); 
   xor (T4, T2, D); 
   or (F1, T3, T4); 
   or (F2, T2, D); 
  endmodule 
2.
a. Reduce the following Boolean expression A’B (D’+ C’D) + B (A + A’CD) to a minimum
number of literals using Boolean Algebra Laws. (CO1, COMPREHENSION) (5 marks)

 A'B (D' + C'D) + B (A + A'CD)       to one literal (5 marks) 

Answer = B(A'D' + A'C'D + A + A'CD)                 (1 mark) 
= B(A'D' + A + A'D (C + C')                                   (1 mark) 
 = B(A + A'(D' + D))                                               (1 mark) 
 = B (A + A')                                                          (1 mark) 
 = B                                                                        (1 mark) 
 
 
b. Write HDL (Hardware Description Language) code for the following circuit (5marks)

module Circuit_A (A, B, C, D, F); 
input A, B, C, D; 
output F; 
wire w, x, y, z, a, d; 
or (x, B, C, d); 
and (y, a ,C); 
and (w, z ,B); 
and (z, y, A); 
or (F, x, w); 
not (a, A); 
not (d, D); 
endmodule 
3 Minimize the following function in SOP minimal form using K-Maps: 
F(A, B, C, D) = SIGMA m(1, 2, 6, 7, 8, 13, 14, 15) + d(0, 3, 5, 12). Implement the Simplified
expression using Logic Gates (CO2, COMPREHENSION) 10M

Drawing the K-Map and Grouping     (5 Marks) 

  
 

Therefore, SOP minimal is,    (2 Marks) 

F = AC'D' + A'D + A'C + AB 
 
Implementation using LOGIC Gates  (3 Marks)

4 Simplify the following boolean function using K-Maps: F(A, B, C, D) = ∑ m(0, 1, 2, 3, 4,

5,10,11) + d(12, 13, 14, 15). Implement the Simplified expression using Logic Gates
10M

Drawing the K-Map and Grouping       (5 Marks) 

Circuit diagram 5 Marks
  

5 Using Map Entered Variable(MEV) technique implement the following Boolean function
using 8:1 multiplexer. F (A, B, C, D) = A’BD’ + ACD + B’CD + A’C’D (CO2,
COMPREHENSION) 10M

Solution: The given Boolean expression is not in standard SOP form. Let us

first convert this in standard SOP form: 
F (A, B, C, D) = A’B (C + C’) D’ + A (B + B’) CD + (A + A’) B’CD + A’ (B + B’) C’D 
= A’BCD’ + A’BC’D’ + ABCD + AB’CD + AB’CD + A’B’CD + A’BC’D +
A’B’C’D 
= 0110 + 0100 + 1111 + 1011 + 1011 + 0011 + 0101 + 0001 
= 6 + 4 + 15 + 11 + 11 + 3 + 5 + 1 
= m (1, 3, 4, 5, 6, 11, 15) 
For SOP Expression  4 Marks Truth Table with MEV Entries  3
Marks  
Circuit Diagram 3 Marks 

MEV map 
Sl. No.  A  B  C  D  f 
entry 
0  0  0  0  0  0 
D  D0 
1  0  0  0  1  1 
2  0  0  1  0  0 
D  D1 
3  0  0  1  1  1 
4  0  1  0  0  1 
1  D2 
5  0  1  0  1  1 
6  0  1  1  0  1 
D’  D3 
7  0  1  1  1  0 
8  1  0  0  0  0 
0 D4 
9  1  0  0  1  0 
10  1  0  1  0  0 
D  D5 
11  1  0  1  1  1 
12  1  1  0  0  0 
0  D6 
13  1  1  0  1  0 
14  1  1  1  0  0 
D  D7 
15  1  1  1  1  1 
6 Analyze the given combinational circuit. 10M
a) Write the Boolean functions for the 4 output in terms of the input variables.
b) If the circuit is described in a truth table, how many rows and columns would there be in the
table
8 A Majority circuit is a combinational circuit whose output is equal to 1 if the input variables
have more 1s than 0s. The output is 0 otherwise. Design a 3 bit input majority combinational
circuit by finding the circuit’s truth table, Boolean equation and a logic diagram. 10M
9 Explain Shift Register and its 4 configurations with block diagram. 10 M
SOLUTION:
SHIFT REGISTER EXPLAINATION 2M
4 CONFIGURATIONS 8M
10 Design and Explain a 5-bit Ring and Johnson Counter using D flip-flops. 10M
SOLUTION:
RING COUNTER DIAGRAM 5M
JOHNSON COUNTER DIAGRAM 5M

PART-C

1 Simplify the following Boolean function and obtain the minimal cover using Quin-McCluskey
method f(a, b, c, d) = ∑m(2,35,7,10,13)+d(4,6,8,9,14,15) 12M

Truth table: (2 Marks) Implicants (Order 0): Implicants (Order 1):

a b c d y (2 Marks) (2 Marks)
0: 0 0 0 0 0 a b c d a b c d
1: 0 0 0 1 0 2: 0 0 1 0 → 2, 3: 0 0 1 - →
2: 0 0 1 0 1 3: 0 0 1 1 → 2, 6: 0 - 1 0 →
3: 0 0 1 1 1 4: 0 1 0 0 → 2, 10: - 0 1 0 →
4: 0 1 0 0 × 5: 0 1 0 1 → 3, 7: 0 - 1 1 →
5: 0 1 0 1 1 6: 0 1 1 0 → 4, 5: 0 1 0 - →
6: 0 1 1 0 × 7: 0 1 1 1 → 4, 6: 0 1 - 0 →
7: 0 1 1 1 1 8: 1 0 0 0 → 5, 7: 0 1 - 1 →
8: 1 0 0 0 × 9: 1 0 0 1 → 5, 13: - 1 0 1 →
9: 1 0 0 1 × 10 6, 7: 0 1 1 - →
1 0 1 0 →
10 : 6, 14: - 1 1 0 →
1 0 1 0 1
: 13 7, 15: - 1 1 1 →
1 1 0 1 →
11 1 0 1 1 0 : 8, 9: 1 0 0 - (×)
 : 14 8, 10: 1 0 - 0 ✓
1 1 1 0 →
12
1 1 0 0 0
: 9, 13: 1 - 0 1 ✓
: 15 10,
1 1 1 1 → 1 - 1 0 →
13 : 14:
1 1 0 1 1
: 13,
14 1 1 - 1 →
1 1 1 0 × 15:
: 14,
15 1 1 1 - →
1 1 1 1 × 15:
:
Implicants (Order 2):
(2 Marks)
a b c d
2, 3, 6, 7: 0 - 1 - ✓
2, 6, 10, 14: - - 1 0 ✓
4, 5, 6, 7: 0 1 - - ✓
5, 7, 13, 15: - 1 - 1 ✓
6, 7, 14, 15: - 1 1 - ✓

Prime implicant chart: (2 Marks)

a b c d 2 3 5 7 10 13
2, 3, 6, 7: 0 - 1 - ○ ● ○ (a’c)
2, 6, 10,
- - 1 0 ○ ○ (cd’)
14:
4, 5, 6, 7: 0 1 - - ○ ○ (a’b)
5, 7, 13,
- 1 - 1 ○ ○ ○ (bd)
15:
6, 7, 14,
- 1 1 - ○ (bc)
15:
8, 10: 1 0 - 0 ○ (ab’d’)
9, 13: 1 - 0 1 ○ (ac’d)
Extracted essential prime implicants: (a’c)
Reduced prime implicant chart (Iteration 0):
a b c d 5 10 13
2, 6, 10,
- - 1 0 ● (cd’)
14:
5, 7, 13,
- 1 - 1 ● ● (bd)
15:
Extracted essential prime implicants: (bd), (cd’)
Minimal boolean expression: (2 Marks)
y = (a’c) + (bd) + (cd’)

2 Simplify the following Boolean function and obtain the minimal cover using Quin-McCluskey
method f(a, b, c, d) = ∑m(1,4,11,13)+d(2,3,6,8,10,14) 12M

Truth table: (2 Marks) Implicants (Order 0): Implicants (Order 1): (2 Marks)
 a b c d y (2 Marks) a b c d
0: 0 0 0 0 0 a b c d 1, 3: 0 0 - 1 ✓
1: 0 0 0 1 1 1: 0 0 0 1 → 2, 3: 0 0 1 - →
2: 0 0 1 0 × 2: 0 0 1 0 → 2, 6: 0 - 1 0 →
3: 0 0 1 1 × 3: 0 0 1 1 → 2, 10: - 0 1 0 →
4: 0 1 0 0 1 4: 0 1 0 0 → 3, 11: - 0 1 1 →
5: 0 1 0 1 0 6: 0 1 1 0 → 4, 6: 0 1 - 0 ✓
6: 0 1 1 0 × 8: 1 0 0 0 → 6, 14: - 1 1 0 →
7: 0 1 1 1 0 10 8, 10: 1 0 - 0 (×)
1 0 1 0 →
:
8: 1 0 0 0 × 10,
11 1 0 1 - →
9: 1 0 0 1 0 1 0 1 1 → 11:
:
10 10,
1 0 1 0 × 13 1 - 1 0 →
: 1 1 0 1 ✓ 14:
:
11
1 0 1 1 1 14
: 1 1 1 0 → Implicants (Order 2): (2 Marks)
:
12 a b c d
1 1 0 0 0
: 2, 3, 10,
- 0 1 - ✓
13 11:
1 1 0 1 1
: 2, 6, 10,
- - 1 0 (×)
14 14:
1 1 1 0 ×
:
15
1 1 1 1 0
:

Prime implicant chart: (2 Marks)

a b c d 1 4 11 13
2, 3, 10,
- 0 1 - ● (b’c)
11:
1, 3: 0 0 - 1 ● (a’b’d)
4, 6: 0 1 - 0 ● (a’bd’)
13: 1 1 0 1 ● (abc’d)

Extracted essential prime implicants: (a’b’d), (a’bd’), (b’c), (abc’d)

Minimal boolean expression: (2 Marks)
y = (a’b’d) + (a’bd’) + (b’c) + (abc’d)

3 Analyze the sequential circuit shown below by obtaining State Equations, State Transition
Table and State Diagram. 12M
The behavior of the circuit is determined by the following Boolean expressions:  
(4 Ma
rks) 
    Z = x * Q1 
    D1 = x' + Q1 
    D2 = x * Q2' + x' * Q1' 
 
State table for the sequential circuit ( 4 Marks) 
Present State  Next State  Output 
Q1Q2    X  Q1Q2        Z   
     
00    0  0 
11 
00    1  0 
01 
01    0  0 
11 
01    1  0 
00   
10    0  0   
10 
10    1  0 
11 
11    0  1 
10 
11    1  1 
10   
   
 
   
 
 
The state diagram for the sequential circuit  ( 4 Marks) 
 
 
4 Analysis the sequential circuit shown below by obtaining State Equations, State Transition
Table and State Diagram. 12M

The flip-flop input equations are: ( 4 Marks) 

 
DA = X xor B'  
DB = X + A 
Z = A xor B 
 
State table for the sequential circuit ( 4 Marks) 
Present State  Next State  Output 
Q1Q2    X  Q1Q2        Z   
     
 00    0  0 
10 
00    1  0 
01 
01    0  1 
00 
01    1  1 
11   
10    0  0   
01 
10    1  0 
11 
11    0  1 
11 
11    1  1 
01   
   
 
   
 
 
The state diagram for the sequential circuit (4 Marks) 

 
 

5 Design a synchronous sequential circuit for the state diagram shown below. Obtain State
Transition Table, Flip Flop Input equations and Circuit diagram. The type of flip-flop to be used
is J-K Flip Flop. 12M

State table of the circuit (4 Marks) 

 Present State  Input  Next State  Flip-flop Inputs 
Q0 Q1  x  Q0 Q1  J0K0  J1K1 
       

0 0  0  0 0  0 X  0 X 
0 0  1  0 1  0 X  1 X 
0 1  0  1 0  1 X  X 1 
0 1  1  0 1  0 X  X 0 
1 0  0  1 0  X 0  0 X 
1 0  1  1 1  X 0  1 X 
1 1  0  1 1  X 0  X 0 
1 1  1  0 0  X 1  X 1 
       
  
The information from the truth table is plotted on the Karnaugh maps  (4 Marks) 
  
 
  
The flip-flop input functions are derived: 
J0 = Q1 * x'        K0 = Q1 * x 
J1 = x                 K1 = Q0' * x' + Q0 * x   =   Q0  x 

The logic diagram  (4 Marks) 

 
6. Design a synchronous sequential circuit for the state diagram shown below. Obtain State
Transition Table, Flip Flop Input equations and Circuit diagram. The type of flip-flop to be use is
D FLIP FLOP 12M