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Tutorial on how to create an op-amp in Cadence

This tutorial aims to outline some the basic principles of design, simulation and layout of analogue circuits in particular op - amps.

All directions to specific options in ADE refer to ADE-L (unless stated otherwise) as any option available in ADE-L should also be
available in the more advanced versions of ADE, although not necessarily in the same place!

This tutorial uses components from the PRIMLIB from the process C35B3C3 from AMS, but the principles and method involved should
hold true for any silicon process on Cadence.

If you want to try this tutorial as an example, try to design an op-amp which meets the specification in the next section.

Typical op-amp specification

GBW >2MHz

Phase margin >60° unloaded

Phase Margin >40° into 10pF load

Operating temperature -40°C to 120°C

Power supply 4.5V to 5.5V

Input offset <20mV

Slew rate > 5V/µs

DC input bias 2 to 3V

Input signal range upto 1Vrms

Current bias 1.5 to 2.5µA

Current consumption <50µA

DC gain >90dB

PSRR >100dB

Nb. The op-amp shown in this tutorial does not meet this specification

Schematic
First create a new schematic cell for the op-amp. To this cell 6 pins need to be added, the two power supplies, the two inputs, the
output and, less obviously, a current input. I shall name the pins as follows VPA, VNA, +, -, OUT and ISNK2u.

Note that the current input name indicates both direction and size of the current input, ie that it should be driven by a 2µA current sink.
I find that this naming convention of currents is good practise as it makes it easy to see through the hierarchy whether the currents are
wired up correctly. Also, the name of the power supplies have an “A” to denominate that they should be connected to the analogue
power supply, as many chips have separate analogue and digital power supplies to minimise noise transferral.

Next, the circuit of the op-amp should be designed. The schematic below shows a typical simple op-amp. The transistors used for
current matching should be long for good matching and do not need to be that wide. The transistors in the differential pair should be
wide and short for good voltage matching.

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The capacitor is used to create a dominant pole to ensure that the op-amp is stable in a closed loop.

Create a symbol then edit as appropriate.

Then, to test the performance of the op-amp a test bench needs to be created, as shown below. Note that for SOI processes the test
bench will need a handle wafer connection, often called “HWnet!” which can be implemented as shown in this test bench, although
since this particular op-amp is designed in a bulk process it isn't necessary. At this point, if you know the load the op-amp will be
driving, you can add it to the test bench.

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Simulation
To measure the performance of the op-amp, a number of simulations can be run, all of which are available under “Analyses” in ADE.
Multiple simulations using different parameters can be run using the parametric analysis to save time. All simulations, unless stated
otherwise, use the test bench circuit shown above.

The first simulation to be run should be a DC simulation where the amplifier can be checked across the corners set in its specification.
These corners could be various parameters such as: temperature, power supply voltage, process variation etc. By selecting in ADE
”>Results>Annotate>DC node voltages” and ”>Results>Annotate>DC operating points” after the DC simulation whilst viewing the op-amp
schematic the operating points of the transistors can be veiwed. (nb the annotate commands only apply to the level of heirarchy open
so you need to be inside the op amp before selecting them). The schematic below shows an example of what you should get.

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Then, the op amp should be checked that for all corners that it has a sensible DC operating point, ie current mirrors mirroring
approximately the correct current, all transistors (except the differential pair) with vgs>vth, V(+) approximately equal to V(-) etc. If any
of the subsequent simulations do not give sensible results after schematic changes, it is worth checking the DC operating conditions
again, for example, if the current mirrors are made too long they will stop working due to inadequate supply voltage. At this point, the
difference between the input voltages should be observed, as this is the DC component of the input offset, DC matching will add to this,
so if this is already high, consider increasing the gain by lengthening the current mirrors, widening the input transistors, increasing the
current through the differential pair etc. After the DC analysis, remember to annotate “Design Defaults” to get the original component
parameters back.

DC matching is, unfortunately, not supported by the AMS process used for this example. If it did work, it would be possible to see the
effects of matching on the input offset and output. If the matching is not good enough, the matching analysis should state how much
each component affects the matching in the log file. If the worst offender is in a current mirror, try increasing the length of the
transitors in the mirror. If the component with the largest effect on matching is the differential pair, try making them wider. Any
variation in the input voltage due to DC matching should be added to the DC input offset as calculated by the DC simulation for the DC
operating point to give a total input offset.

It is also possible to find out the matching using a Monte-Carlo analysis, however ADE-L does not support this. I will add a separate
tutorial on how to use the Monte-Carlo analysis using a simpler example.

For a stability analysis, you need to set the “Probe Instance” in the analysis window as the voltage source in the feedback loop, in this
case “V1”. When you run the simulation, it will give you a phase margin, gain margin and their relevant frequencies in the log window. If
there are no results, try increasing the range of the frequency sweep. It should also be noted that the “stb” analysis does not like
working from 0Hz, put in 0.1Hz, that is near enough DC!

It is probably more useful to have these results set up as outputs. To do this go to >Results>Direct Plot>Main Form. Here you can select
to plot “Loop Gain”, “Magnitude and Phase”, “dB20”, and if you select the “Add To Outputs”, it will be in the outputs for subsequent
simulations. Unfortunately, the “Add To Outputs” option does not appear to work for anything other than “Loop Gain”, but there is
another way. If you go to >Tools>Results Browser, it will open up in the bottom left of the plot window. If you click on “stb_margin” it

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will open up the stability summary, as seen in the log file. If you right click on any of the 4 results, you can select calculator to get the
expression for this result in the calculator. Then, if you open up the outputs and create a new expression, then if you click “Get
Expression”, it will add the expression from the calculator. I suggest then to give it a sensible name, as the calculator expressions are
often long and unclear what they mean, and then (importantly!) click “Add” before clicking OK.

Now you can observe the phase margin and phase margin frequency across corners using a parametric analysis. If you want the DC gain,
send the signal “loopGain” from the “stb” folder in the results browser to the Calculator. Enable the function panel by clicking the
button labelled “fn” below the box in which the signal is displayed in the calculator. In the function panel search for “value” in the
functions and select it. In the “Interpolate At” box, put 0.1 for 0.1Hz (the lowest frequency you put into the sweep range for the stability
analysis) and press “OK”, then select the “dB20” function to get it in decibels, then you can add this to your outputs, as before.
Increasing the capacitance on the output transistor decreases the phase margin frequency (ie GBW) and increases the phase margin
and has no effect on the DC gain. I will leave the effects of changing other components and currents up to you to find out.

AC analysis can be used to achieve the same results as stability analysis, but this requires a different test bench with an “ac break”
replacing the voltage source in the feedback circuit. An “ac break” effectively blocks AC but allows DC to pass meaning that the op-amp
can be correctly biased in DC yet you can see the open loop response of it. Below is shown a typical “ac break” circuit.

Here is the new test bench.

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Note that the input to the op-amp has an AC magnitude of 1 (“acm=1”), whilst none of the other sources do. If you wanted to test PSRR,
you could put an AC magnitude on the power supply, V0. Before you run the simulation, you need to make sure you save the output, but
don't plot it. After running, open the results browser and select the ac folder. Send the output “out” to the calculator, use the “dB20”
function on it to get the loop gain and add to the outputs. Likewise, you can use the “phase” function on the output (remember to
remove the “dB20”).

To get the phase margin and the phase margin frequency, first get the loop gain on the calculator, then use the “cross” function with a
“Threshold Value” of 0 to get the phase margin frequency. To get the phase margin value, use the “value” function on the phase
function calculated earlier. In the “Interpolate At”, put in the function for phase margin frequency, press “OK”, then add to outputs.
You'll have to add or subtract 180° to get the phase margin, this should be obvious from the phase plot.

To discover the input signal range, a transient analysis can be used with different sized input signals. To discover the maximum slew
rate, it is perhaps easier to replace the input sinusoid signal with a pwl source, where you can change the slew rate of the input and see
if the output follows.

Layout
For this section on layout I will not cover the full layout of my op-amp as the actual final layout will be different for each op-amp, I will
merely cover the salient points of what should be done to achieve a good layout.

The first thing to do is to add dummies and comments to the op-amp schematic, as shown below. Any current dummy should have a pair
of minimum width dummies, one for each end of the current mirror. If the current mirror is to be split up into 2 rows/columns, then 4
are required etc. To avoid warnings about unconnected nets a “noConn” from the “basic” library is added to each dummy. (nb, there
needs to be as many “noConn” as dummies, ie MN1<1:2> connects to I0<1:2>, where I0 is the “noConn”, otherwise, the loose terminals of
the dummies get connected together).

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It is best to comment each current mirror as “matched”, as shown, as in practise it won't necessarily be you who lays out your circuit.

For the differential pair, if they are each single transistors you should split them up into two half width transitors and make a comment
saying that they should be laid out in a quad.

To show what these comments mean, I will show the arrangement of transistors in a typical mirror or quad, first the mirror:

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Note that the different transistors are interleaved and have a common centre to compensate if there is a process gradient across the
chip. The dummies on the outsideare so that the outside transistors have a similar environment to transistors inside the mirror, ie a
transistor on each side.

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The quad, as shown above, again has a common centre. Dummies are not necessarily required as all transistors experience the same,
empty on one side, transistor on the other. Note that I have overlapped contacts to save space.

Although I haven't drawn the wiring on the above examples, it should be noted that the current should go through all the transistors in
the same direction and that wiring over matched components should be avoided. If wiring over matched components can not be
avoided, the paths and connections over each component should be as similar as possible and not noisy. These main principles of
common centre, dummies and wiring apply to any array of components that is matched.

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